From 169ee53b79318cba0ad2cd331151510a03f53267 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 20 Mar 2021 22:53:17 -0600
Subject: [PATCH] [Benchmark] Add missing modules to VTR benchmarks

---
 .../benchmarks/vtr_benchmark/raygentop.v      | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/openfpga_flow/benchmarks/vtr_benchmark/raygentop.v b/openfpga_flow/benchmarks/vtr_benchmark/raygentop.v
index 2aaeec7a6..0f4a66b43 100755
--- a/openfpga_flow/benchmarks/vtr_benchmark/raygentop.v
+++ b/openfpga_flow/benchmarks/vtr_benchmark/raygentop.v
@@ -2974,3 +2974,30 @@ module fifo3 (datain, writeen, dataout, shiften, globalreset, clk);
     end 
  endmodule
 
+//---------------------------------------
+// A single-port 256x21bit RAM 
+// This module is tuned for VTR's benchmarks
+//---------------------------------------
+module single_port_ram (
+	input clk,
+	input we,
+	input [7:0] addr,
+	input [20:0] data,
+	output [20:0] out );
+
+	reg [20:0] ram[255:0];
+	reg [20:0] internal;
+
+	assign out = internal;
+
+	always @(posedge clk) begin
+		if(wen) begin
+			ram[addr] <= data;
+		end
+
+		if(ren) begin
+			internal <= ram[addr];
+		end
+	end
+
+endmodule