diff --git a/openfpga_flow/openfpga_simulation_settings/fixed_shift_register_sim_openfpga.xml b/openfpga_flow/openfpga_simulation_settings/fixed_shift_register_sim_openfpga.xml
new file mode 100644
index 000000000..740e00a1c
--- /dev/null
+++ b/openfpga_flow/openfpga_simulation_settings/fixed_shift_register_sim_openfpga.xml
@@ -0,0 +1,42 @@
+<!-- Simulation Setting for OpenFPGA framework
+     This file will use automatic inference for any settings
+     including:
+     - auto select the number of simulation cycles
+     - auto select the simulation clock frequency from VPR results
+  -->
+<openfpga_simulation_setting>
+  <clock_setting>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <programming frequency="100e6">
+      <clock name="bl_shift_register_clk" port="bl_sr_clk[0:0]" frequency="1.5e9" is_shift_register="true"/>
+      <clock name="wl_shift_register_clk" port="wl_sr_clk[0:0]" frequency="1.5e9" is_shift_register="true"/>
+    </programming>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>