riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added verbose option in VVP output

This commit is contained in:
Ganesh Gore 2019-09-17 22:09:37 -06:00
parent 678e3181ba
commit 169732ccc1
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
openfpga_flow/scripts/run_fpga_flow.py
View File

@ -854,7 +854,7 @@ def run_netlists_verification():
command += [tb_top_autochecked] command += [tb_top_autochecked]
run_command("iverilog_verification", "iverilog_output.txt", command) run_command("iverilog_verification", "iverilog_output.txt", command)
vvp_command = ["vvp", "-Ns", compiled_file] vvp_command = ["vvp", "-Nvs", compiled_file]
output = run_command("vvp_verification", "vvp_sim_output.txt", vvp_command) output = run_command("vvp_verification", "vvp_sim_output.txt", vvp_command)
if "Succeed" in output: if "Succeed" in output:
logger.info("VVP Simulation Successful") logger.info("VVP Simulation Successful")