From 3c9e4919b4d89458855c0ea6a1772bb11dfbdf18 Mon Sep 17 00:00:00 2001 From: Lalit Sharma Date: Fri, 18 Dec 2020 03:18:46 -0800 Subject: [PATCH] Updating variable name in ys to call BLIF output file. --- openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys | 2 +- .../tasks/quicklogic_tests/flow_test/config/task.conf | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys b/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys index ce527daa0..314a32324 100644 --- a/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +++ b/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys @@ -2,5 +2,5 @@ # Read verilog files ${READ_VERILOG_FILE} -synth_quicklogic -blif ${TOP_MODULE}.eblif -family ap3 -vpr -openfpga -top ${TOP_MODULE} +synth_quicklogic -blif ${OUTPUT_BLIF} -family ap3 -vpr -openfpga -top ${TOP_MODULE} diff --git a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf index 0b189c1b9..59969ccae 100644 --- a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf @@ -16,19 +16,19 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v [SYNTHESIS_PARAM] bench0_top = counter -bench0_chan_width = 300 +bench0_chan_width = 100 bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]