From 1ef0898f41adaeff8f762e34fe0a79cfebe1e4d4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 12 Oct 2020 12:31:51 -0600 Subject: [PATCH 1/8] [Tool] Now users can specify a different fabric netlist when generating Verilog testbench --- openfpga/src/base/openfpga_verilog.cpp | 2 ++ openfpga/src/base/openfpga_verilog_command.cpp | 4 ++++ openfpga/src/fpga_verilog/verilog_api.cpp | 1 + openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp | 8 +++++++- openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h | 1 + openfpga/src/fpga_verilog/verilog_testbench_options.cpp | 9 +++++++++ openfpga/src/fpga_verilog/verilog_testbench_options.h | 6 ++++++ 7 files changed, 30 insertions(+), 1 deletion(-) diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp index 0c6367fc5..69c0b60d4 100644 --- a/openfpga/src/base/openfpga_verilog.cpp +++ b/openfpga/src/base/openfpga_verilog.cpp @@ -65,6 +65,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { CommandOptionId opt_output_dir = cmd.option("file"); + CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path"); CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path"); CommandOptionId opt_print_top_testbench = cmd.option("print_top_testbench"); CommandOptionId opt_fast_configuration = cmd.option("fast_configuration"); @@ -79,6 +80,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx, */ VerilogTestbenchOption options; options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir)); + options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist)); options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark)); options.set_print_formal_verification_top_netlist(cmd_context.option_enable(cmd, opt_print_formal_verification_top_netlist)); options.set_print_preconfig_top_testbench(cmd_context.option_enable(cmd, opt_print_preconfig_top_testbench)); diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp index 89c4e27e3..116d2842c 100644 --- a/openfpga/src/base/openfpga_verilog_command.cpp +++ b/openfpga/src/base/openfpga_verilog_command.cpp @@ -72,6 +72,10 @@ ShellCommandId add_openfpga_write_verilog_testbench_command(openfpga::Shell Date: Mon, 12 Oct 2020 12:36:24 -0600 Subject: [PATCH 2/8] [Documentation] Update for new options in fpga-verilog --- .../openfpga_shell/openfpga_commands/fpga_verilog_commands.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index 24dc3a603..667acb7c2 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -29,6 +29,8 @@ write_verilog_testbench - ``--file`` or ``-f`` The output directory for all the testbench netlists. We suggest the use of same output directory as fabric Verilog netlists + - ``--fabric_netlist_file_path`` Specify the fabric Verilog file if they are not in the same directory as the testbenches to be generated. If not specified, OpenFPGA will assume that the fabric netlists are the in the same directory as testbenches and assign default names. + - ``--reference_benchmark_file_path`` Must specify the reference benchmark Verilog file if you want to output any testbenches - ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal. From e510e79c1250c4e6ce60fd3fdd9dbf2f9b31d4de Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 12 Oct 2020 12:42:43 -0600 Subject: [PATCH 3/8] [Flow] Add openfpga shell example script to use fabric netlist option --- ...tom_fabric_netlist_example_script.openfpga | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga new file mode 100644 index 000000000..f228d3c7a --- /dev/null +++ b/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga @@ -0,0 +1,74 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file ./TESTBENCH --fabric_netlist_file_path ${OPENFPGA_FABRIC_NETLIST_FILE} --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory From 9e1fd300dc062f442f44d503c458a77dbd88dfac Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 12 Oct 2020 12:47:58 -0600 Subject: [PATCH 4/8] [Test] Add test case for customized location of fabric netlists --- .../config/task.conf | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf b/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf new file mode 100644 index 000000000..943259966 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf @@ -0,0 +1,35 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_fabric_netlist_file=./SRC/fabric_netlists.v + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] From 8941e3861363278c02c1282bf4e7cf0e63d8dcf1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 12 Oct 2020 12:50:08 -0600 Subject: [PATCH 5/8] [Test] Enable verification in the new test case --- .../basic_tests/custom_fabric_netlist_location/config/task.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf b/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf index 943259966..bf54ec66a 100644 --- a/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf @@ -33,3 +33,4 @@ bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2 bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From e59377a3ec7b99e53a837e1c2834ccaeb080b018 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 12 Oct 2020 12:52:01 -0600 Subject: [PATCH 6/8] [Flow] bug fix in the sample script for fabric netlist customization --- .../custom_fabric_netlist_example_script.openfpga | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga index f228d3c7a..577ed9ce4 100644 --- a/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga @@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./FABRIC_NETLIST --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -55,7 +55,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./TESTBENCH --fabric_netlist_file_path ${OPENFPGA_FABRIC_NETLIST_FILE} --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping +write_verilog_testbench --file ./SRC --fabric_netlist_file_path ${OPENFPGA_FABRIC_NETLIST_FILE} --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here From dc68c52d0a41c215e414ab6cc008676e17a95792 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 12 Oct 2020 12:53:34 -0600 Subject: [PATCH 7/8] [Test] Now use a light architecture to speed up the test case runtime --- .../custom_fabric_netlist_location/config/task.conf | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf b/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf index bf54ec66a..cd23bc3f7 100644 --- a/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf @@ -17,12 +17,12 @@ fpga_flow=vpr_blif [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_fabric_netlist_file=./SRC/fabric_netlists.v +openfpga_fabric_netlist_file=./FABRIC_NETLIST/fabric_netlists.v [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif From 6b6c018945f765b246d60791b16370972d3949ea Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 12 Oct 2020 12:54:51 -0600 Subject: [PATCH 8/8] [Test] Add the new test case to CI --- .travis/basic_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 8f5961618..474667b84 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -63,6 +63,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric --deb echo -e "Testing Verilog testbench generation only"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_testbench --debug --show_thread_logs +echo -e "Testing separated Verilog fabric netlists and testbench locations"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/custom_fabric_netlist_location --debug --show_thread_logs + echo -e "Testing user-defined simulation settings: clock frequency and number of cycles"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_simulation_settings --debug --show_thread_logs