diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh
index 8f5961618..474667b84 100755
--- a/.travis/basic_reg_test.sh
+++ b/.travis/basic_reg_test.sh
@@ -63,6 +63,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric --deb
 echo -e "Testing Verilog testbench generation only";
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_testbench --debug --show_thread_logs
 
+echo -e "Testing separated Verilog fabric netlists and testbench locations";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/custom_fabric_netlist_location --debug --show_thread_logs
+
 echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_simulation_settings --debug --show_thread_logs
 
diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
index 24dc3a603..667acb7c2 100644
--- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
+++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
@@ -29,6 +29,8 @@ write_verilog_testbench
 
   - ``--file`` or ``-f`` The output directory for all the testbench netlists. We suggest the use of same output directory as fabric Verilog netlists
 
+  - ``--fabric_netlist_file_path`` Specify the fabric Verilog file if they are not in the same directory as the testbenches to be generated. If not specified, OpenFPGA will assume that the fabric netlists are the in the same directory as testbenches and assign default names.
+
   - ``--reference_benchmark_file_path`` Must specify the reference benchmark Verilog file if you want to output any testbenches
 
   - ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal. 
diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp
index 0c6367fc5..69c0b60d4 100644
--- a/openfpga/src/base/openfpga_verilog.cpp
+++ b/openfpga/src/base/openfpga_verilog.cpp
@@ -65,6 +65,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
                             const Command& cmd, const CommandContext& cmd_context) {
 
   CommandOptionId opt_output_dir = cmd.option("file");
+  CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path");
   CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
   CommandOptionId opt_print_top_testbench = cmd.option("print_top_testbench");
   CommandOptionId opt_fast_configuration = cmd.option("fast_configuration");
@@ -79,6 +80,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
    */
   VerilogTestbenchOption options;
   options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
+  options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist));
   options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
   options.set_print_formal_verification_top_netlist(cmd_context.option_enable(cmd, opt_print_formal_verification_top_netlist));
   options.set_print_preconfig_top_testbench(cmd_context.option_enable(cmd, opt_print_preconfig_top_testbench));
diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp
index 89c4e27e3..116d2842c 100644
--- a/openfpga/src/base/openfpga_verilog_command.cpp
+++ b/openfpga/src/base/openfpga_verilog_command.cpp
@@ -72,6 +72,10 @@ ShellCommandId add_openfpga_write_verilog_testbench_command(openfpga::Shell<Open
   shell_cmd.set_option_short_name(output_opt, "f");
   shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
 
+  /* Add an option '--fabric_netlist_file_path'*/
+  CommandOptionId fabric_netlist_opt = shell_cmd.add_option("fabric_netlist_file_path", false, "Specify the file path to the fabric Verilog netlist");
+  shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING);
+
   /* Add an option '--reference_benchmark_file_path'*/
   CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist");
   shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index fe5b76196..aa207787e 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -235,6 +235,7 @@ void fpga_verilog_testbench(const ModuleManager &module_manager,
   /* Generate a Verilog file including all the netlists that have been generated */
   print_verilog_testbench_include_netlists(src_dir_path,
                                            netlist_name,
+                                           options.fabric_netlist_file_path(),
                                            options.reference_benchmark_file_path());
 }
 
diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
index 93fdb2161..612c65557 100644
--- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
+++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
@@ -96,6 +96,7 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
  *******************************************************************/
 void print_verilog_testbench_include_netlists(const std::string& src_dir,
                                               const std::string& circuit_name,
+                                              const std::string& fabric_netlist_file,
                                               const std::string& reference_benchmark_file) {
   std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
 
@@ -116,7 +117,12 @@ void print_verilog_testbench_include_netlists(const std::string& src_dir,
 
   /* Include FPGA top module */
   print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
-  print_verilog_include_netlist(fp, src_dir + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME));
+  if (true == fabric_netlist_file.empty()) {
+    print_verilog_include_netlist(fp, src_dir + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME));
+  } else {
+    VTR_ASSERT_SAFE(false == fabric_netlist_file.empty());
+    print_verilog_include_netlist(fp, fabric_netlist_file);
+  }
   fp << std::endl;
 
   /* Include reference benchmark netlist only when auto-check flag is enabled */
diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
index c3952af85..0fdf2338b 100644
--- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
+++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
@@ -23,6 +23,7 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
 
 void print_verilog_testbench_include_netlists(const std::string& src_dir,
                                               const std::string& circuit_name,
+                                              const std::string& fabric_netlist_file,
                                               const std::string& reference_benchmark_file);
 
 void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
index d56037f81..8c009f823 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
+++ b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
@@ -14,6 +14,7 @@ namespace openfpga {
  *************************************************/
 VerilogTestbenchOption::VerilogTestbenchOption() {
   output_directory_.clear();
+  fabric_netlist_file_path_.clear();
   reference_benchmark_file_path_.clear();
   print_preconfig_top_testbench_ = false;
   print_formal_verification_top_netlist_ = false;
@@ -30,6 +31,10 @@ std::string VerilogTestbenchOption::output_directory() const {
   return output_directory_;
 }
 
+std::string VerilogTestbenchOption::fabric_netlist_file_path() const {
+  return fabric_netlist_file_path_;
+}
+
 std::string VerilogTestbenchOption::reference_benchmark_file_path() const {
   return reference_benchmark_file_path_;
 }
@@ -73,6 +78,10 @@ void VerilogTestbenchOption::set_output_directory(const std::string& output_dir)
   output_directory_ = output_dir;
 }
 
+void VerilogTestbenchOption::set_fabric_netlist_file_path(const std::string& fabric_netlist_file_path) {
+  fabric_netlist_file_path_ = fabric_netlist_file_path;
+}
+
 void VerilogTestbenchOption::set_reference_benchmark_file_path(const std::string& reference_benchmark_file_path) {
   reference_benchmark_file_path_ = reference_benchmark_file_path;
   /* Chain effect on other options: 
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.h b/openfpga/src/fpga_verilog/verilog_testbench_options.h
index 89d93b46e..72a64f494 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_options.h
+++ b/openfpga/src/fpga_verilog/verilog_testbench_options.h
@@ -23,6 +23,7 @@ class VerilogTestbenchOption {
     VerilogTestbenchOption();
   public: /* Public accessors */
     std::string output_directory() const;
+    std::string fabric_netlist_file_path() const;
     std::string reference_benchmark_file_path() const;
     bool fast_configuration() const;
     bool print_formal_verification_top_netlist() const;
@@ -42,6 +43,10 @@ class VerilogTestbenchOption {
      * If the file path is empty, the above testbench generation will not be enabled 
      */
     void set_reference_benchmark_file_path(const std::string& reference_benchmark_file_path);
+    /* The fabric netlist file path is an optional parameter 
+     * to allow users to specify a fabric netlist at another location
+     */
+    void set_fabric_netlist_file_path(const std::string& fabric_netlist_file_path);
     void set_print_formal_verification_top_netlist(const bool& enabled);
     /* The preconfig top testbench generation can be enabled only when formal verification top netlist is enabled */
     void set_print_preconfig_top_testbench(const bool& enabled);
@@ -52,6 +57,7 @@ class VerilogTestbenchOption {
     void set_verbose_output(const bool& enabled);
   private: /* Internal Data */
     std::string output_directory_;
+    std::string fabric_netlist_file_path_;
     std::string reference_benchmark_file_path_;
     bool fast_configuration_;
     bool print_formal_verification_top_netlist_;
diff --git a/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga
new file mode 100644
index 000000000..577ed9ce4
--- /dev/null
+++ b/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga
@@ -0,0 +1,74 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing #--verbose
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.xml --format xml
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./FABRIC_NETLIST --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file ./SRC --fabric_netlist_file_path ${OPENFPGA_FABRIC_NETLIST_FILE} --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+write_pnr_sdc --file ./SDC
+
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory
diff --git a/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf b/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf
new file mode 100644
index 000000000..cd23bc3f7
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf
@@ -0,0 +1,36 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_fabric_netlist_file=./FABRIC_NETLIST/fabric_netlists.v
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=