[FPGA-SPICE] Add SPICE subcircuit writer
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tangxifan
parent
82e137cbe4
commit
15df9b3893
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/********************************************************************
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* This file includes functions to write a SPICE module
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* based on its definition in Module Manager
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*
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* Note that SPICE writer functions are just an outputter for the
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* module definition.
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* You should NOT modify any content of the module manager
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* Please use const keyword to restrict this!
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*******************************************************************/
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#include <algorithm>
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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/* Headers from openfpgautil library */
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#include "openfpga_port.h"
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#include "openfpga_digest.h"
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#include "openfpga_naming.h"
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#include "module_manager_utils.h"
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#include "spice_writer_utils.h"
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#include "spice_subckt_writer.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Generate the name of a local wire for a undriven port inside SPICE
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* module
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*******************************************************************/
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static
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std::string generate_spice_undriven_local_wire_name(const ModuleManager& module_manager,
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const ModuleId& parent,
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const ModuleId& child,
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const size_t& instance_id,
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const ModulePortId& child_port_id) {
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std::string wire_name;
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if (!module_manager.instance_name(parent, child, instance_id).empty()) {
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wire_name = module_manager.instance_name(parent, child, instance_id);
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} else {
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wire_name = module_manager.module_name(parent) + std::string("_") + std::to_string(instance_id);
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wire_name += std::string("_");
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}
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wire_name += std::string("_undriven_");
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wire_name += module_manager.module_port(child, child_port_id).get_name();
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return wire_name;
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}
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/********************************************************************
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* Name a net for a local wire for a SPICE subckt
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* 1. If this is a local wire, name it after the <src_module_name>_<instance_id>_<src_port_name>
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* 2. If this is not a local wire, name it after the port name of parent module
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*
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* In addition, it will assign the pin index as well
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*
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* Restriction: this function requires each net has single driver
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* which is definitely always true in circuits.
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*******************************************************************/
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static
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BasicPort generate_spice_port_for_module_net(const ModuleManager& module_manager,
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const ModuleId& module_id,
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const ModuleNetId& module_net) {
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/* Check all the sink modules of the net,
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* if we have a source module is the current module, this is not local wire
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*/
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for (ModuleNetSrcId src_id : module_manager.module_net_sources(module_id, module_net)) {
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if (module_id == module_manager.net_source_modules(module_id, module_net)[src_id]) {
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/* Here, this is not a local wire, return the port name of the src_port */
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ModulePortId net_src_port = module_manager.net_source_ports(module_id, module_net)[src_id];
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size_t src_pin_index = module_manager.net_source_pins(module_id, module_net)[src_id];
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return BasicPort(module_manager.module_port(module_id, net_src_port).get_name(), src_pin_index, src_pin_index);
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}
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}
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/* Check all the sink modules of the net */
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for (ModuleNetSinkId sink_id : module_manager.module_net_sinks(module_id, module_net)) {
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if (module_id == module_manager.net_sink_modules(module_id, module_net)[sink_id]) {
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/* Here, this is not a local wire, return the port name of the sink_port */
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ModulePortId net_sink_port = module_manager.net_sink_ports(module_id, module_net)[sink_id];
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size_t sink_pin_index = module_manager.net_sink_pins(module_id, module_net)[sink_id];
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return BasicPort(module_manager.module_port(module_id, net_sink_port).get_name(), sink_pin_index, sink_pin_index);
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}
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}
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/* Reach here, this is a local wire */
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std::string net_name;
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/* Each net must only one 1 source */
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VTR_ASSERT(1 == module_manager.net_source_modules(module_id, module_net).size());
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/* Get the source module */
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ModuleId net_src_module = module_manager.net_source_modules(module_id, module_net)[ModuleNetSrcId(0)];
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/* Get the instance id */
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size_t net_src_instance = module_manager.net_source_instances(module_id, module_net)[ModuleNetSrcId(0)];
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/* Get the port id */
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ModulePortId net_src_port = module_manager.net_source_ports(module_id, module_net)[ModuleNetSrcId(0)];
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/* Get the pin id */
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size_t net_src_pin = module_manager.net_source_pins(module_id, module_net)[ModuleNetSrcId(0)];
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/* Load user-defined name if we have it */
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if (false == module_manager.net_name(module_id, module_net).empty()) {
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net_name = module_manager.net_name(module_id, module_net);
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} else {
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net_name = module_manager.module_name(net_src_module);
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net_name += std::string("_") + std::to_string(net_src_instance) + std::string("_");
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net_name += module_manager.module_port(net_src_module, net_src_port).get_name();
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}
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return BasicPort(net_name, net_src_pin, net_src_pin);
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}
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/********************************************************************
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* Print a SPICE wire connection
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* We search all the sinks of the net,
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* if we find a module output, we try to find the next module output
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* among the sinks of the net
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* For each module output (except the first one), we print a wire connection
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*******************************************************************/
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static
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void print_spice_subckt_output_short_connection(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& module_id,
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const ModuleNetId& module_net) {
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/* Ensure a valid file stream */
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VTR_ASSERT(true == valid_file_stream(fp));
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bool first_port = true;
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BasicPort src_port;
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/* We have found a module input, now check all the sink modules of the net */
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for (ModuleNetSinkId net_sink : module_manager.module_net_sinks(module_id, module_net)) {
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ModuleId sink_module = module_manager.net_sink_modules(module_id, module_net)[net_sink];
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if (module_id != sink_module) {
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continue;
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}
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/* Find the sink port and pin information */
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ModulePortId sink_port_id = module_manager.net_sink_ports(module_id, module_net)[net_sink];
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size_t sink_pin = module_manager.net_sink_pins(module_id, module_net)[net_sink];
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BasicPort sink_port(module_manager.module_port(module_id, sink_port_id).get_name(), sink_pin, sink_pin);
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/* For the first module output, this is the source port, we do nothing and go to the next */
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if (true == first_port) {
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src_port = sink_port;
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/* Flip the flag */
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first_port = false;
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continue;
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}
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/* We need to print a wire connection here */
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VTR_ASSERT(src_port.get_width() == sink_port.get_width());
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for (size_t ipin = 0; ipin < src_port.pins().size(); ++ipin) {
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BasicPort src_spice_pin(src_port.get_name(), src_port.pins()[ipin], src_port.pins()[ipin]);
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BasicPort sink_spice_pin(sink_port.get_name(), sink_port.pins()[ipin], sink_port.pins()[ipin]);
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print_spice_short_connection(fp,
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generate_spice_port(src_spice_pin),
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generate_spice_port(sink_spice_pin));
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}
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}
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}
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/********************************************************************
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* Print a SPICE wire connection
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* We search all the sources of the net,
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* if we find a module input, we try to find a module output
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* among the sinks of the net
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* If we find such a pair, we print a wire connection
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*******************************************************************/
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static
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void print_spice_subckt_local_short_connection(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& module_id,
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const ModuleNetId& module_net) {
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/* Ensure a valid file stream */
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VTR_ASSERT(true == valid_file_stream(fp));
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for (ModuleNetSrcId net_src : module_manager.module_net_sources(module_id, module_net)) {
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ModuleId src_module = module_manager.net_source_modules(module_id, module_net)[net_src];
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if (module_id != src_module) {
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continue;
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}
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/* Find the source port and pin information */
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print_spice_comment(fp, std::string("Net source id " + std::to_string(size_t(net_src))));
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ModulePortId src_port_id = module_manager.net_source_ports(module_id, module_net)[net_src];
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size_t src_pin = module_manager.net_source_pins(module_id, module_net)[net_src];
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BasicPort src_port(module_manager.module_port(module_id, src_port_id).get_name(), src_pin, src_pin);
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/* We have found a module input, now check all the sink modules of the net */
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for (ModuleNetSinkId net_sink : module_manager.module_net_sinks(module_id, module_net)) {
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ModuleId sink_module = module_manager.net_sink_modules(module_id, module_net)[net_sink];
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if (module_id != sink_module) {
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continue;
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}
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/* Find the sink port and pin information */
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print_spice_comment(fp, std::string("Net sink id " + std::to_string(size_t(net_sink))));
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ModulePortId sink_port_id = module_manager.net_sink_ports(module_id, module_net)[net_sink];
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size_t sink_pin = module_manager.net_sink_pins(module_id, module_net)[net_sink];
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BasicPort sink_port(module_manager.module_port(module_id, sink_port_id).get_name(), sink_pin, sink_pin);
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/* We need to print a wire connection here */
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VTR_ASSERT(src_port.get_width() == sink_port.get_width());
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for (size_t ipin = 0; ipin < src_port.pins().size(); ++ipin) {
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BasicPort src_spice_pin(src_port.get_name(), src_port.pins()[ipin], src_port.pins()[ipin]);
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BasicPort sink_spice_pin(sink_port.get_name(), sink_port.pins()[ipin], sink_port.pins()[ipin]);
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print_spice_short_connection(fp,
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generate_spice_port(src_spice_pin),
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generate_spice_port(sink_spice_pin));
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}
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}
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}
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}
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/********************************************************************
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* Print short connections inside a SPICE module
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* The short connection is defined as the direct connection
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* between an input port of the module and an output port of the module
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* This type of connection is not covered when printing SPICE instances
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* Therefore, they are covered in this function
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*
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* module
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* +-----------------------------+
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* | |
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* inputA--->|---------------------------->|--->outputB
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* | |
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* | |
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* | |
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* +-----------------------------+
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*******************************************************************/
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static
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void print_spice_subckt_local_short_connections(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& module_id) {
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/* Local wires come from the child modules */
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for (ModuleNetId module_net : module_manager.module_nets(module_id)) {
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/* We only care the nets that indicate short connections */
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if (false == module_net_include_local_short_connection(module_manager, module_id, module_net)) {
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continue;
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}
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print_spice_comment(fp, std::string("Local connection due to Wire " + std::to_string(size_t(module_net))));
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print_spice_subckt_local_short_connection(fp, module_manager, module_id, module_net);
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}
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}
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/********************************************************************
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* Print output short connections inside a SPICE module
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* The output short connection is defined as the direct connection
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* between two output ports of the module
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* This type of connection is not covered when printing SPICE instances
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* Therefore, they are covered in this function
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*
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* module
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* +-----------------------------+
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* |
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* src------>+--------------->|--->outputA
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* | |
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* | |
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* +--------------->|--->outputB
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* +-----------------------------+
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*******************************************************************/
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static
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void print_spice_subckt_output_short_connections(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& module_id) {
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/* Local wires come from the child modules */
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for (ModuleNetId module_net : module_manager.module_nets(module_id)) {
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/* We only care the nets that indicate short connections */
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if (false == module_net_include_output_short_connection(module_manager, module_id, module_net)) {
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continue;
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}
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print_spice_subckt_output_short_connection(fp, module_manager, module_id, module_net);
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}
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}
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/********************************************************************
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* Write a SPICE instance to a file
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* This function will name the input and output connections to
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* the inputs/output or local wires available in the parent module
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*
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* Parent_module
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* +-----------------------------+
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* | |
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* | +--------------+ |
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* | | | |
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* | | child_module | |
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* | | [instance] | |
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* | +--------------+ |
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* | |
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* +-----------------------------+
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*
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*******************************************************************/
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static
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void write_spice_instance_to_file(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& parent_module,
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const ModuleId& child_module,
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const size_t& instance_id) {
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/* Ensure a valid file stream */
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VTR_ASSERT(true == valid_file_stream(fp));
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/* Print instance name:
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* if we have an instance name, use it;
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* if not, we use a default name <name>_<num_instance_in_parent_module>
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*/
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std::string instance_head_line = "X ";
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if (true == module_manager.instance_name(parent_module, child_module, instance_id).empty()) {
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instance_head_line += generate_instance_name(module_manager.module_name(child_module), instance_id);
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} else {
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instance_head_line += module_manager.instance_name(parent_module, child_module, instance_id);
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}
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instance_head_line += " ";
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fp << instance_head_line;
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/* Port sequence: global, inout, input, output and clock ports, */
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bool fit_one_line = true;
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bool new_line = false;
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size_t pin_cnt = 0;
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for (int port_type = ModuleManager::MODULE_GLOBAL_PORT;
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port_type < ModuleManager::NUM_MODULE_PORT_TYPES;
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++port_type) {
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for (const auto& child_port_id : module_manager.module_port_ids_by_type(child_module, static_cast<ModuleManager::e_module_port_type>(port_type))) {
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BasicPort child_port = module_manager.module_port(child_module, child_port_id);
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/* Create the port name and width to be used by the instance */
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std::vector<BasicPort> instance_ports;
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for (size_t child_pin : child_port.pins()) {
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/* Find the net linked to the pin */
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ModuleNetId net = module_manager.module_instance_port_net(parent_module, child_module, instance_id,
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child_port_id, child_pin);
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BasicPort instance_port;
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if (ModuleNetId::INVALID() == net) {
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/* We give the same port name as child module, this case happens to global ports */
|
||||||
|
instance_port.set_name(generate_spice_undriven_local_wire_name(module_manager, parent_module, child_module, instance_id, child_port_id));
|
||||||
|
instance_port.set_width(child_pin, child_pin);
|
||||||
|
} else {
|
||||||
|
/* Find the name for this child port */
|
||||||
|
instance_port = generate_spice_port_for_module_net(module_manager, parent_module, net);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (true == new_line) {
|
||||||
|
std::string port_whitespace(instance_head_line.length() - 2, ' ');
|
||||||
|
fp << "+ " << port_whitespace;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (0 != pin_cnt) {
|
||||||
|
write_space_to_file(fp, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
VTR_ASSERT(1 == instance_port.get_width());
|
||||||
|
|
||||||
|
/* For single-bit port,
|
||||||
|
* we can print the port name directly
|
||||||
|
*/
|
||||||
|
bool omit_pin_zero = false;
|
||||||
|
if ((1 == instance_port.pins().size())
|
||||||
|
&& (0 == instance_port.get_lsb())) {
|
||||||
|
omit_pin_zero = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
fp << generate_spice_port(instance_port, omit_pin_zero);
|
||||||
|
|
||||||
|
/* Increase the counter */
|
||||||
|
pin_cnt++;
|
||||||
|
|
||||||
|
/* Currently we limit 10 ports per line to keep a clean netlist */
|
||||||
|
new_line = false;
|
||||||
|
if (10 == pin_cnt) {
|
||||||
|
pin_cnt = 0;
|
||||||
|
fp << std::endl;
|
||||||
|
new_line = true;
|
||||||
|
fit_one_line = false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Print module name:
|
||||||
|
* if port print cannot fit one line, we create a new line for the module for a clean format
|
||||||
|
*/
|
||||||
|
if (false == fit_one_line) {
|
||||||
|
fp << std::endl;
|
||||||
|
fp << "+";
|
||||||
|
}
|
||||||
|
write_space_to_file(fp, 1);
|
||||||
|
fp << module_manager.module_name(child_module);
|
||||||
|
|
||||||
|
/* Print an end to the instance */
|
||||||
|
fp << std::endl;
|
||||||
|
}
|
||||||
|
|
||||||
|
/********************************************************************
|
||||||
|
* Write a SPICE sub-circuit to a file
|
||||||
|
* This is a key function, maybe most frequently called in our SPICE writer
|
||||||
|
* Note that file stream must be valid
|
||||||
|
*******************************************************************/
|
||||||
|
void write_spice_subckt_to_file(std::fstream& fp,
|
||||||
|
const ModuleManager& module_manager,
|
||||||
|
const ModuleId& module_id) {
|
||||||
|
|
||||||
|
VTR_ASSERT(true == valid_file_stream(fp));
|
||||||
|
|
||||||
|
/* Ensure we have a valid module_id */
|
||||||
|
VTR_ASSERT(module_manager.valid_module_id(module_id));
|
||||||
|
|
||||||
|
/* Print module declaration */
|
||||||
|
print_spice_subckt_definition(fp, module_manager, module_id);
|
||||||
|
|
||||||
|
/* Print an empty line as splitter */
|
||||||
|
fp << std::endl;
|
||||||
|
|
||||||
|
/* Print an empty line as splitter */
|
||||||
|
fp << std::endl;
|
||||||
|
|
||||||
|
/* Print local connection (from module inputs to output! */
|
||||||
|
print_spice_comment(fp, std::string("BEGIN Local short connections"));
|
||||||
|
print_spice_subckt_local_short_connections(fp, module_manager, module_id);
|
||||||
|
print_spice_comment(fp, std::string("END Local short connections"));
|
||||||
|
|
||||||
|
print_spice_comment(fp, std::string("BEGIN Local output short connections"));
|
||||||
|
print_spice_subckt_output_short_connections(fp, module_manager, module_id);
|
||||||
|
|
||||||
|
print_spice_comment(fp, std::string("END Local output short connections"));
|
||||||
|
/* Print an empty line as splitter */
|
||||||
|
fp << std::endl;
|
||||||
|
|
||||||
|
/* Print instances */
|
||||||
|
for (ModuleId child_module : module_manager.child_modules(module_id)) {
|
||||||
|
for (size_t instance : module_manager.child_module_instances(module_id, child_module)) {
|
||||||
|
/* Print an instance */
|
||||||
|
write_spice_instance_to_file(fp, module_manager, module_id, child_module, instance);
|
||||||
|
/* Print an empty line as splitter */
|
||||||
|
fp << std::endl;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Print an end for the module */
|
||||||
|
print_spice_subckt_end(fp, module_manager.module_name(module_id));
|
||||||
|
|
||||||
|
/* Print an empty line as splitter */
|
||||||
|
fp << std::endl;
|
||||||
|
}
|
||||||
|
|
||||||
|
} /* end namespace openfpga */
|
||||||
|
|
@ -0,0 +1,23 @@
|
||||||
|
#ifndef SPICE_SUBCKT_WRITER_H
|
||||||
|
#define SPICE_SUBCKT_WRITER_H
|
||||||
|
|
||||||
|
/********************************************************************
|
||||||
|
* Include header files that are required by function declaration
|
||||||
|
*******************************************************************/
|
||||||
|
#include <fstream>
|
||||||
|
#include "module_manager.h"
|
||||||
|
|
||||||
|
/********************************************************************
|
||||||
|
* Function declaration
|
||||||
|
*******************************************************************/
|
||||||
|
|
||||||
|
/* begin namespace openfpga */
|
||||||
|
namespace openfpga {
|
||||||
|
|
||||||
|
void write_spice_subckt_to_file(std::fstream& fp,
|
||||||
|
const ModuleManager& module_manager,
|
||||||
|
const ModuleId& module_id);
|
||||||
|
|
||||||
|
} /* end namespace openfpga */
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Reference in New Issue