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Error correction in memory generation for pb_types without modes

This commit is contained in:
AurelienUoU 2019-06-13 15:34:25 -06:00
parent bf13c1f731
commit 15b4cc9ecb
1 changed files with 2 additions and 0 deletions
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2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
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@ -418,8 +418,10 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
temp_iopad_lsb = 0; temp_iopad_lsb = 0;
/* Local wires for memory configurations */ /* Local wires for memory configurations */
if (0 < temp_conf_bits_msb) {
dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info, dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info,
0, temp_conf_bits_msb - 1); 0, temp_conf_bits_msb - 1);
}
/* Quote all the sub blocks*/ /* Quote all the sub blocks*/