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Reorganize the code directory

This commit is contained in:
Xifan Tang 2018-07-26 11:28:21 -06:00
parent 3abce69f7c
commit 158dec405e
414 changed files with 314380 additions and 1 deletions
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fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_FF.xml Executable file
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fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_MC.xml Executable file
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fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_SS.xml Executable file
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fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml Executable file
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fpga_flow/benchmarks/FPGA_SPICE_bench/C1355.blif Normal file
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fpga_flow/benchmarks/FPGA_SPICE_bench/alu2.blif Normal file
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fpga_flow/benchmarks/FPGA_SPICE_bench/alu4.blif Normal file
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.model apex7
.inputs CAPSD CAT0 CAT1 CAT2 CAT3 CAT4 CAT5 VACC MMERR IBT0 IBT1 IBT2 \
ICLR LSD ACCRPY VERR_N RATR MARSSR VLENESR VSUMESR PLUTO0 PLUTO1 PLUTO2 \
PLUTO3 PLUTO4 PLUTO5 ORWD_N OWL_N PY END FBI WATCH OVACC KBG_N DEL1 \
COMPPAR VST0 VST1 STAR0 STAR1 STAR2 STAR3 BULL0 BULL1 BULL2 BULL3 \
BULL4 BULL5 BULL6
.outputs SDO LSD_P ACCRPY_P VERR_F RATR_P MARSSR_P VLENESR_P VSUMESR_P \
PLUTO0_P PLUTO1_P PLUTO2_P PLUTO3_P PLUTO4_P PLUTO5_P ORWD_F OWL_F PY_P \
END_P FBI_P WATCH_P OVACC_P KBG_F DEL1_P COMPPAR_P VST0_P VST1_P \
STAR0_P STAR1_P STAR2_P STAR3_P BULL0_P BULL1_P BULL2_P BULL3_P \
BULL4_P BULL5_P BULL6_P
.names FBI STAR3 C2G5 _260_m_ LSD OWL_N LSD_P
0---11 1
-0--11 1
--1-11 1
1000-- 1
.names ACCRPY OWL_N _199_m__inv _219_m_ ACCRPY_P
11-- 1
--00 1
.names VERR_N WATCH _199_m__inv _42_m_ TIMOT OWL_N _219_m_ VERR_F
-----01 1
100---- 1
1-0-0-- 1
1--10-- 1
.names RATR OWL_N _886_m_ COMPPAR _58_m__inv RATR_P
--1-- 1
11--- 1
---00 1
.names MARSSR OWL_N C29G7 TIMOT MARSSR_P
11-- 1
--01 1
.names VLENESR OWL_N KBG_N VLENESR_P
11- 1
-10 1
.names VSUMESR OWL_N VST1 _58_m__inv VSUMESR_P
11-- 1
--10 1
.names IBT0 PLUTO0 OWL_N _1015_m_ _894_m_ PLUTO0_P
-11-- 1
0--11 1
.names IBT0 PLUTO1 OWL_N _1015_m_ _894_m_ PLUTO1_P
-11-- 1
1--11 1
.names IBT1 PLUTO2 OWL_N IBT0 IBT2 _1015_m_ PLUTO2_P
-11--- 1
0--011 1
.names IBT1 PLUTO3 OWL_N IBT0 IBT2 _1015_m_ PLUTO3_P
-11--- 1
0--111 1
.names IBT1 PLUTO4 OWL_N IBT0 IBT2 _1015_m_ PLUTO4_P
-11--- 1
1--011 1
.names IBT1 PLUTO5 OWL_N IBT0 IBT2 _1015_m_ PLUTO5_P
-11--- 1
1--111 1
.names WATCH C1G3 ORWD_F
0- 1
-0 1
.names WATCH TIMOT ICLR END KBG_N OWL_F
0-001 1
-0001 1
.names PY DEL1 _89_m_ _90_m_ PY_P
1-1- 1
-1-1 1
.names _58_m__inv _199_m__inv _219_m_ END_P
0-- 1
-00 1
.names ORWD_N FBI _99_m_ _80_m_ _254_m__inv _260_m_ C2G5 _219_m_ STAR2 \
_2087_m_ FBI_P
-1---0---- 1
0---00---- 1
---000---- 1
0-----10-- 1
-1----10-- 1
---0--10-- 1
-1----1-11 1
--1---1-11 1
.names VACC OWL_N OVACC C29G7 WATCH_P
---0 1
011- 1
.names VACC ICLR OVACC_P
10 1
.names KBG_N _199_m__inv _42_m_ OWL_N _219_m_ KBG_F
10--- 1
1-1-- 1
---01 1
.names CAPSD ICLR DEL1_P
10 1
.names FBI DEL1 COMPPAR _219_m_ OWL_N COMPPAR_P
-100- 1
0-1-1 1
-01-1 1
.names VST0 VST1 _89_m_ _90_m_ VST0_P
1-1- 1
-1-1 1
.names PY VST1 _89_m_ _90_m_ VST1_P
-11- 1
1--1 1
.names STAR0 _254_m__inv _44_m__inv STAR0_P
00- 1
1-0 1
.names STAR0 STAR1 _99_m_ _44_m__inv _2087_m_ _80_m_ _219_m_ STAR1_P
-1-0--- 1
101---- 1
01--1-- 1
1----00 1
.names STAR2 _99_m_ _44_m__inv C2G5 _80_m_ _219_m_ _2087_m_ STAR2_P
1-0---- 1
-1-0--- 1
1-----1 1
0---10- 1
.names OWL_N STAR2 STAR3 _254_m__inv _44_m__inv _2087_m_ _80_m_ \
STAR3_P
--1-0-- 1
--1--1- 1
101---- 1
-100--1 1
.names BULL0 C29G7 OWL_N WATCH BULL0_P
00-- 1
1-10 1
.names BULL1 _1214_m_ BULL0 C29G7 BULL1_P
11-- 1
0-10 1
.names BULL1 BULL2 _1214_m_ BULL0 C29G7 BULL2_P
-11-- 1
10-10 1
.names OWL_N BULL3 _226_m_ BULL3_P
111 1
100 1
.names BULL4 OWL_N BULL3 _226_m_ _873_m_ BULL4_P
0---1 1
110-- 1
11-1- 1
.names BULL5 BULL4_P BULL4 _873_m_ OWL_N BULL3 _226_m_ BULL5_P
11----- 1
0-11--- 1
1---10- 1
1---1-1 1
.names BULL2 BULL3 BULL4 BULL5 BULL6 _1214_m_ _873_m_ _226_m_ OWL_N \
BULL6_P
----11--- 1
0---1---1 1
-0--1---1 1
--0-1---1 1
---01---1 1
--110-1-- 1
-111-1-0- 1
.names STAR2 _80_m_ C2G5
1- 1
-0 1
.names C1G3 C29G7 _260_m_
0- 1
-1 1
.names ORWD_F _219_m_ C2G5 _199_m__inv
00- 1
-01 1
.names OWL_N FBI _219_m_
0- 1
-0 1
.names STAR3 ORWD_F C2G5 CAT1 WATCH CAT0 _894_m_ _42_m_
00----- 1
-01---- 1
0--0101 1
--10101 1
.names BULL0 BULL3 BULL4 BULL5 BULL6 BULL1 BULL2 TIMOT
0010110 1
.names MMERR VST0 _58_m__inv _886_m_
000 1
.names OWL_N END _58_m__inv
0- 1
-0 1
.names OWL_N WATCH C29G7
0- 1
-0 1
.names _886_m_ C29G7 TIMOT COMPPAR _58_m__inv VST1 OWL_N KBG_N _1015_m_
1------- 1
-01----- 1
---00--- 1
----01-- 1
------10 1
.names IBT1 IBT2 _894_m_
10 1
.names CAT1 CAT2 CAT3 CAT4 CAT5 IBT0 _894_m_ CAT0 IBT1 IBT2 C1G3
0----11--- 1
-----010-- 1
----01--11 1
---0-0--11 1
--0--1--01 1
-0---0--01 1
.names ICLR FBI _89_m_
00 1
.names ICLR FBI _90_m_
01 1
.names ORWD_N _260_m_ _99_m_
00 1
.names STAR0 STAR1 _80_m_
11 1
.names _99_m_ _219_m_ _254_m__inv
01 1
.names OWL_N _80_m_ _2087_m_
10 1
.names ORWD_N OWL_N FBI ORWD_F _44_m__inv
-0-- 1
--1- 1
0--0 1
.names OWL_N BULL0 BULL1 WATCH _1214_m_
10-- 1
1-0- 1
1--0 1
.names WATCH BULL0 BULL1 BULL2 _226_m_
0--- 1
-0-- 1
--0- 1
---0 1
.names OWL_N BULL3 _226_m_ _873_m_
110 1
.names VST0 SDO
1 1
.end

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.model top
.inputs opcode[0] opcode[1] opcode[2] opcode[3] opcode[4] op_ext[0] \
op_ext[1]
.outputs sel_reg_dst[0] sel_reg_dst[1] sel_alu_opB[0] sel_alu_opB[1] \
alu_op[0] alu_op[1] alu_op[2] alu_op_ext[0] alu_op_ext[1] alu_op_ext[2] \
alu_op_ext[3] halt reg_write sel_pc_opA sel_pc_opB beqz bnez bgez bltz \
jump Cin invA invB sign mem_write sel_wb
.names opcode[0] opcode[1] n35
10 1
.names opcode[3] opcode[4] n36
11 1
.names n35 n36 n37
11 1
.names opcode[1] opcode[3] n38
11 1
.names opcode[4] n38 n39
11 1
.names n37 n39 n40
00 1
.names opcode[2] n40 n41
00 1
.names opcode[1] opcode[3] n42
01 1
.names opcode[4] n42 n43
11 1
.names opcode[3] opcode[4] n44
00 1
.names n36 n44 n45
00 1
.names opcode[1] n45 n46
10 1
.names n43 n46 n47
00 1
.names opcode[2] n47 n48
10 1
.names n41 n48 sel_reg_dst[0]
00 0
.names opcode[0] n36 n50
00 1
.names opcode[0] n50 n51
00 1
.names opcode[1] n51 n52
00 1
.names opcode[3] n44 n53
00 1
.names opcode[1] n53 n54
10 1
.names n52 n54 n55
00 1
.names opcode[2] n55 n56
00 1
.names opcode[3] opcode[4] n57
01 1
.names opcode[3] n57 n58
00 1
.names opcode[1] n58 n59
10 1
.names opcode[1] n59 n60
10 1
.names opcode[2] n60 n61
10 1
.names n56 n61 sel_reg_dst[1]
00 1
.names opcode[0] n45 n63
00 1
.names opcode[3] n36 n64
10 1
.names opcode[0] n64 n65
10 1
.names n63 n65 n66
00 1
.names opcode[1] n66 n67
10 1
.names n52 n67 n68
00 1
.names opcode[2] n68 n69
00 1
.names opcode[2] n69 sel_alu_opB[0]
00 1
.names opcode[0] opcode[3] n71
00 1
.names n57 n71 n72
01 1
.names opcode[0] n45 n73
10 1
.names n72 n73 n74
00 1
.names opcode[1] n74 n75
00 1
.names n54 n75 n76
00 1
.names opcode[2] n76 n77
00 1
.names opcode[2] n53 n78
10 1
.names n77 n78 sel_alu_opB[1]
00 1
.names opcode[0] opcode[3] n80
01 1
.names opcode[4] op_ext[0] n81
11 1
.names n80 n81 n82
11 1
.names opcode[3] op_ext[1] n83
10 1
.names n36 n83 n84
01 1
.names opcode[3] op_ext[0] n85
10 1
.names n36 n85 n86
01 1
.names opcode[3] op_ext[0] n87
11 1
.names n86 n87 n88
00 1
.names op_ext[1] n88 n89
10 1
.names n84 n89 n90
00 1
.names opcode[0] n90 n91
10 1
.names n82 n91 n92
00 1
.names opcode[1] n92 n93
10 1
.names opcode[2] n93 n94
00 1
.names opcode[0] n53 n95
10 1
.names opcode[0] n95 n96
10 1
.names opcode[2] n96 n97
10 1
.names n94 n97 alu_op[0]
00 1
.names opcode[3] op_ext[1] n99
11 1
.names n84 n99 n100
00 1
.names opcode[1] n100 n101
10 1
.names opcode[2] n101 n102
00 1
.names opcode[1] n54 n103
10 1
.names opcode[2] n103 n104
10 1
.names n102 n104 alu_op[1]
00 1
.names opcode[1] n36 n106
00 1
.names n44 n106 n107
01 1
.names n44 n50 n108
01 1
.names opcode[0] n58 n109
10 1
.names n108 n109 n110
00 1
.names opcode[1] n110 n111
10 1
.names n107 n111 n112
00 1
.names opcode[2] n112 n113
00 1
.names opcode[2] opcode[3] n114
11 1
.names opcode[4] n114 n115
11 1
.names n113 n115 alu_op[2]
00 0
.names opcode[1] opcode[2] n117
00 1
.names n52 n117 n118
01 1
.names opcode[1] n74 n119
10 1
.names n37 n119 n120
00 1
.names opcode[2] n120 n121
10 1
.names n118 n121 alu_op_ext[0]
00 0
.names opcode[0] n53 n123
00 1
.names opcode[0] n123 n124
00 1
.names opcode[1] n124 n125
10 1
.names opcode[1] opcode[2] n126
10 1
.names n125 n126 n127
01 1
.names opcode[1] opcode[2] n128
11 1
.names n45 n128 n129
01 1
.names n127 n129 alu_op_ext[1]
00 0
.names n106 n125 n131
00 1
.names opcode[2] n131 n132
00 1
.names n61 n132 alu_op_ext[2]
00 1
.names n80 n109 n134
00 1
.names opcode[1] n134 n135
10 1
.names opcode[2] n107 n136
00 1
.names n135 n136 n137
01 1
.names n78 n137 alu_op_ext[3]
00 1
.names opcode[0] n58 n139
00 1
.names opcode[0] n139 n140
00 1
.names opcode[1] n140 n141
00 1
.names opcode[1] n141 n142
00 1
.names opcode[2] n142 n143
00 1
.names opcode[2] n143 halt
00 1
.names opcode[1] n134 n145
00 1
.names n59 n145 n146
00 1
.names opcode[2] n146 n147
00 1
.names opcode[1] opcode[4] n148
01 1
.names opcode[1] n64 n149
10 1
.names n148 n149 n150
00 1
.names opcode[2] n150 n151
10 1
.names n147 n151 reg_write
00 0
.names opcode[0] n109 n153
10 1
.names opcode[2] n153 n154
10 1
.names opcode[2] n154 sel_pc_opA
10 1
.names opcode[2] n140 n156
10 1
.names opcode[2] n156 sel_pc_opB
10 1
.names opcode[0] n64 n158
00 1
.names opcode[0] n158 n159
00 1
.names opcode[1] n159 n160
00 1
.names opcode[1] n160 n161
00 1
.names opcode[2] n161 n162
10 1
.names opcode[2] n162 beqz
10 1
.names opcode[0] n65 n164
10 1
.names opcode[1] n164 n165
00 1
.names opcode[1] n165 n166
00 1
.names opcode[2] n166 n167
10 1
.names opcode[2] n167 bnez
10 1
.names opcode[1] n164 n169
10 1
.names opcode[1] n169 n170
10 1
.names opcode[2] n170 n171
10 1
.names opcode[2] n171 bgez
10 1
.names opcode[1] n159 n173
10 1
.names opcode[1] n173 n174
10 1
.names opcode[2] n174 n175
10 1
.names opcode[2] n175 bltz
10 1
.names opcode[2] n58 n177
10 1
.names opcode[2] n177 jump
10 1
.names opcode[0] opcode[1] n179
11 1
.names n88 n179 n180
01 1
.names n35 n65 n181
10 1
.names opcode[2] n181 n182
00 1
.names n180 n182 n183
01 1
.names opcode[1] n51 n184
10 1
.names n106 n184 n185
00 1
.names opcode[2] n185 n186
10 1
.names n183 n186 Cin
00 1
.names op_ext[0] n36 n188
11 1
.names op_ext[1] n188 n189
00 1
.names op_ext[1] n189 n190
00 1
.names opcode[0] n190 n191
10 1
.names opcode[0] n191 n192
10 1
.names opcode[1] n192 n193
10 1
.names n165 n193 n194
00 1
.names opcode[2] n194 n195
00 1
.names opcode[2] n195 invA
00 1
.names n90 n179 n197
01 1
.names opcode[2] n197 n198
00 1
.names n186 n198 invB
00 1
.names opcode[1] n124 n200
00 1
.names opcode[1] n96 n201
10 1
.names n200 n201 n202
00 1
.names opcode[2] n202 n203
00 1
.names opcode[2] n203 mem_write
00 1
.names opcode[1] n96 n205
00 1
.names opcode[1] n205 n206
00 1
.names opcode[2] n206 n207
00 1
.names opcode[2] n207 sel_wb
00 1
.names sign
1
.end

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.model TOP
.inputs i_0_ i_1_ i_2_ i_3_ i_4_ i_5_ i_6_ i_7_ i_8_ i_9_ i_10_ i_11_ i_12_ \
i_13_ i_14_ i_15_ i_16_ i_17_ i_18_ i_19_ i_20_ i_21_ i_22_ i_23_ i_24_ i_25_ \
i_26_ i_27_ i_28_ i_29_ i_30_ i_31_ i_32_ i_33_ i_34_ i_35_ i_36_ i_37_ i_38_ \
i_39_ i_40_ i_41_ i_42_ i_43_ i_44_ i_45_ i_46_ i_47_ i_48_ i_49_ i_50_ i_51_ \
i_52_ i_53_ i_54_ i_55_ i_56_ i_57_ i_58_ i_59_ i_60_ i_61_ i_62_ i_63_ i_64_
.outputs o_0_ o_1_ o_2_ o_3_ o_4_ o_5_ o_6_ o_7_ o_8_ o_9_ o_10_ o_11_ o_12_ \
o_13_ o_14_ o_15_ o_16_ o_17_ o_18_ o_19_ o_20_ o_21_ o_22_ o_23_ o_24_ o_25_ \
o_26_ o_27_ o_28_ o_29_ o_30_ o_31_ o_32_ o_33_ o_34_ o_35_ o_36_ o_37_ o_38_ \
o_39_ o_40_ o_41_ o_42_ o_43_ o_44_ o_45_ o_46_ o_47_ o_48_ o_49_ o_50_ o_51_ \
o_52_ o_53_ o_54_ o_55_ o_56_ o_57_ o_58_ o_59_ o_60_ o_61_ o_62_ o_63_ o_64_
.names n178 o_0_
0 1
.names i_5_ n71 n83 n181 o_1_
1000 1
.names n172 o_2_
0 1
.names n168 o_3_
0 1
.names i_15_ i_29_ o_4_
11 1
.names i_14_ i_15_ n112 o_6_
101 1
.names i_15_ i_43_ n129 o_7_
011 1
.names n162 o_8_
0 1
.names n158 o_9_
0 1
.names i_15_ i_28_ i_29_ i_37_ o_10_
0110 1
.names i_15_ i_29_ i_37_ o_11_
011 1
.names i_6_ i_15_ i_24_ n14 n144 n195 o_12_
100100 1
.names i_41_ n151 n18 n132 o_13_
1111 1
.names i_50_ n154 o_14_
11 1
.names i_10_ i_58_ n112 n198 o_15_
1010 1
.names i_3_ i_26_ n10 n151 o_16_
0111 1
.names i_3_ n6 n8 n71 n151 o_17_
11101 1
.names n148 o_18_
0 1
.names i_64_ n223 n229 o_19_
100 1
.names i_51_ n143 n144 n226 o_20_
1000 1
.names n141 o_21_
0 1
.names n136 o_22_
0 1
.names n133 o_23_
0 1
.names i_10_ i_11_ i_14_ n7 n129 n132 n183 o_24_
0101110 1
.names i_24_ i_25_ n4 n121 o_25_
1011 1
.names n124 o_26_
0 1
.names i_13_ i_16_ i_20_ i_52_ n232 o_27_
10000 1
.names n121 n4 i_25_ o_28_
111 1
.names i_46_ i_60_ n12 n183 o_29_
0110 1
.names i_52_ n232 o_30_
10 1
.names n115 o_31_
0 1
.names i_46_ n12 n183 o_32_
110 1
.names i_39_ i_40_ n12 o_33_
101 1
.names i_58_ n112 n198 o_34_
110 1
.names i_0_ i_4_ i_41_ n110 n187 n231 o_35_
010100 1
.names i_60_ i_61_ i_62_ n26 n108 o_36_
01011 1
.names n102 o_37_
0 1
.names n97 o_38_
0 1
.names i_40_ i_41_ i_42_ i_50_ n101 n187 n214 o_39_
0010000 1
.names i_54_ n45 n46 n66 n91 o_40_
10001 1
.names n88 o_41_
0 1
.names n85 o_42_
0 1
.names n81 o_43_
0 1
.names n74 o_44_
0 1
.names n68 o_45_
0 1
.names n60 o_46_
0 1
.names i_17_ i_35_ n46 n76 o_47_
1000 1
.names n49 o_48_
0 1
.names n44 o_49_
0 1
.names i_57_ n66 n229 o_50_
100 1
.names i_48_ i_49_ i_50_ n55 n228 o_51_
10000 1
.names n30 o_52_
0 1
.names i_63_ i_64_ n223 n229 o_53_
1000 1
.names i_55_ i_62_ n26 n214 o_54_
1010 1
.names i_35_ i_62_ n214 n227 o_55_
1000 1
.names n19 o_56_
0 1
.names i_18_ n13 n18 n221 o_57_
1110 1
.names i_22_ n6 n13 n14 n16 n193 o_58_
111110 1
.names i_40_ n12 o_59_
11 1
.names i_7_ n149 o_60_
10 1
.names i_8_ n10 o_61_
11 1
.names i_47_ n6 n8 n180 o_62_
1110 1
.names i_56_ n6 n5 n7 o_63_
1111 1
.names n4 n5 i_30_ o_64_
111 1
.names n7 n185 n205 n4
110 1
.names n132 n208 n5
10 1
.names n185 n186 n6
10 1
.names i_50_ i_58_ i_60_ n180 n7
0000 1
.names i_60_ n5 n99 n8
010 1
.names i_40_ n8 n71 n205 n212 n10
01000 1
.names i_50_ n154 n12
01 1
.names i_15_ i_41_ i_62_ n197 n13
0000 1
.names i_3_ n208 n14
00 1
.names i_60_ n71 n99 n16
000 1
.names n110 n212 n219 n18
100 1
.names i_36_ n170 n224 n20
1-- 1
-1- 1
--1 1
.names n222 n135 n77 n22
1-- 1
-1- 1
--1 1
.names i_16_ i_20_ i_21_ n20 n22 n19
1---- 1
-0--- 1
--1-- 1
---1- 1
----1 1
.names i_35_ n227 n26
00 1
.names i_45_ n180 n31
1- 1
-1 1
.names i_47_ i_48_ i_49_ n32
1-- 1
-1- 1
--1 1
.names i_33_ n72 n70 i_31_ i_17_ i_34_ n33
1----- 1
-1---- 1
--1--- 1
---1-- 1
----1- 1
-----1 1
.names i_15_ n222 n35
1- 1
-1 1
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.end

1479
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fpga_flow/benchmarks/FPGA_SPICE_bench/fsm8_8_13.blif Normal file
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.model random_fsm
.inputs i0 i1 i2 i3 i4 i5 i6 i7 clk rst
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.latch net_318 S5_q re clk 2
.latch net_319 S4_q re clk 2
.latch net_320 S6_q re clk 2
.latch net_321 S3_q re clk 2
.latch net_322 S2_q re clk 2
.latch net_324 S7_q re clk 2
.latch net_325 S1_q re clk 2
.latch net_326 S0_q re clk 2
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0 1
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0 1
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0 1
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0 1
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.model top
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fpga_flow/benchmarks/FPGA_SPICE_bench/pci_conf_cyc_addr_dec.blif Normal file
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@ -0,0 +1,259 @@
# Benchmark "pci_conf_cyc_addr_dec" written by ABC on Mon Aug 29 15:33:11 2005
.model pci_conf_cyc_addr_dec
.inputs ccyc_addr_in[0] ccyc_addr_in[1] ccyc_addr_in[2] ccyc_addr_in[3] \
ccyc_addr_in[4] ccyc_addr_in[5] ccyc_addr_in[6] ccyc_addr_in[7] \
ccyc_addr_in[8] ccyc_addr_in[9] ccyc_addr_in[10] ccyc_addr_in[11] \
ccyc_addr_in[12] ccyc_addr_in[13] ccyc_addr_in[14] ccyc_addr_in[15] \
ccyc_addr_in[16] ccyc_addr_in[17] ccyc_addr_in[18] ccyc_addr_in[19] \
ccyc_addr_in[20] ccyc_addr_in[21] ccyc_addr_in[22] ccyc_addr_in[23] \
ccyc_addr_in[24] ccyc_addr_in[25] ccyc_addr_in[26] ccyc_addr_in[27] \
ccyc_addr_in[28] ccyc_addr_in[29] ccyc_addr_in[30] ccyc_addr_in[31]
.outputs ccyc_addr_out[0] ccyc_addr_out[1] ccyc_addr_out[2] \
ccyc_addr_out[3] ccyc_addr_out[4] ccyc_addr_out[5] ccyc_addr_out[6] \
ccyc_addr_out[7] ccyc_addr_out[8] ccyc_addr_out[9] ccyc_addr_out[10] \
ccyc_addr_out[11] ccyc_addr_out[12] ccyc_addr_out[13] ccyc_addr_out[14] \
ccyc_addr_out[15] ccyc_addr_out[16] ccyc_addr_out[17] ccyc_addr_out[18] \
ccyc_addr_out[19] ccyc_addr_out[20] ccyc_addr_out[21] ccyc_addr_out[22] \
ccyc_addr_out[23] ccyc_addr_out[24] ccyc_addr_out[25] ccyc_addr_out[26] \
ccyc_addr_out[27] ccyc_addr_out[28] ccyc_addr_out[29] ccyc_addr_out[30] \
ccyc_addr_out[31]
.names [64]
0
.names [65]
1
.names ccyc_addr_in[1] ccyc_addr_out[1]
1 1
.names ccyc_addr_in[2] ccyc_addr_out[2]
1 1
.names ccyc_addr_in[3] ccyc_addr_out[3]
1 1
.names ccyc_addr_in[4] ccyc_addr_out[4]
1 1
.names ccyc_addr_in[5] ccyc_addr_out[5]
1 1
.names ccyc_addr_in[6] ccyc_addr_out[6]
1 1
.names ccyc_addr_in[7] ccyc_addr_out[7]
1 1
.names ccyc_addr_in[8] ccyc_addr_out[8]
1 1
.names ccyc_addr_in[9] ccyc_addr_out[9]
1 1
.names ccyc_addr_in[10] ccyc_addr_out[10]
1 1
.names [126] [98] [115] ccyc_addr_out[30]
00- 1
--0 1
.names [147] [98] [151] ccyc_addr_out[29]
00- 1
--0 1
.names [131] [97] [123] ccyc_addr_out[28]
00- 1
--0 1
.names [120] [97] [116] ccyc_addr_out[27]
00- 1
--0 1
.names [105] ccyc_addr_out[0] [143] ccyc_addr_out[31]
00- 1
--0 1
.names [134] [99] [118] ccyc_addr_out[26]
00- 1
--0 1
.names [142] [99] [138] ccyc_addr_out[25]
00- 1
--0 1
.names [145] [104] [144] ccyc_addr_out[24]
00- 1
--0 1
.names [122] [104] [148] ccyc_addr_out[23]
00- 1
--0 1
.names [121] [106] [152] ccyc_addr_out[22]
00- 1
--0 1
.names [119] [106] [117] ccyc_addr_out[21]
00- 1
--0 1
.names [128] [107] [133] ccyc_addr_out[20]
00- 1
--0 1
.names [130] [107] [125] ccyc_addr_out[19]
00- 1
--0 1
.names [137] [102] [132] ccyc_addr_out[18]
00- 1
--0 1
.names [139] [102] [135] ccyc_addr_out[17]
00- 1
--0 1
.names [140] [100] [141] ccyc_addr_out[16]
00- 1
--0 1
.names [129] [100] [158] ccyc_addr_out[15]
00- 1
--0 1
.names [146] [101] [153] ccyc_addr_out[14]
00- 1
--0 1
.names [149] [101] [154] ccyc_addr_out[13]
00- 1
--0 1
.names [150] [103] [157] ccyc_addr_out[12]
00- 1
--0 1
.names [124] [103] [136] ccyc_addr_out[11]
00- 1
--0 1
.names [108] [168] [97]
11 0
.names [109] ccyc_addr_in[12] [98]
11 0
.names [111] ccyc_addr_in[12] [99]
11 0
.names [112] [168] [100]
11 0
.names [113] ccyc_addr_in[12] [101]
11 0
.names [112] ccyc_addr_in[12] [102]
11 0
.names [113] [168] [103]
11 0
.names [111] [168] [104]
11 0
.names [155] [127] ccyc_addr_in[13] [105]
111 0
.names [114] ccyc_addr_in[12] [106]
11 0
.names [114] [168] [107]
11 0
.names [110] [108]
0 1
.names [110] [109]
0 1
.names [171] [165] [167] [110]
111 0
.names [156] [167] [111]
00 1
.names [159] [167] [112]
00 1
.names [159] ccyc_addr_in[13] [113]
00 1
.names [156] ccyc_addr_in[13] [114]
00 1
.names ccyc_addr_in[30] ccyc_addr_out[0] [115]
11 0
.names ccyc_addr_in[27] ccyc_addr_out[0] [116]
11 0
.names ccyc_addr_in[21] ccyc_addr_out[0] [117]
11 0
.names ccyc_addr_in[26] ccyc_addr_out[0] [118]
11 0
.names [163] ccyc_addr_out[0] [119]
00 0
.names [163] ccyc_addr_out[0] [120]
00 0
.names ccyc_addr_in[11] [162] [121]
11 0
.names [163] ccyc_addr_out[0] [122]
00 0
.names ccyc_addr_in[28] ccyc_addr_out[0] [123]
11 0
.names [163] ccyc_addr_out[0] [124]
00 0
.names ccyc_addr_in[19] ccyc_addr_out[0] [125]
11 0
.names [160] [162] [126]
11 0
.names [165] [171] [127]
11 1
.names [160] [162] [128]
11 0
.names [163] ccyc_addr_out[0] [129]
00 0
.names [163] ccyc_addr_out[0] [130]
00 0
.names [160] [162] [131]
11 0
.names ccyc_addr_in[18] ccyc_addr_out[0] [132]
11 0
.names ccyc_addr_in[20] ccyc_addr_out[0] [133]
11 0
.names [160] [162] [134]
11 0
.names ccyc_addr_in[17] ccyc_addr_out[0] [135]
11 0
.names [160] ccyc_addr_out[0] [136]
11 0
.names [160] [162] [137]
11 0
.names ccyc_addr_in[25] ccyc_addr_out[0] [138]
11 0
.names [163] ccyc_addr_out[0] [139]
00 0
.names ccyc_addr_in[11] [162] [140]
11 0
.names ccyc_addr_in[16] ccyc_addr_out[0] [141]
11 0
.names [163] ccyc_addr_out[0] [142]
00 0
.names ccyc_addr_in[31] ccyc_addr_out[0] [143]
11 0
.names ccyc_addr_in[24] ccyc_addr_out[0] [144]
11 0
.names [160] [162] [145]
11 0
.names [160] [162] [146]
11 0
.names [163] ccyc_addr_out[0] [147]
00 0
.names ccyc_addr_in[23] ccyc_addr_out[0] [148]
11 0
.names [163] ccyc_addr_in[0] [149]
00 0
.names ccyc_addr_in[11] [162] [150]
11 0
.names ccyc_addr_in[29] ccyc_addr_out[0] [151]
11 0
.names ccyc_addr_in[22] ccyc_addr_out[0] [152]
11 0
.names [165] [166] [153]
00 0
.names [167] [166] [154]
00 0
.names [163] ccyc_addr_in[12] [155]
00 1
.names [172] ccyc_addr_in[14] [156]
11 0
.names [168] [166] [157]
00 0
.names [170] [166] [158]
00 0
.names [172] [169] [159]
11 0
.names [164] [160]
0 1
.names [166] ccyc_addr_out[0]
0 1
.names ccyc_addr_in[0] [162]
0 1
.names ccyc_addr_in[11] [163]
1 1
.names ccyc_addr_in[11] [164]
0 1
.names ccyc_addr_in[14] [165]
0 1
.names ccyc_addr_in[0] [166]
0 1
.names ccyc_addr_in[13] [167]
0 1
.names ccyc_addr_in[12] [168]
0 1
.names ccyc_addr_in[14] [169]
0 1
.names [171] [170]
0 1
.names [172] [171]
0 1
.names ccyc_addr_in[15] [172]
0 1
.end

324
fpga_flow/benchmarks/FPGA_SPICE_bench/planet.blif Normal file
View File

@ -0,0 +1,324 @@
.model planet.kiss2
.inputs v0 v1 v2 v3 v4 v5 v6
.outputs v13.6 v13.7 v13.8 v13.9 v13.10 v13.11 v13.12 v13.13 v13.14 v13.15 \
v13.16 v13.17 v13.18 v13.19 v13.20 v13.21 v13.22 v13.23 v13.24
.latch v13.0 v7 0
.latch v13.1 v8 0
.latch v13.2 v9 0
.latch v13.3 v10 0
.latch v13.4 v11 1
.latch v13.5 v12 0
.names [104] v13.6
0 1
.names [106] v13.7
0 1
.names [108] v13.8
0 1
.names [110] v13.9
0 1
.names [112] v13.10
0 1
.names [114] v13.11
0 1
.names [116] v13.12
0 1
.names [118] v13.13
0 1
.names [120] v13.14
0 1
.names [122] v13.15
0 1
.names [124] v13.16
0 1
.names [126] v13.17
0 1
.names [128] v13.18
0 1
.names [130] v13.19
0 1
.names [132] v13.20
0 1
.names [134] v13.21
0 1
.names [136] v13.22
0 1
.names [138] v13.23
0 1
.names [140] v13.24
0 1
.names [92] v13.0
0 1
.names [94] v13.1
0 1
.names [96] v13.2
0 1
.names [98] v13.3
0 1
.names [100] v13.4
0 1
.names [102] v13.5
0 1
.names v4 v5 v7 v8 v9 v10 v11 v12 [0]
10000000 1
.names v4 v5 v7 v8 v9 v10 v11 [1]
1111000 1
.names v0 v1 v3 v7 v9 v10 v11 v12 [2]
01100011 1
.names v0 v3 v6 v7 v9 v10 v11 v12 [3]
01000011 1
.names v2 v4 v5 v7 v8 v9 v11 v12 [4]
01011000 1
.names v2 v4 v5 v8 v9 v10 v11 v12 [5]
01010001 1
.names v0 v2 v8 v9 v10 v11 [6]
001100 1
.names v4 v5 v7 v8 v9 v10 v11 v12 [7]
00000000 1
.names v2 v4 v5 v7 v8 v9 v10 v11 [8]
00011000 1
.names v0 v4 v5 v8 v9 v10 v11 v12 [9]
01010010 1
.names v0 v4 v5 v8 v9 v10 v11 v12 [10]
00010010 1
.names v2 v4 v7 v8 v9 v11 v12 [11]
0011000 1
.names v2 v5 v7 v8 v9 v10 v11 [12]
0111000 1
.names v0 v2 v8 v9 v12 [13]
01100 1
.names v1 v7 v9 v10 v11 [14]
11111 1
.names v2 v3 v8 v10 v11 [15]
10011 1
.names v2 v3 v8 v11 v12 [16]
10011 1
.names v0 v5 v8 v9 v10 v11 v12 [17]
0110010 1
.names v4 v5 v7 v8 v9 v10 v11 v12 [18]
11000000 1
.names v7 v8 v10 v11 v12 [19]
00110 1
.names v2 v7 v8 v9 v10 v11 [20]
010101 1
.names v2 v7 v8 v9 [21]
1111 1
.names v4 v8 v9 v10 v11 v12 [22]
010001 1
.names v2 v7 v8 v10 [23]
1111 1
.names v3 v6 v7 v8 v9 v10 v11 v12 [24]
10011111 1
.names v3 v6 v7 v8 v9 v10 v12 [25]
1110011 1
.names v1 v7 v8 v10 [26]
0110 1
.names v7 v9 v11 v12 [27]
1111 1
.names v7 v8 v9 v10 v11 v12 [28]
100000 1
.names v0 v1 v3 v7 v9 v10 v11 v12 [29]
11100011 1
.names v0 v3 v6 v7 v9 v10 v11 v12 [30]
11000011 1
.names v4 v8 v9 v11 v12 [31]
01010 1
.names v2 v3 v7 v8 v9 v10 v11 v12 [32]
10000101 1
.names v2 v3 v7 v8 v9 v10 v11 v12 [33]
00000101 1
.names v7 v8 v9 v10 v11 v12 [34]
001010 1
.names v7 v9 v10 v11 v12 [35]
10100 1
.names v1 v8 v9 v10 v11 [36]
00011 1
.names v0 v1 v6 v7 v9 v10 v12 [37]
1010001 1
.names v6 v8 v9 v10 v11 [38]
00011 1
.names v6 v7 v8 v9 v10 v11 v12 [39]
1011111 1
.names v7 v8 v9 v10 v11 [40]
11111 1
.names v7 v8 v10 v12 [41]
0101 1
.names v2 v8 v9 v10 v11 [42]
00101 1
.names v4 v5 v10 [43]
110 1
.names v7 v8 v9 v10 v11 v12 [44]
111010 1
.names v7 v9 v10 v11 v12 [45]
11100 1
.names v2 v8 v9 v10 v11 v12 [46]
010011 1
.names v2 v7 v8 v9 v10 [47]
00100 1
.names v1 v2 v7 v8 v9 v11 v12 [48]
0110010 1
.names v1 v2 v7 v8 v9 v11 v12 [49]
1110010 1
.names v1 v2 v7 v8 v9 v11 v12 [50]
1010010 1
.names v1 v2 v7 v8 v9 v11 v12 [51]
0010010 1
.names v7 v9 v10 v11 v12 [52]
11011 1
.names v3 v7 v8 v9 v11 v12 [53]
101101 1
.names v2 v7 v8 v10 v11 [54]
01011 1
.names v3 v7 v9 v10 v11 v12 [55]
100101 1
.names v7 v8 v9 v10 v11 v12 [56]
111101 1
.names v2 v8 v9 v10 v11 [57]
00011 1
.names v3 v6 v7 v8 v12 [58]
00011 1
.names v2 v7 v8 v9 v10 [59]
10100 1
.names v7 v9 v11 v12 [60]
0010 1
.names v0 v7 v10 v12 [61]
0001 1
.names v2 v8 v9 v10 v11 [62]
10011 1
.names v7 v8 v10 v11 v12 [63]
10001 1
.names v3 v7 v8 v11 v12 [64]
00101 1
.names v7 v8 v9 v10 v11 [65]
11010 1
.names v7 v8 v9 v12 [66]
1011 1
.names v2 v8 v9 v10 v11 v12 [67]
101010 1
.names v7 v8 v11 v12 [68]
1000 1
.names v0 v8 v9 v10 v11 v12 [69]
110010 1
.names v2 v7 v8 v9 v11 v12 [70]
111000 1
.names v6 v7 v8 v9 v10 [71]
01001 1
.names v3 v7 v8 v9 v10 [72]
01001 1
.names v7 v9 v10 v11 v12 [73]
10111 1
.names v3 v7 v9 v10 v12 [74]
00001 1
.names v8 v9 v10 v11 v12 [75]
11000 1
.names v7 v9 v10 v12 [76]
0010 1
.names v8 v9 v10 v11 v12 [77]
01100 1
.names v9 v10 v11 v12 [78]
1001 1
.names v7 v8 v10 v11 v12 [79]
01100 1
.names v2 v7 v8 v10 v11 [80]
11011 1
.names v7 v8 v11 v12 [81]
1011 1
.names v7 v8 v10 v11 [82]
0101 1
.names v7 v10 v11 v12 [83]
0110 1
.names v7 v8 v9 v11 v12 [84]
00101 1
.names v7 v8 v9 v10 v11 [85]
00111 1
.names v7 v9 v10 v11 [86]
0100 1
.names v2 v8 v9 v10 v12 [87]
11001 1
.names v8 v9 v10 v12 [88]
0101 1
.names v9 v10 v11 v12 [89]
0110 1
.names v7 v8 v9 v11 [90]
0101 1
.names v7 v10 v11 v12 [91]
0001 1
.names [2] [3] [16] [18] [20] [24] [28] [32] [33] [35] [36] [37] [38] [46] \
[47] [48] [49] [50] [51] [53] [54] [55] [58] [62] [64] [70] [71] [72] [73] \
[74] [75] [77] [82] [85] [86] [88] [90] [91] [92]
00000000000000000000000000000000000000 1
.names [4] [5] [11] [22] [32] [33] [34] [36] [37] [38] [39] [48] [50] [55] \
[58] [61] [62] [64] [67] [68] [71] [72] [74] [77] [79] [80] [82] [84] [85] \
[86] [87] [88] [89] [90] [91] [94]
00000000000000000000000000000000000 1
.names [1] [4] [9] [10] [11] [15] [17] [29] [30] [34] [35] [36] [37] [38] [39] \
[40] [45] [47] [49] [51] [52] [53] [67] [69] [70] [74] [76] [77] [79] [80] \
[81] [83] [84] [85] [87] [88] [91] [96]
0000000000000000000000000000000000000 1
.names [5] [9] [15] [18] [22] [29] [30] [31] [36] [38] [39] [40] [41] [49] \
[51] [52] [56] [57] [63] [65] [66] [69] [70] [73] [75] [79] [80] [83] [84] \
[85] [86] [87] [89] [90] [91] [98]
00000000000000000000000000000000000 1
.names [2] [3] [4] [9] [11] [19] [25] [28] [31] [32] [33] [35] [41] [42] [45] \
[46] [48] [49] [50] [51] [52] [53] [56] [59] [65] [67] [69] [71] [72] [78] \
[80] [81] [84] [86] [87] [88] [89] [91] [100]
00000000000000000000000000000000000000 1
.names [2] [3] [5] [9] [18] [22] [24] [28] [29] [30] [31] [41] [42] [44] [45] \
[48] [50] [55] [56] [58] [63] [64] [65] [67] [69] [70] [75] [77] [78] [79] \
[83] [84] [85] [87] [89] [90] [102]
000000000000000000000000000000000000 1
.names [7] [18] [20] [24] [25] [29] [30] [32] [33] [37] [39] [46] [47] [48] \
[49] [50] [51] [53] [55] [56] [57] [58] [59] [61] [62] [64] [66] [68] [70] \
[71] [72] [74] [75] [77] [79] [81] [82] [83] [84] [85] [86] [87] [88] [90] \
[91] [104]
000000000000000000000000000000000000000000000 1
.names [8] [10] [12] [17] [34] [40] [63] [65] [67] [73] [76] [78] [89] [106]
0000000000000 1
.names [8] [10] [12] [17] [24] [25] [29] [30] [32] [33] [34] [37] [39] [44] \
[48] [49] [50] [51] [52] [53] [54] [55] [57] [58] [60] [61] [62] [63] [64] \
[65] [66] [67] [68] [69] [71] [72] [73] [74] [76] [77] [78] [80] [81] [82] \
[83] [85] [86] [88] [89] [90] [91] [108]
000000000000000000000000000000000000000000000000000 1
.names [20] [40] [45] [46] [54] [65] [69] [80] [110]
00000000 1
.names [12] [17] [18] [34] [40] [44] [45] [54] [59] [60] [67] [69] [70] [73] \
[75] [76] [80] [84] [87] [89] [112]
00000000000000000000 1
.names [24] [29] [30] [32] [33] [37] [39] [42] [43] [44] [46] [48] [49] [50] \
[51] [53] [54] [55] [56] [57] [58] [59] [60] [61] [62] [63] [64] [66] [67] \
[68] [69] [70] [71] [72] [73] [74] [75] [76] [77] [78] [79] [80] [81] [82] \
[83] [84] [85] [86] [87] [88] [89] [90] [91] [114]
00000000000000000000000000000000000000000000000000000 1
.names [18] [44] [45] [54] [56] [59] [60] [65] [69] [70] [73] [75] [79] [80] \
[84] [87] [89] [116]
00000000000000000 1
.names [12] [14] [17] [18] [20] [26] [34] [56] [59] [63] [65] [67] [70] [75] \
[76] [78] [79] [84] [87] [118]
0000000000000000000 1
.names [7] [8] [10] [24] [25] [29] [30] [32] [33] [37] [39] [40] [42] [43] \
[44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56] [57] [58] \
[59] [60] [61] [62] [63] [64] [65] [66] [67] [68] [69] [70] [71] [72] [73] \
[74] [75] [76] [77] [78] [79] [80] [81] [82] [83] [84] [85] [86] [87] [88] \
[89] [90] [91] [120]
00000000000000000000000000000000000000000000000000000000000000 1
.names [0] [4] [5] [9] [122]
0000 1
.names [25] [59] [124]
00 1
.names [13] [18] [21] [23] [59] [67] [70] [80] [87] [126]
000000000 1
.names [4] [5] [9] [12] [17] [18] [128]
000000 1
.names [24] [25] [59] [130]
000 1
.names [2] [3] [29] [30] [132]
0000 1
.names [18] [32] [134]
00 1
.names [33] [35] [65] [136]
000 1
.names [39] [66] [69] [138]
000 1
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[140]
000000000000000 1
.end

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.model top
.inputs dest_x[0] dest_x[1] dest_x[2] dest_x[3] dest_x[4] dest_x[5] \
dest_x[6] dest_x[7] dest_x[8] dest_x[9] dest_x[10] dest_x[11] dest_x[12] \
dest_x[13] dest_x[14] dest_x[15] dest_x[16] dest_x[17] dest_x[18] \
dest_x[19] dest_x[20] dest_x[21] dest_x[22] dest_x[23] dest_x[24] \
dest_x[25] dest_x[26] dest_x[27] dest_x[28] dest_x[29] dest_y[0] dest_y[1] \
dest_y[2] dest_y[3] dest_y[4] dest_y[5] dest_y[6] dest_y[7] dest_y[8] \
dest_y[9] dest_y[10] dest_y[11] dest_y[12] dest_y[13] dest_y[14] \
dest_y[15] dest_y[16] dest_y[17] dest_y[18] dest_y[19] dest_y[20] \
dest_y[21] dest_y[22] dest_y[23] dest_y[24] dest_y[25] dest_y[26] \
dest_y[27] dest_y[28] dest_y[29]
.outputs outport[0] outport[1] outport[2] outport[3] outport[4] outport[5] \
outport[6] outport[7] outport[8] outport[9] outport[10] outport[11] \
outport[12] outport[13] outport[14] outport[15] outport[16] outport[17] \
outport[18] outport[19] outport[20] outport[21] outport[22] outport[23] \
outport[24] outport[25] outport[26] outport[27] outport[28] outport[29]
.names dest_x[9] dest_x[10] n92
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.names n95 n96 n97
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00 1
.names dest_x[12] n95 n99
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.names dest_x[13] n98 n102
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.end

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.model TOP
.inputs s1488_in_7_ s1488_in_6_ s1488_in_5_ s1488_in_4_ s1488_in_3_ \
s1488_in_2_ s1488_in_1_ s1488_in_0_ clock
.outputs s1488_out_18_ s1488_out_17_ s1488_out_16_ s1488_out_15_ s1488_out_14_ \
s1488_out_13_ s1488_out_12_ s1488_out_11_ s1488_out_10_ s1488_out_9_ \
s1488_out_8_ s1488_out_7_ s1488_out_6_ s1488_out_5_ s1488_out_4_ s1488_out_3_ \
s1488_out_2_ s1488_out_1_ s1488_out_0_
.latch N_N33 N_N356 re clock 2
.latch N_N34 N_N357 re clock 2
.latch N_N35 N_N358 re clock 2
.latch N_N36 N_N359 re clock 2
.latch N_N37 N_N360 re clock 2
.latch N_N38 N_N361 re clock 2
.names s1488_in_3_ n1 n3 n244 s1488_out_18_
1110 1
.names n4 s1488_out_17_
0 1
.names n5 s1488_out_16_
0 1
.names n6 s1488_out_15_
0 1
.names n7 s1488_out_14_
0 1
.names n10 n8 N_N361 n173 s1488_out_13_
1-0- 1
-100 1
.names n30 s1488_out_12_
0 1
.names n12 s1488_out_11_
0 1
.names n39 s1488_out_10_
0 1
.names s1488_in_4_ n14 n173 n210 s1488_out_9_
110- 1
11-0 1
.names n15 n16 n17 n18 s1488_out_8_
1--- 1
-1-- 1
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---1 1
.names n40 n42 n192 n290 s1488_out_7_
1--- 1
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--0- 1
---0 1
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0 1
.names n52 s1488_out_5_
0 1
.names n53 s1488_out_4_
0 1
.names n54 s1488_out_3_
0 1
.names n55 s1488_out_2_
0 1
.names n233 s1488_out_1_
0 1
.names n56 s1488_out_0_
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.names n114 N_N360 n1
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111- 1
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101- 1
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.names n19 N_N38
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.names n91 n92 N_N356 n90 n20
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11-1 1
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10-1 1
.names n112 n122 n249 n262 n23
11-- 1
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.names s1488_in_2_ n107 n116 n115 n26
-11- 1
01-1 1
.names n104 n113 n256 n27
11- 1
1-0 1
.names n22 n23 n24 n26 n27 n90 N_N35
1----- 1
-1---- 1
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----1- 1
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001- 1
-010 1
.names n28 N_N34
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-0-1 1
0-11 1
.names n84 n85 n103 n83
110 1
.names s1488_in_6_ n84 n88
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-1 1
.names s1488_in_2_ N_N356 n114 n89
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-1- 1
--0 1
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-110 1
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-110 1
.names n83 n86 n107 n122 n92
11-- 1
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1--0 1
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0-- 1
-0- 1
--1 1
.names s1488_in_3_ s1488_in_0_ n3 n93
101 1
.names s1488_in_2_ N_N358 n67 n226 n95
0-1- 1
01-0 1
.names N_N361 n159 n243 n246 n100
00-- 1
0-1- 1
-0-1 1
--11 1
.names n95 N_N357 n245 n247 n101
011- 1
0-11 1
.names s1488_in_6_ n132 n99
0- 1
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.names G16 G313 G328 G213
111 1
.names G317 G328 G235
11 1
.names G40 G41 G328 G249
111 1
.names G328 G267 G268
11 1
.names G0 G38 G328 G276
111 1
.names G317 G328 G282
11 1
.names G1 G39 G313 G117
111 1
.names G323 G281 G280 G277
111 1
.names G280 G42 G278
11 1
.names G318 G317 G328 G121
111 1
.names G280 G318 G40 G128
111 1
.names G38 G318 G232
11 1
.names G15 G318 G233
11 1
.names G318 G313 G251
11 1
.names G318 G317 G252
11 1
.names G42 G313 G40 G270
000 1
.names G318 G15 G14 G270 G271
1111 1
.names G328 G313 G317 G209
000 1
.names G39 G38 G245 G209 G210
1111 1
.names G41 G256 G225
0- 1
-0 1
.names G318 G225 G226
11 1
.names G42 G41 G280 G15 G176
0--- 1
-0-- 1
--0- 1
---0 1
.names G317 G176 G175
11 1
.names G280 G267 G198 G196
000 1
.names G8 G7 G6 G196 G197
1111 1
.names G113 G317 G262
0- 1
-0 1
.names G39 G38 G262 G263
111 1
.names G38 G281 G267 G147
000 1
.names G42 G313 G317 G39 G148
0000 1
.names G169 G170 G149
00 1
.names G256 G147 G148 G149 G150
1111 1
.names G160 G161 G162 G163 G157
0000 1
.names G280 G157 G158
11 1
.names G187 G188 G189 G190 G184
0000 1
.names G280 G184 G185
11 1
.names G193 G194 G173
00 1
.names G41 G40 G15 G173 G174
1111 1
.names G213 G214 G215 G212
000 1
.names G317 G39 G256 G212 G211
1111 1
.names G234 G235 G222
00 1
.names G16 G222 G223
11 1
.names G282 G283 G274
00 1
.names G318 G4 G274 G272
111 1
.names G109 G110 G111 G40 G266
0--- 1
-0-- 1
--0- 1
---0 1
.names G318 G266 G264
11 1
.names G8 G7 G6 G131 G293
0--- 1
-0-- 1
--0- 1
---0 1
.names G16 G293 G294
11 1
.names G276 G277 G278 G279 G154
0000 1
.names G313 G317 G318 G154 G152
1111 1
.names G41 G3 G216
00 1
.names G236 G237 G217
0- 1
-0 1
.names G2 G323 G216 G217 G218
1111 1
.names G249 G250 G251 G252 G153
0000 1
.names G38 G16 G256 G153 G151
1111 1
.names G285 G286 G287 G275
0-- 1
-0- 1
--0 1
.names G40 G39 G275 G273
111 1
.names G106 G107 G108 G257
0-- 1
-0- 1
--0 1
.names G318 G280 G257 G258
111 1
.names G223 G224 G220
00 1
.names G318 G220 G219
11 1
.names G263 G264 G265 G260
000 1
.names G41 G260 G259
11 1
.names G150 G151 G152 G155 G89
1--- 1
-1-- 1
--1- 1
---1 1
.names G62 G63 G64 G61 G92
0--- 1
-0-- 1
--0- 1
---0 1
.names G70 G71 G72 G69 G95
0--- 1
-0-- 1
--0- 1
---0 1
.names G78 G79 G80 G77 G98
0--- 1
-0-- 1
--0- 1
---0 1
.names G85 G86 G87 G84 G101
0--- 1
-0-- 1
--0- 1
---0 1
.names G10 G11 G126
1- 1
-1 1
.names G11 G12 G124
1- 1
-1 1
.names G10 G12 G125
1- 1
-1 1
.names G41 G40 G1 G107
1-- 1
-1- 1
--1 1
.names G16 G41 G145
1- 1
-1 1
.names G5 G41 G243
1- 1
-1 1
.names G15 G42 G111
1- 1
-1 1
.names G16 G42 G144
1- 1
-1 1
.names G40 G41 G42 G239
1-- 1
-1- 1
--1 1
.names G42 G5 G287
1- 1
-1 1
.names G39 G42 G115
1- 1
-1 1
.names G38 G39 G41 G183
1-- 1
-1- 1
--1 1
.names G16 G39 G40 G237
1-- 1
-1- 1
--1 1
.names G4 G39 G246
1- 1
-1 1
.names G203 G202 G112 G198 G113
1--- 1
-1-- 1
--1- 1
---1 1
.names G171 G11 G12 G42 G132
1--- 1
-1-- 1
--1- 1
---1 1
.names G10 G172 G12 G42 G133
1--- 1
-1-- 1
--1- 1
---1 1
.names G14 G267 G38 G39 G182
1--- 1
-1-- 1
--1- 1
---1 1
.names G14 G267 G40 G42 G238
1--- 1
-1-- 1
--1- 1
---1 1
.names G256 G317 G241
1- 1
-1 1
.names G4 G281 G136
1- 1
-1 1
.names G39 G313 G116
1- 1
-1 1
.names G42 G313 G286
1- 1
-1 1
.names G328 G15 G108
1- 1
-1 1
.names G201 G267 G328 G109
1-- 1
-1- 1
--1 1
.names G256 G313 G328 G240
1-- 1
-1- 1
--1 1
.names G41 G328 G242
1- 1
-1 1
.names G281 G328 G244
1- 1
-1 1
.names G280 G42 G110
1- 1
-1 1
.names G280 G42 G134
1- 1
-1 1
.names G280 G40 G135
1- 1
-1 1
.names G267 G318 G328 G114
1-- 1
-1- 1
--1 1
.names G318 G317 G328 G236
1-- 1
-1- 1
--1 1
.names G245 G318 G248
1- 1
-1 1
.names G42 G41 G319
0- 1
-0 1
.names G317 G318 G38 G319 G321
1--- 1
-1-- 1
--1- 1
---1 1
.names G16 G3 G181 G1 G178
0000 1
.names G41 G178 G180
1- 1
-1 1
.names G42 G41 G40 G73
0-- 1
-0- 1
--0 1
.names G281 G267 G201 G74
000 1
.names G39 G4 G73 G74 G78
1--- 1
-1-- 1
--1- 1
---1 1
.names G42 G313 G284
0- 1
-0 1
.names G3 G2 G1 G284 G285
1--- 1
-1-- 1
--1- 1
---1 1
.names G144 G145 G59
0- 1
-0 1
.names G40 G318 G4 G59 G63
1--- 1
-1-- 1
--1- 1
---1 1
.names G328 G40 G15 G9 G105
0--- 1
-0-- 1
--0- 1
---0 1
.names G8 G7 G203 G105 G106
1--- 1
-1-- 1
--1- 1
---1 1
.names G328 G313 G304
00 1
.names G40 G318 G16 G304 G308
1--- 1
-1-- 1
--1- 1
---1 1
.names G328 G313 G316
0- 1
-0 1
.names G40 G39 G38 G316 G320
1--- 1
-1-- 1
--1- 1
---1 1
.names G40 G280 G50
00 1
.names G328 G313 G39 G50 G52
1--- 1
-1-- 1
--1- 1
---1 1
.names G42 G41 G280 G137
000 1
.names G317 G137 G139
1- 1
-1 1
.names G42 G41 G280 G253
000 1
.names G317 G253 G255
1- 1
-1 1
.names G9 G8 G204
0- 1
-0 1
.names G228 G229 G205
0- 1
-0 1
.names G202 G203 G204 G205 G207
1--- 1
-1-- 1
--1- 1
---1 1
.names G141 G142 G143 G305
000 1
.names G39 G38 G305 G309
1-- 1
-1- 1
--1 1
.names G41 G40 G318 G16 G57
0--- 1
-0-- 1
--0- 1
---0 1
.names G132 G133 G134 G58
0-- 1
-0- 1
--0 1
.names G267 G4 G57 G58 G62
1--- 1
-1-- 1
--1- 1
---1 1
.names G135 G136 G303
0- 1
-0 1
.names G328 G313 G39 G303 G307
1--- 1
-1-- 1
--1- 1
---1 1
.names G246 G247 G248 G81
0-- 1
-0- 1
--0 1
.names G328 G313 G317 G81 G85
1--- 1
-1-- 1
--1- 1
---1 1
.names G195 G280 G177
00 1
.names G174 G175 G177 G67
1-- 1
-1- 1
--1 1
.names G42 G41 G317 G65
0-- 1
-0- 1
--0 1
.names G197 G281 G66
00 1
.names G318 G4 G65 G66 G70
1--- 1
-1-- 1
--1- 1
---1 1
.names G103 G328 G317 G104 G155
0000 1
.names G207 G206 G75
0- 1
-0 1
.names G40 G281 G4 G75 G79
1--- 1
-1-- 1
--1- 1
---1 1
.names G158 G159 G60
00 1
.names G317 G318 G60 G64
1-- 1
-1- 1
--1 1
.names G185 G186 G68
00 1
.names G317 G318 G68 G72
1-- 1
-1- 1
--1 1
.names G39 G281 G4 G67 G71
1--- 1
-1-- 1
--1- 1
---1 1
.names G271 G272 G273 G82
000 1
.names G38 G82 G86
1- 1
-1 1
.names G218 G219 G221 G76
000 1
.names G38 G76 G80
1- 1
-1 1
.names G258 G259 G261 G83
000 1
.names G281 G83 G87
1- 1
-1 1
.names G124 G125 G126 G256 G123
0--- 1
-0-- 1
--0- 1
---0 1
.names G41 G317 G39 G256 G295
0--- 1
-0-- 1
--0- 1
---0 1
.names G313 G317 G39 G15 G291
0--- 1
-0-- 1
--0- 1
---0 1
.names G313 G317 G39 G15 G329
0--- 1
-0-- 1
--0- 1
---0 1
.names G40 G39 G280 G130 G48
0--- 1
-0-- 1
--0- 1
---0 1
.names G40 G39 G280 G5 G56
0--- 1
-0-- 1
--0- 1
---0 1
.names G313 G40 G39 G280 G289
0--- 1
-0-- 1
--0- 1
---0 1
.names G41 G40 G39 G280 G297
0--- 1
-0-- 1
--0- 1
---0 1
.names G313 G40 G39 G280 G311
0--- 1
-0-- 1
--0- 1
---0 1
.names G40 G39 G280 G16 G314
0--- 1
-0-- 1
--0- 1
---0 1
.names G313 G40 G39 G280 G326
0--- 1
-0-- 1
--0- 1
---0 1
.names G39 G38 G119
00 1
.names G281 G3 G323 G119 G301
0--- 1
-0-- 1
--0- 1
---0 1
.names G317 G318 G280 G15 G44
0--- 1
-0-- 1
--0- 1
---0 1
.names G41 G317 G318 G280 G54
0--- 1
-0-- 1
--0- 1
---0 1
.names G318 G280 G281 G156
0-- 1
-0- 1
--0 1
.names G318 G280 G15 G14 G299
0--- 1
-0-- 1
--0- 1
---0 1
.names G182 G183 G179
0- 1
-0 1
.names G238 G239 G240 G241 G224
0--- 1
-0-- 1
--0- 1
---0 1
.names G242 G243 G244 G40 G227
0--- 1
-0-- 1
--0- 1
---0 1
.names G280 G267 G198 G131
000 1
.names G114 G115 G116 G317 G269
0--- 1
-0-- 1
--0- 1
---0 1
.names G267 G123 G122
00 1
.names G318 G280 G16 G122 G46
0--- 1
-0-- 1
--0- 1
---0 1
.names G180 G328 G317 G179 G69
0--- 1
-0-- 1
--0- 1
---0 1
.names G318 G256 G138
00 1
.names G139 G138 G306
0- 1
-0 1
.names G318 G256 G254
00 1
.names G255 G254 G84
0- 1
-0 1
.names G127 G128 G129 G51
000 1
.names G3 G181 G1 G156 G146
0000 1
.names G328 G313 G317 G146 G61
0--- 1
-0-- 1
--0- 1
---0 1
.names G231 G232 G233 G206
000 1
.names G210 G211 G77
00 1
.names G166 G167 G165
00 1
.names G199 G200 G192
00 1
.names G117 G118 G104
00 1
.names G120 G121 G324
00 1
.names G164 G165 G159
00 1
.names G191 G192 G186
00 1
.names G226 G227 G221
00 1
.names G268 G269 G261
00 1
.end

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#
# Written by e2fmt Tue Mar 31 16:20:04 1998
############################################
.model top
.inputs v_6_ v_7_ v_4_ v_5_ v_2_ v_3_ v_0_ v_1_
.outputs sqrt_3_ sqrt_2_ sqrt_1_ sqrt_0_
# connect ports to nets with different names
.names v_6_ n_n74
1 1
.names n_n81 sqrt_3_
1 1
.names v_7_ n_n75
1 1
.names n_n79 sqrt_2_
1 1
.names v_4_ n_n83
1 1
.names n_n77 sqrt_1_
1 1
.names v_5_ n_n73
1 1
.names n_n72 sqrt_0_
1 1
.names v_2_ n_n80
1 1
.names v_3_ n_n82
1 1
.names v_0_ n_n76
1 1
.names v_1_ n_n78
1 1
# instance g_g159
.names n_n146 n_n21 n_n149 n_n145
1-0 1
-11 1
# instance g_g148
.names n_n120 n_n93 n_n147
10 1
01 1
# instance g_g137
.names n_n20 n_n20 n_n21 n_n95
1-0 1
-11 1
# instance g_g126
.names n_n32 n_n6 n_tmp34
10 1
01 1
# instance g_g115
.names n_n78 n_n66 n_n15
1- 1
-1 1
# instance g_g104
.names n_n21 n_n21 n_n72 n_n77
1-0 1
-11 1
# instance g_g158
.names n_n29 n_n1 n_tmp74
10 1
01 1
# instance g_g149
.names n_n114 n_n21 n_n149
10 1
01 1
# instance g_g136
.names n_n124 n_tmp70 n_n20 n_n126
1-0 1
-11 1
# instance g_g127
.names n_n4 n_n5 n_tmp36
10 1
01 1
# instance g_g114
.names n_n92 n_n26 n_n99
11 1
# instance g_g105
.names n_n140 n_n94 n_n142 n_n132
1-0 1
-11 1
# instance g_g168
.names n_n76 n_n76 n_n49 n_n86
1-0 1
-11 1
# instance g_g135
.names n_n117 n_tmp71 n_n20 n_n116
1-0 1
-11 1
# instance g_g124
.names n_n34 n_n8 n_tmp32
10 1
01 1
# instance g_g117
.names n_n73 n_n64 n_n13
1- 1
-1 1
# instance g_g106
.names n_n141 n_n20 n_n143 n_n140
1-0 1
-11 1
# instance g_g169
.names n_n78 n_tmp36 n_n49 n_n88
1-0 1
-11 1
# instance g_g134
.names n_n123 n_tmp69 n_n20 n_n122
1-0 1
-11 1
# instance g_g125
.names n_n33 n_n7 n_tmp35
10 1
01 1
# instance g_g116
.names n_n83 n_n65 n_n14
1- 1
-1 1
# instance g_g107
.names n_n116 n_n94 n_n142
10 1
01 1
# instance g_g133
.names n_n119 n_tmp72 n_n20 n_n121
1-0 1
-11 1
# instance g_g122
.names n_n109 n_n10 n_tmp30
10 1
01 1
# instance g_g111
.names n_n111 n_n59 n_n17
1- 1
-1 1
# instance g_g100
.names n_n37 n_n52 n_tmp108
10 1
01 1
# instance g_g9
.names n_n83 n_n9
0 1
# instance g_g132
.names n_n111 n_tmp73 n_n20 n_n110
1-0 1
-11 1
# instance g_g123
.names n_n35 n_n9 n_tmp33
10 1
01 1
# instance g_g110
.names n_n113 n_n60 n_n18
1- 1
-1 1
# instance g_g101
.names n_n124 n_n49 n_n135
10 1
01 1
# instance g_g131
.names n_n113 n_tmp74 n_n20 n_n115
1-0 1
-11 1
# instance g_g120
.names n_n74 n_n31 n_n109
11 1
# instance g_g113
.names n_n16 n_n100 n_n101
11 1
# instance g_g102
.names n_n134 n_n49 n_n135 n_n133
1-0 1
-11 1
# instance g_g130
.names n_n88 n_tmp75 n_n20 n_n87
1-0 1
-11 1
# instance g_g121
.names n_n31 n_n74 n_tmp31
10 1
01 1
# instance g_g112
.names n_n119 n_n27 n_n100
11 1
# instance g_g103
.names n_n95 n_n95 n_n72 n_n79
1-0 1
-11 1
# instance g_g162
.names n_n74 n_tmp31 n_n49 n_n124
1-0 1
-11 1
# instance g_g151
.names n_n129 n_n124 n_n156
11 1
# instance g_g140
.names n_n87 n_tmp114 n_n21 n_n89
1-0 1
-11 1
# instance g_g5
.names n_n78 n_n5
0 1
# instance g_g163
.names n_n75 n_tmp30 n_n49 n_n123
1-0 1
-11 1
# instance g_g150
.names n_n129 n_n124 n_n92
10 1
01 1
# instance g_g141
.names n_n122 n_tmp108 n_n21 n_n127
1-0 1
-11 1
# instance g_g6
.names n_n82 n_n6
0 1
# instance g_g160
.names n_n28 n_n0 n_tmp73
10 1
01 1
# instance g_g153
.names n_n27 n_n119 n_tmp72
10 1
01 1
# instance g_g142
.names n_n126 n_tmp109 n_n21 n_n125
1-0 1
-11 1
# instance g_g7
.names n_n80 n_n7
0 1
# instance g_g161
.names n_n145 n_n95 n_n148 n_n139
1-0 1
-11 1
# instance g_g152
.names n_n139 n_n93 n_n147 n_n138
1-0 1
-11 1
# instance g_g143
.names n_n115 n_tmp113 n_n21 n_n114
1-0 1
-11 1
# instance g_g8
.names n_n73 n_n8
0 1
# instance g_g166
.names n_n80 n_tmp35 n_n49 n_n113
1-0 1
-11 1
# instance g_g155
.names n_n26 n_n92 n_tmp70
10 1
01 1
# instance g_g144
.names n_n116 n_tmp110 n_n21 n_n118
1-0 1
-11 1
# instance g_g119
.names n_n82 n_n62 n_n11
1- 1
-1 1
# instance g_g108
.names n_n121 n_n20 n_n143
10 1
01 1
# instance g_g1
.names n_n113 n_n1
0 1
# instance g_g167
.names n_n82 n_tmp34 n_n49 n_n111
1-0 1
-11 1
# instance g_g154
.names n_n100 n_n16 n_tmp71
10 1
01 1
# instance g_g145
.names n_n110 n_tmp112 n_n21 n_n112
1-0 1
-11 1
# instance g_g118
.names n_n80 n_n63 n_n12
1- 1
-1 1
# instance g_g109
.names n_n88 n_n61 n_n19
1- 1
-1 1
# instance g_g2
.names n_n61 n_n2
0 1
# instance g_g164
.names n_n83 n_tmp33 n_n49 n_n119
1-0 1
-11 1
# instance g_g157
.names n_n2 n_n3 n_tmp75
10 1
01 1
# instance g_g146
.names n_n121 n_tmp111 n_n21 n_n120
1-0 1
-11 1
# instance g_g139
.names n_n91 n_n91 n_n21 n_n90
1-0 1
-11 1
# instance g_g128
.names n_n49 n_n49 n_n20 n_n94
1-0 1
-11 1
# instance g_g3
.names n_n88 n_n3
0 1
# instance g_g165
.names n_n73 n_tmp32 n_n49 n_n117
1-0 1
-11 1
# instance g_g156
.names n_n25 n_n51 n_tmp69
10 1
01 1
# instance g_g147
.names n_n112 n_n95 n_n148
10 1
01 1
# instance g_g138
.names n_n94 n_n94 n_n21 n_n93
1-0 1
-11 1
# instance g_g129
.names n_n86 n_n86 n_n20 n_n91
1-0 1
-11 1
# instance g_g4
.names n_n66 n_n4
0 1
# instance g_g94
.names n_n22 n_n23 n_tmp114
10 1
01 1
# instance g_g83
.names n_n86 n_n30 n_n61
11 1
# instance g_g72
.names n_n153 n_n102 n_n41
1- 1
-1 1
# instance g_g61
.names n_n52 n_n131 n_n130
11 1
# instance g_g50
.names n_n126 n_n55
0 1
# instance g_g95
.names n_n42 n_n85 n_tmp111
10 1
01 1
# instance g_g82
.names n_n108 n_n73 n_n31
1- 1
-1 1
# instance g_g73
.names n_n155 n_n87 n_n40
1- 1
-1 1
# instance g_g60
.names n_n53 n_n136 n_n144
11 1
# instance g_g51
.names n_n125 n_n56
0 1
# instance g_g96
.names n_n41 n_n84 n_tmp110
10 1
01 1
# instance g_g81
.names n_n105 n_n80 n_n32
1- 1
-1 1
# instance g_g70
.names n_n87 n_n68 n_n43
1- 1
-1 1
# instance g_g63
.names n_n117 n_n119 n_n50
1- 1
-1 1
# instance g_g52
.names n_n118 n_n57
0 1
# instance g_g97
.names n_n40 n_n115 n_tmp113
10 1
01 1
# instance g_g80
.names n_n104 n_n78 n_n33
1- 1
-1 1
# instance g_g71
.names n_n152 n_n110 n_n42
1- 1
-1 1
# instance g_g62
.names n_n51 n_n133 n_n128
11 1
# instance g_g53
.names n_n58 n_n146
0 1
# instance g_g0
.names n_n111 n_n0
0 1
# instance g_g98
.names n_n151 n_n44 n_tmp112
10 1
01 1
# instance g_g43
.names n_n48 n_n150
0 1
# instance g_g32
.names n_n76 n_n36
0 1
# instance g_g21
.names n_n130 n_n21
0 1
# instance g_g10
.names n_n75 n_n10
0 1
# instance g_g99
.names n_n38 n_n55 n_tmp109
10 1
01 1
# instance g_g42
.names n_n71 n_n47
0 1
# instance g_g33
.names n_n38 n_n67
0 1
# instance g_g20
.names n_n128 n_n20
0 1
# instance g_g11
.names n_n11 n_n106
0 1
# instance g_g41
.names n_n70 n_n46
0 1
# instance g_g30
.names n_n34 n_n64
0 1
# instance g_g23
.names n_n87 n_n23
0 1
# instance g_g12
.names n_n12 n_n105
0 1
# instance g_g40
.names n_n69 n_n45
0 1
# instance g_g31
.names n_n35 n_n65
0 1
# instance g_g22
.names n_n68 n_n22
0 1
# instance g_g13
.names n_n13 n_n108
0 1
# instance g_g69
.names n_n44 n_n151 n_n152
11 1
# instance g_g58
.names n_n55 n_n132 n_n131
11 1
# instance g_g47
.names n_n122 n_n52
0 1
# instance g_g36
.names n_n41 n_n70
0 1
# instance g_g25
.names n_n28 n_n59
0 1
# instance g_g14
.names n_n14 n_n107
0 1
# instance g_g68
.names n_n115 n_n45 n_n151
11 1
# instance g_g59
.names n_n110 n_n115 n_n54
1- 1
-1 1
# instance g_g46
.names n_n123 n_n51
0 1
# instance g_g37
.names n_n42 n_n71
0 1
# instance g_g24
.names n_n94 n_n24
0 1
# instance g_g15
.names n_n15 n_n104
0 1
# instance g_g89
.names n_n93 n_n93 n_n72 n_n81
1-0 1
-11 1
# instance g_g78
.names n_n106 n_n82 n_n35
1- 1
-1 1
# instance g_g45
.names n_n50 n_n134
0 1
# instance g_g34
.names n_n91 n_n39
0 1
# instance g_g27
.names n_n86 n_n30
0 1
# instance g_g16
.names n_n117 n_n16
0 1
# instance g_g88
.names n_n99 n_n156 n_n25
1- 1
-1 1
# instance g_g79
.names n_n107 n_n83 n_n34
1- 1
-1 1
# instance g_g44
.names n_n49 n_n129
0 1
# instance g_g35
.names n_n40 n_n69
0 1
# instance g_g26
.names n_n29 n_n60
0 1
# instance g_g17
.names n_n17 n_n97
0 1
# instance g_g90
.names n_n24 n_n116 n_n84
10 1
01 1
# instance g_g87
.names n_n101 n_n117 n_n26
1- 1
-1 1
# instance g_g76
.names n_n150 n_n126 n_n37
1- 1
-1 1
# instance g_g65
.names n_n126 n_n67 n_n48
1- 1
-1 1
# instance g_g54
.names n_n144 n_n72
0 1
# instance g_g29
.names n_n33 n_n63
0 1
# instance g_g18
.names n_n18 n_n96
0 1
# instance g_g91
.names n_n128 n_n121 n_n85
10 1
01 1
# instance g_g86
.names n_n97 n_n111 n_n27
1- 1
-1 1
# instance g_g77
.names n_n76 n_n36 n_n66
11 1
# instance g_g64
.names n_n75 n_n74 n_n49
1- 1
-1 1
# instance g_g55
.names n_n89 n_n90 n_n58
1- 1
-1 1
# instance g_g28
.names n_n32 n_n62
0 1
# instance g_g19
.names n_n19 n_n98
0 1
# instance g_g92
.names n_n128 n_n121 n_n102
11 1
# instance g_g85
.names n_n96 n_n113 n_n28
1- 1
-1 1
# instance g_g74
.names n_n91 n_n39 n_n68
11 1
# instance g_g67
.names n_n84 n_n46 n_n154
11 1
# instance g_g56
.names n_n57 n_n138 n_n137
11 1
# instance g_g49
.names n_n54 n_n141
0 1
# instance g_g38
.names n_n43 n_n155
0 1
# instance g_g93
.names n_n24 n_n116 n_n103
11 1
# instance g_g84
.names n_n98 n_n88 n_n29
1- 1
-1 1
# instance g_g75
.names n_n154 n_n103 n_n38
1- 1
-1 1
# instance g_g66
.names n_n85 n_n47 n_n153
11 1
# instance g_g57
.names n_n56 n_n137 n_n136
11 1
# instance g_g48
.names n_n127 n_n53
0 1
# instance g_g39
.names n_n110 n_n44
0 1
.end

1142
fpga_flow/benchmarks/FPGA_SPICE_bench/ss_pcm.blif Normal file
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515
fpga_flow/benchmarks/FPGA_SPICE_bench/steppermotordrive.blif Normal file
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# Benchmark "steppermotordrive" written by ABC on Mon Aug 29 15:33:12 2005
.model steppermotordrive
.inputs clock Direction StepEnable ProvideStaticHolding
.outputs StepDrive[0] StepDrive[1] StepDrive[2] StepDrive[3]
.latch \StepCounter_reg[16]_in \StepCounter_reg[16] 2
.latch \StepCounter_reg[15]_in \StepCounter_reg[15] 2
.latch \StepCounter_reg[11]_in \StepCounter_reg[11] 2
.latch \StepDrive_reg[0]_in \StepDrive_reg[0] 2
.latch \StepDrive_reg[1]_in \StepDrive_reg[1] 2
.latch \StepCounter_reg[17]_in \StepCounter_reg[17] 2
.latch \StepCounter_reg[12]_in \StepCounter_reg[12] 2
.latch \StepCounter_reg[14]_in \StepCounter_reg[14] 2
.latch \state_reg[1]_in \state_reg[1] 2
.latch \StepDrive_reg[2]_in \StepDrive_reg[2] 2
.latch \StepCounter_reg[8]_in \StepCounter_reg[8] 2
.latch \StepCounter_reg[10]_in \StepCounter_reg[10] 2
.latch \StepDrive_reg[3]_in \StepDrive_reg[3] 2
.latch InternalStepEnable_reg_in InternalStepEnable_reg 2
.latch \StepCounter_reg[13]_in \StepCounter_reg[13] 2
.latch \StepCounter_reg[7]_in \StepCounter_reg[7] 2
.latch \StepCounter_reg[3]_in \StepCounter_reg[3] 2
.latch \StepCounter_reg[6]_in \StepCounter_reg[6] 2
.latch \state_reg[0]_in \state_reg[0] 2
.latch \StepCounter_reg[2]_in \StepCounter_reg[2] 2
.latch \StepCounter_reg[9]_in \StepCounter_reg[9] 2
.latch \StepCounter_reg[0]_in \StepCounter_reg[0] 2
.latch \StepCounter_reg[4]_in \StepCounter_reg[4] 2
.latch \StepCounter_reg[5]_in \StepCounter_reg[5] 2
.latch \StepCounter_reg[1]_in \StepCounter_reg[1] 2
.names [33]
0
.names [34]
1
.names \StepCounter_reg[16] [35]
1 1
.names \StepCounter_reg[15] [36]
1 1
.names \StepCounter_reg[11] [37]
1 1
.names \StepDrive_reg[0] StepDrive[0]
1 1
.names \StepDrive_reg[1] StepDrive[1]
1 1
.names [42] \StepCounter_reg[16]_in
0 1
.names \StepCounter_reg[17] [41]
1 1
.names [54] [100] [42]
11 0
.names [65] [95] \StepDrive_reg[0]_in
11 0
.names [63] [95] \StepDrive_reg[1]_in
11 0
.names \StepCounter_reg[12] [45]
1 1
.names \StepCounter_reg[14] [46]
1 1
.names \state_reg[1] [47]
1 1
.names \StepDrive_reg[2] StepDrive[2]
1 1
.names \StepCounter_reg[8] [49]
1 1
.names \StepCounter_reg[10] [50]
1 1
.names \StepDrive_reg[3] StepDrive[3]
1 1
.names InternalStepEnable_reg [52]
1 1
.names \StepCounter_reg[13] [53]
1 1
.names [143] [35] [241] [54]
01- 1
1-1 1
.names \StepCounter_reg[7] [55]
1 1
.names \StepCounter_reg[3] [56]
1 1
.names \StepCounter_reg[6] [57]
1 1
.names \state_reg[0] [58]
1 1
.names \StepCounter_reg[2] [59]
1 1
.names \StepCounter_reg[9] [60]
1 1
.names \StepCounter_reg[0] [61]
1 1
.names [78] [95] \StepDrive_reg[2]_in
11 0
.names [100] StepDrive[1] [75] [63]
11- 0
--1 0
.names [109] [146] [76] \state_reg[1]_in
00- 1
--0 1
.names [100] StepDrive[0] [87] [65]
11- 0
--1 0
.names [84] [100] \StepCounter_reg[14]_in
11 1
.names [169] [100] \StepCounter_reg[13]_in
11 1
.names [77] InternalStepEnable_reg_in
0 1
.names [93] [98] \StepCounter_reg[10]_in
00 1
.names \StepCounter_reg[4] [70]
1 1
.names \StepCounter_reg[5] [71]
1 1
.names \StepCounter_reg[1] [72]
1 1
.names [89] [95] \StepDrive_reg[3]_in
11 0
.names [92] [100] \StepCounter_reg[8]_in
11 1
.names [119] [146] [75]
00 1
.names [146] [47] [76]
11 0
.names [100] [133] StepEnable [77]
11- 0
--1 0
.names [131] [178] [179] StepDrive[2] [78]
11-- 0
--11 0
.names [125] [58] [259] \state_reg[0]_in
01- 1
1-1 1
.names [107] [97] \StepCounter_reg[3]_in
00 1
.names [97] [230] \StepCounter_reg[0]_in
00 1
.names [108] [98] \StepCounter_reg[2]_in
00 1
.names [101] [97] \StepCounter_reg[9]_in
00 1
.names [132] [103] [84]
01 1
10 1
.names [96] [97] \StepCounter_reg[7]_in
00 1
.names [106] [97] \StepCounter_reg[6]_in
00 1
.names [118] [146] [87]
00 1
.names [105] [178] \StepCounter_reg[4]_in
00 1
.names [126] [223] [179] StepDrive[3] [89]
11-- 0
--11 0
.names [114] [100] \StepCounter_reg[1]_in
11 1
.names [104] [178] \StepCounter_reg[5]_in
00 1
.names [151] [117] [102] [92]
00- 1
--0 1
.names [204] [236] [99] [93]
11- 0
--1 0
.names [161] [94]
0 1
.names [136] [223] [95]
11 0
.names [148] [234] [96]
01 1
10 1
.names [100] [97]
0 1
.names [259] [98]
0 1
.names [204] [236] [99]
00 1
.names [223] [100]
0 1
.names [60] [157] [101]
01 1
10 1
.names [151] [117] [102]
11 0
.names [111] [204] [103]
00 1
.names [71] [229] [104]
01 1
10 1
.names [70] [153] [105]
01 1
10 1
.names [135] [210] [106]
01 1
10 1
.names [122] [233] [107]
01 1
10 1
.names [113] [128] [110] [108]
11- 0
--1 0
.names [124] Direction [112] [109]
11- 0
--1 0
.names [113] [128] [110]
00 1
.names [244] [186] [111]
11 0
.names [119] Direction [112]
00 1
.names [196] [113]
0 1
.names [130] [230] [114]
01 1
10 1
.names [71] [55] [115]
11 0
.names [217] [116]
0 1
.names [194] [117]
0 1
.names [124] [118]
0 1
.names [58] [47] [134] [119]
11- 0
--1 0
.names [140] [215] [120]
00 1
.names [138] [170] [121]
00 1
.names [202] [122]
0 1
.names [140] [123]
0 1
.names [47] [58] [124]
01 1
10 1
.names [52] [58] [125]
01 1
10 1
.names [47] [142] [126]
00 1
.names [139] [140] [127]
11 0
.names [253] [128]
0 1
.names [215] [129]
0 1
.names [190] [130]
0 1
.names [47] [52] [131]
11 1
.names [138] [132]
0 1
.names [142] [133]
0 1
.names [58] [47] [134]
00 1
.names [228] [135]
0 1
.names ProvideStaticHolding [52] [136]
00 1
.names [37] [137]
0 1
.names [46] [138]
0 1
.names [53] [139]
0 1
.names [45] [140]
0 1
.names [55] [141]
0 1
.names [52] [142]
0 1
.names [35] [143]
0 1
.names [60] [144]
0 1
.names [60] [236] [145]
11 0
.names [147] [52] [146]
11 0
.names [180] [147]
0 1
.names [227] [148]
0 1
.names [248] [197] [150] [149]
111 0
.names [228] [202] [150]
00 1
.names [152] [153] [151]
00 0
.names [191] [232] [152]
00 0
.names [201] [154] [153]
11 0
.names [192] [154]
0 1
.names [115] [155]
0 1
.names [140] [144] [156]
00 0
.names [158] [157]
0 1
.names [229] [182] [158]
00 1
.names [145] [160] [159]
00 1
.names [227] [194] [160]
00 0
.names [168] [161]
0 1
.names [137] [162]
0 1
.names [36] [163]
0 1
.names [165] \StepCounter_reg[11]_in
0 1
.names [166] [259] [165]
11 0
.names [94] [129] [167] [166]
00- 1
--0 1
.names [168] [37] [167]
11 0
.names [235] [159] [168]
11 0
.names [170] [171] [169]
01 1
10 1
.names [53] [170]
0 1
.names [172] [181] [189] [171]
111 0
.names [229] [172]
0 1
.names [174] [177] [178] \StepCounter_reg[15]_in
11- 0
--1 0
.names [175] [36] [174]
11 0
.names [161] [176] [175]
11 0
.names [120] [121] [176]
11 1
.names [121] [120] [161] [163] [177]
1111 0
.names [179] [178]
0 1
.names [180] [179]
1 1
.names [225] [224] [180]
11 0
.names [182] [181]
0 1
.names [193] [155] [182]
11 0
.names [184] [185] [183]
00 1
.names [231] [35] [184]
11 0
.names [186] [187] [188] [185]
111 0
.names [116] [186]
0 1
.names [156] [187]
0 1
.names [121] [36] [188]
11 1
.names [156] [116] [189]
00 1
.names [252] [190]
1 1
.names [70] [71] [191]
11 0
.names [59] [56] [192]
11 0
.names [194] [228] [193]
00 1
.names [49] [194]
0 1
.names [46] [36] [195]
00 0
.names [252] [250] [196]
00 1
.names [237] [203] [197]
00 1
.names [191] [192] [198]
00 1
.names [228] [141] [199]
00 1
.names [194] [250] [200]
00 0
.names [250] [190] [201]
00 1
.names [56] [202]
0 1
.names [70] [203]
0 1
.names [205] [207] [148] [193] [204]
1111 0
.names [202] [206] [205]
00 1
.names [59] [71] [70] [206]
111 0
.names [208] [250] [207]
00 1
.names [209] [60] [208]
11 0
.names [252] [209]
0 1
.names [211] [61] [213] [210]
111 0
.names [212] [202] [211]
00 1
.names [209] [212]
0 1
.names [206] [213]
0 1
.names [200] [214]
0 1
.names [37] [215]
0 1
.names [226] [217] [49] [216]
111 0
.names [37] [50] [217]
11 1
.names [127] [195] [218]
00 1
.names [220] \StepCounter_reg[12]_in
0 1
.names [221] [222] [100] [220]
111 0
.names [123] [246] [221]
00 0
.names [246] [123] [222]
11 0
.names [260] [223]
0 1
.names [216] [218] [239] [224]
111 0
.names [41] [35] [225]
11 1
.names [228] [227] [226]
11 0
.names [55] [227]
0 1
.names [57] [228]
0 1
.names [250] [251] [229]
00 0
.names [250] [230]
0 1
.names [251] [231]
0 1
.names [199] [232]
0 1
.names [248] [233]
0 1
.names [235] [234]
0 1
.names [149] [235]
0 1
.names [50] [236]
1 1
.names [71] [237]
0 1
.names [239] [238]
0 1
.names [162] [236] [60] [239]
111 0
.names [190] [232] [240]
00 1
.names [242] [240] [238] [214] [241]
1111 0
.names [243] [242]
0 1
.names [198] [244] [245] [243]
111 0
.names [170] [140] [244]
00 1
.names [138] [163] [245]
00 1
.names [247] [246]
0 1
.names [240] [238] [214] [198] [247]
1111 0
.names [249] [248]
0 1
.names [61] [72] [59] [249]
111 0
.names [61] [250]
0 1
.names [209] [59] [56] [70] [251]
1111 0
.names [72] [252]
0 1
.names [59] [253]
0 1
.names [255] [257] [98] \StepCounter_reg[17]_in
11- 0
--1 0
.names [256] [41] [255]
11 0
.names [183] [181] [230] [256]
111 0
.names [183] [181] [230] [258] [257]
1111 0
.names [41] [258]
0 1
.names [260] [259]
1 1
.names [224] [225] [260]
11 0
.end

881
fpga_flow/benchmarks/FPGA_SPICE_bench/stereovision3.blif Normal file
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@ -0,0 +1,881 @@
# Benchmark "sv_chip3_hierarchy_no_mem" written by ABC on Tue Apr 9 16:48:04 2013
.model sv_chip3_hierarchy_no_mem
.inputs top^tm3_clk_v0 top^tm3_clk_v2 top^tm3_vidin_llc top^tm3_vidin_vs \
top^tm3_vidin_href top^tm3_vidin_cref top^tm3_vidin_rts0 \
top^tm3_vidin_vpo~0 top^tm3_vidin_vpo~1 top^tm3_vidin_vpo~2 \
top^tm3_vidin_vpo~3 top^tm3_vidin_vpo~4 top^tm3_vidin_vpo~5 \
top^tm3_vidin_vpo~6 top^tm3_vidin_vpo~7 top^tm3_vidin_vpo~8 \
top^tm3_vidin_vpo~9 top^tm3_vidin_vpo~10 top^tm3_vidin_vpo~11 \
top^tm3_vidin_vpo~12 top^tm3_vidin_vpo~13 top^tm3_vidin_vpo~14 \
top^tm3_vidin_vpo~15
.outputs top^tm3_vidin_sda top^tm3_vidin_scl top^vidin_new_data \
top^vidin_rgb_reg~0 top^vidin_rgb_reg~1 top^vidin_rgb_reg~2 \
top^vidin_rgb_reg~3 top^vidin_rgb_reg~4 top^vidin_rgb_reg~5 \
top^vidin_rgb_reg~6 top^vidin_rgb_reg~7 top^vidin_addr_reg~0 \
top^vidin_addr_reg~1 top^vidin_addr_reg~2 top^vidin_addr_reg~3 \
top^vidin_addr_reg~4 top^vidin_addr_reg~5 top^vidin_addr_reg~6 \
top^vidin_addr_reg~7 top^vidin_addr_reg~8 top^vidin_addr_reg~9 \
top^vidin_addr_reg~10 top^vidin_addr_reg~11 top^vidin_addr_reg~12 \
top^vidin_addr_reg~13 top^vidin_addr_reg~14 top^vidin_addr_reg~15 \
top^vidin_addr_reg~16 top^vidin_addr_reg~17 top^vidin_addr_reg~18
.latch n107 top^FF_NODE~20 re top^tm3_clk_v0 0
.latch n112 top^FF_NODE~30 re top^tm3_clk_v0 0
.latch n117 top^FF_NODE~41 re top^tm3_clk_v0 0
.latch n122 top^FF_NODE~135 re top^tm3_clk_v0 0
.latch n127 top^FF_NODE~31 re top^tm3_clk_v0 0
.latch n132 top^FF_NODE~42 re top^tm3_clk_v0 0
.latch n137 top^FF_NODE~119 re top^tm3_clk_v0 0
.latch n142 top^FF_NODE~32 re top^tm3_clk_v0 0
.latch n147 top^FF_NODE~43 re top^tm3_clk_v0 0
.latch n152 top^FF_NODE~120 re top^tm3_clk_v0 0
.latch n157 top^FF_NODE~33 re top^tm3_clk_v0 0
.latch n162 top^FF_NODE~44 re top^tm3_clk_v0 0
.latch n167 top^FF_NODE~121 re top^tm3_clk_v0 0
.latch n172 top^FF_NODE~34 re top^tm3_clk_v0 0
.latch n177 top^FF_NODE~45 re top^tm3_clk_v0 0
.latch n182 top^FF_NODE~122 re top^tm3_clk_v0 0
.latch n187 top^FF_NODE~35 re top^tm3_clk_v0 0
.latch n192 top^FF_NODE~46 re top^tm3_clk_v0 0
.latch n197 top^FF_NODE~123 re top^tm3_clk_v0 0
.latch n202 top^FF_NODE~36 re top^tm3_clk_v0 0
.latch n207 top^FF_NODE~47 re top^tm3_clk_v0 0
.latch n212 top^FF_NODE~124 re top^tm3_clk_v0 0
.latch n217 top^FF_NODE~37 re top^tm3_clk_v0 0
.latch n222 top^FF_NODE~48 re top^tm3_clk_v0 0
.latch n227 top^FF_NODE~125 re top^tm3_clk_v0 0
.latch n232 top^FF_NODE~38 re top^tm3_clk_v0 0
.latch n237 top^FF_NODE~117 re top^tm3_clk_v0 0
.latch n242 top^FF_NODE~118 re top^tm3_clk_v0 0
.latch n247 top^FF_NODE~126 re top^tm3_clk_v0 0
.latch n252 top^FF_NODE~127 re top^tm3_clk_v0 0
.latch n257 top^FF_NODE~128 re top^tm3_clk_v0 0
.latch n262 top^FF_NODE~129 re top^tm3_clk_v0 0
.latch n267 top^FF_NODE~130 re top^tm3_clk_v0 0
.latch n272 top^FF_NODE~131 re top^tm3_clk_v0 0
.latch n277 top^FF_NODE~132 re top^tm3_clk_v0 0
.latch n282 top^FF_NODE~133 re top^tm3_clk_v0 0
.latch n287 top^FF_NODE~134 re top^tm3_clk_v0 0
.latch n292 top^FF_NODE~136 re top^tm3_clk_v0 0
.latch n297 top^FF_NODE~137 re top^tm3_clk_v0 0
.latch n302 top^FF_NODE~138 re top^tm3_clk_v0 0
.latch n307 top^FF_NODE~139 re top^tm3_clk_v0 0
.latch n312 top^FF_NODE~140 re top^tm3_clk_v0 0
.latch n317 top^FF_NODE~141 re top^tm3_clk_v0 0
.latch n322 top^FF_NODE~142 re top^tm3_clk_v0 0
.latch n327 top^FF_NODE~143 re top^tm3_clk_v0 0
.latch n332 top^FF_NODE~144 re top^tm3_clk_v0 0
.latch n337 top^FF_NODE~21 re top^tm3_clk_v0 0
.latch n342 top^FF_NODE~39 re top^tm3_clk_v0 0
.latch n347 top^FF_NODE~22 re top^tm3_clk_v0 0
.latch n352 top^FF_NODE~49 re top^tm3_clk_v0 0
.latch n357 top^FF_NODE~23 re top^tm3_clk_v0 0
.latch n362 top^FF_NODE~50 re top^tm3_clk_v0 0
.latch n367 top^FF_NODE~24 re top^tm3_clk_v0 0
.latch n372 top^FF_NODE~51 re top^tm3_clk_v0 0
.latch n377 top^FF_NODE~25 re top^tm3_clk_v0 0
.latch n382 top^FF_NODE~52 re top^tm3_clk_v0 0
.latch n387 top^FF_NODE~26 re top^tm3_clk_v0 0
.latch n392 top^FF_NODE~53 re top^tm3_clk_v0 0
.latch n397 top^FF_NODE~27 re top^tm3_clk_v0 0
.latch n402 top^FF_NODE~54 re top^tm3_clk_v0 0
.latch n407 top^FF_NODE~28 re top^tm3_clk_v0 0
.latch n412 top^FF_NODE~55 re top^tm3_clk_v0 0
.latch n417 top^FF_NODE~29 re top^tm3_clk_v0 0
.latch n422 top^FF_NODE~56 re top^tm3_clk_v0 0
.latch n427 top^FF_NODE~228 re top^tm3_clk_v2 0
.latch n432 top^FF_NODE~381 re top^tm3_clk_v2 0
.latch n437 top^FF_NODE~386 re top^tm3_clk_v2 0
.latch n442 top^FF_NODE~229 re top^tm3_clk_v2 0
.latch n447 top^FF_NODE~230 re top^tm3_clk_v2 0
.latch n452 top^FF_NODE~387 re top^tm3_clk_v2 0
.latch n457 top^FF_NODE~388 re top^tm3_clk_v2 0
.latch n462 top^FF_NODE~389 re top^tm3_clk_v2 0
.latch n467 top^FF_NODE~390 re top^tm3_clk_v2 0
.latch n472 top^FF_NODE~391 re top^tm3_clk_v2 0
.latch n477 top^FF_NODE~392 re top^tm3_clk_v2 0
.latch n482 top^FF_NODE~382 re top^tm3_clk_v2 0
.latch n487 top^FF_NODE~383 re top^tm3_clk_v2 0
.latch n492 top^FF_NODE~384 re top^tm3_clk_v2 0
.latch n497 top^FF_NODE~385 re top^tm3_clk_v2 0
.latch n502 top^FF_NODE~378 re top^tm3_clk_v2 0
.latch n507 top^FF_NODE~40 re top^tm3_clk_v0 0
.latch n512 top^FF_NODE~57 re top^tm3_clk_v0 0
.latch n517 top^FF_NODE~81 re top^tm3_clk_v0 0
.latch n522 top^FF_NODE~58 re top^tm3_clk_v0 0
.latch n527 top^FF_NODE~82 re top^tm3_clk_v0 0
.latch n632 top^FF_NODE~69 re top^tm3_clk_v0 0
.latch n637 top^FF_NODE~93 re top^tm3_clk_v0 0
.latch n682 top^FF_NODE~74 re top^tm3_clk_v0 0
.latch n687 top^FF_NODE~98 re top^tm3_clk_v0 0
.latch n692 top^FF_NODE~75 re top^tm3_clk_v0 0
.latch n697 top^FF_NODE~99 re top^tm3_clk_v0 0
.latch n702 top^FF_NODE~76 re top^tm3_clk_v0 0
.latch n707 top^FF_NODE~100 re top^tm3_clk_v0 0
.latch n712 top^FF_NODE~77 re top^tm3_clk_v0 0
.latch n717 top^FF_NODE~101 re top^tm3_clk_v0 0
.latch n722 top^FF_NODE~78 re top^tm3_clk_v0 0
.latch n727 top^FF_NODE~102 re top^tm3_clk_v0 0
.latch n751 top^FF_NODE~114 re top^tm3_clk_v0 0
.latch n755 top^FF_NODE~115 re top^tm3_clk_v0 0
.latch n759 top^FF_NODE~116 re top^tm3_clk_v0 0
.latch n763 top^FF_NODE~379 re top^tm3_clk_v2 0
.latch n767 top^FF_NODE~380 re top^tm3_clk_v2 0
.names top^tm3_vidin_href top^tm3_vidin_cref top^FF_NODE~20 n107
100 1
111 1
.names top^tm3_vidin_vs top^FF_NODE~30 n458 n112
001 1
010 1
.names top^tm3_vidin_href top^FF_NODE~20 top^FF_NODE~22 top^FF_NODE~28 \
top^FF_NODE~29 n459 n458
1----- 0
-00001 0
.names top^FF_NODE~21 top^FF_NODE~23 top^FF_NODE~24 top^FF_NODE~25 \
top^FF_NODE~26 top^FF_NODE~27 n459
000000 1
.names top^tm3_vidin_cref top^FF_NODE~30 top^FF_NODE~41 n117
01- 1
1-1 1
.names top^FF_NODE~38 top^FF_NODE~40 top^FF_NODE~115 top^FF_NODE~116 n292
0001 1
.names top^tm3_vidin_vs top^FF_NODE~31 top^FF_NODE~30 n458 n127
0011 1
010- 1
01-0 1
.names top^tm3_vidin_cref top^FF_NODE~31 top^FF_NODE~42 n132
01- 1
1-1 1
.names top^tm3_vidin_vs top^FF_NODE~31 top^FF_NODE~32 top^FF_NODE~30 n458 \
n142
001-- 1
01011 1
0-10- 1
0-1-0 1
.names top^tm3_vidin_cref top^FF_NODE~32 top^FF_NODE~43 n147
01- 1
1-1 1
.names top^tm3_vidin_vs top^FF_NODE~33 top^FF_NODE~30 n458 top^FF_NODE~31 \
top^FF_NODE~32 n157
001111 1
010--- 1
01-0-- 1
01--0- 1
01---0 1
.names top^tm3_vidin_cref top^FF_NODE~33 top^FF_NODE~44 n162
01- 1
1-1 1
.names top^tm3_vidin_vs top^FF_NODE~33 top^FF_NODE~34 n473 top^FF_NODE~30 \
n458 n172
001--- 1
010111 1
0-10-- 1
0-1-0- 1
0-1--0 1
.names top^FF_NODE~31 top^FF_NODE~32 n473
11 1
.names top^tm3_vidin_cref top^FF_NODE~34 top^FF_NODE~45 n177
01- 1
1-1 1
.names top^tm3_vidin_vs top^FF_NODE~33 top^FF_NODE~34 top^FF_NODE~35 n477_1 \
n473 n187
00-1-- 1
011011 1
0-01-- 1
0--10- 1
0--1-0 1
.names top^FF_NODE~30 n458 n477_1
11 1
.names top^tm3_vidin_cref top^FF_NODE~35 top^FF_NODE~46 n192
01- 1
1-1 1
.names top^tm3_vidin_vs top^FF_NODE~36 n481 n202
001 1
010 1
.names top^FF_NODE~33 top^FF_NODE~34 top^FF_NODE~35 n473 top^FF_NODE~30 \
n458 n481
111111 1
.names top^tm3_vidin_cref top^FF_NODE~36 top^FF_NODE~47 n207
01- 1
1-1 1
.names top^tm3_vidin_vs top^FF_NODE~36 top^FF_NODE~37 n481 n217
001- 1
0101 1
0-10 1
.names top^tm3_vidin_cref top^FF_NODE~37 top^FF_NODE~48 n222
01- 1
1-1 1
.names top^FF_NODE~126 n292 n247
10 1
.names top^FF_NODE~127 n292 n252
10 1
.names top^tm3_vidin_href top^FF_NODE~21 top^tm3_vidin_cref top^FF_NODE~20 \
n337
1001 1
111- 1
11-0 1
.names top^tm3_vidin_cref top^FF_NODE~21 top^FF_NODE~39 n342
01- 1
1-1 1
.names top^tm3_vidin_href top^FF_NODE~21 top^FF_NODE~22 top^tm3_vidin_cref \
top^FF_NODE~20 n347
101-- 1
11001 1
1-11- 1
1-1-0 1
.names top^tm3_vidin_href top^FF_NODE~21 top^FF_NODE~22 top^FF_NODE~23 \
top^tm3_vidin_cref top^FF_NODE~20 n357
10-1-- 1
111001 1
1-01-- 1
1--11- 1
1--1-0 1
.names top^tm3_vidin_href top^FF_NODE~21 top^FF_NODE~22 top^FF_NODE~23 \
top^FF_NODE~24 n514 n367
10--1- 1
111101 1
1-0-1- 1
1--01- 1
1---10 1
.names top^tm3_vidin_cref top^FF_NODE~20 n514
01 1
.names top^tm3_vidin_cref top^FF_NODE~24 top^FF_NODE~51 n372
01- 1
1-1 1
.names top^tm3_vidin_href top^FF_NODE~25 n517_1 n377
101 1
110 1
.names top^tm3_vidin_cref top^FF_NODE~20 top^FF_NODE~21 top^FF_NODE~22 \
top^FF_NODE~23 top^FF_NODE~24 n517_1
011111 1
.names top^tm3_vidin_cref top^FF_NODE~25 top^FF_NODE~52 n382
01- 1
1-1 1
.names top^tm3_vidin_href top^FF_NODE~25 top^FF_NODE~26 n517_1 n387
101- 1
1101 1
1-10 1
.names top^tm3_vidin_cref top^FF_NODE~26 top^FF_NODE~53 n392
01- 1
1-1 1
.names top^tm3_vidin_href top^FF_NODE~27 n522_1 n397
101 1
110 1
.names top^FF_NODE~25 top^FF_NODE~26 n517_1 n522_1
111 1
.names top^tm3_vidin_cref top^FF_NODE~27 top^FF_NODE~54 n402
01- 1
1-1 1
.names top^tm3_vidin_href top^FF_NODE~27 top^FF_NODE~28 n522_1 n407
101- 1
1101 1
1-10 1
.names top^tm3_vidin_cref top^FF_NODE~28 top^FF_NODE~55 n412
01- 1
1-1 1
.names top^tm3_vidin_href top^FF_NODE~27 top^FF_NODE~28 top^FF_NODE~29 \
n522_1 n417
10-1- 1
11101 1
1-01- 1
1--10 1
.names top^tm3_vidin_cref top^FF_NODE~29 top^FF_NODE~56 n422
01- 1
1-1 1
.names n529 n531 n533 n539 n543 n546 n528
1----- 0
-01111 0
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n530 n529
100011 1
.names top^FF_NODE~391 top^FF_NODE~392 n530
01 1
.names top^FF_NODE~392 n532 n531
00 1
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 top^FF_NODE~391 n532
00010- 0
10-010 0
11100- 0
1111-0 0
11-100 0
1-0010 0
-00010 0
--1100 0
.names top^FF_NODE~391 top^FF_NODE~392 n534 n535 n536 n538 n533
1---1- 1
-1--10 1
--1110 1
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n534
-0-11 0
-1101 0
--011 0
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n535
01001 0
01111 0
10010 0
10100 0
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n537 n536
001011 0
11-111 0
1-1111 0
-11111 0
.names top^FF_NODE~391 top^FF_NODE~392 n537
10 1
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n538
0-000 1
-0000 1
.names top^FF_NODE~390 top^FF_NODE~391 top^FF_NODE~392 n540 n541 n542 n539
0101-- 0
-00--0 0
-10-0- 0
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 n540
0110 1
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n541
1-010 0
-1010 0
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n542
01010 0
0-100 0
11000 0
.names top^FF_NODE~391 top^FF_NODE~392 n538 n544 n545 n543
01--0 0
101-- 0
10-0- 0
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n544
11000 0
-0100 0
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n545
011-0 0
101-0 0
11-10 0
--110 0
.names top^FF_NODE~391 top^FF_NODE~392 n547 n548 n549 n550 n546
00---- 1
11---- 1
-011-- 1
-1--11 1
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n547
0-110 0
-0110 0
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n548
00-11 0
0-0-1 0
11110 0
1--01 0
-00-1 0
-1-01 0
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n549
11100 0
-0010 0
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n550
00100 0
01010 0
11000 0
-0001 0
.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \
top^FF_NODE~385 n552
00000 1
11-11 1
--111 1
.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \
top^FF_NODE~385 n553
11011 1
.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \
top^FF_NODE~385 n555
0---- 1
-1-11 1
--111 1
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n537 n557
000011 1
001001 1
010101 1
100001 1
101101 1
110011 1
111001 1
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n537 n558
001111 1
011011 1
100111 1
.names top^FF_NODE~389 top^FF_NODE~390 top^FF_NODE~391 top^FF_NODE~392 n560 \
n561 n559
10001- 0
1110-1 0
-000-1 0
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 n560
001 1
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 n561
111 1
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n530 n562
000011 1
000101 1
010001 1
011101 1
101001 1
110101 1
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n564 n563
000111 1
00-001 1
010-01 1
011-11 1
01-011 1
110111 1
-00001 1
.names top^FF_NODE~391 top^FF_NODE~392 n564
00 1
.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \
top^FF_NODE~385 n547 n566
000100 1
00-010 1
010110 1
011-00 1
01-000 1
0-1000 1
.names n568 n544 n569 n570 n571 n573 n567
01-00- 1
0-100- 1
-1-001 1
--1001 1
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n568
0-011 1
-0011 1
.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \
top^FF_NODE~385 n569
01101 0
0-011 0
.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \
top^FF_NODE~385 n541 n570
000100 1
001010 1
010010 1
011000 1
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n572 n571
000100 1
-11000 1
.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \
top^FF_NODE~385 n572
00-01 0
01-10 0
0-001 0
0-110 0
.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \
top^FF_NODE~385 n573
00010 0
01-00 0
0-001 0
.names n575 n582 n586 n589 n591 n595 n574
000011 1
.names n576 top^FF_NODE~391 top^FF_NODE~392 n575
001 1
.names n549 n577 n578 n579 n580 n581 n576
0--0-- 0
-10--- 0
----00 0
.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~385 n577
0001 1
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n578
0-100 0
-0100 0
.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \
top^FF_NODE~385 n579
00001 0
0-100 0
.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \
top^FF_NODE~385 n580
01100 0
0-011 0
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n581
-1000 0
.names n583 n580 n584 n585 top^FF_NODE~391 top^FF_NODE~392 n582
10--01 1
--0001 1
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n583
10000 1
.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \
top^FF_NODE~385 n584
001-0 0
00-01 0
01011 0
0-100 0
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n585
00110 0
-1010 0
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 n587 n537 n588 n586
101110 1
.names top^FF_NODE~389 top^FF_NODE~390 n587
11 1
.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \
top^FF_NODE~385 n588
00010 0
0-100 0
.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \
top^FF_NODE~385 n590 n589
01--01 1
0-0101 1
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n537 n590
1-1011 1
-11011 1
.names n588 n592 n593 n594 top^FF_NODE~391 top^FF_NODE~392 n591
00--10 0
--0010 0
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n592
00111 0
11011 0
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n593
11110 0
-0001 0
.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \
top^FF_NODE~385 n594
000-1 0
001-0 0
00-10 0
.names n596 n597 n598 n599 n600 n601 n595
0--001 1
-0-001 1
--000- 1
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 n596
0111 1
.names top^FF_NODE~390 top^FF_NODE~391 top^FF_NODE~392 n597
110 1
.names top^FF_NODE~384 n577 n598
11 1
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n564 n599
000101 1
100001 1
-11001 1
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \
top^FF_NODE~390 n564 n600
000011 1
-11101 1
.names top^FF_NODE~389 top^FF_NODE~390 top^FF_NODE~391 top^FF_NODE~392 n561 \
n602 n601
0001-1 0
11101- 0
.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 n602
000 1
.names top^FF_NODE~378 top^FF_NODE~379 top^FF_NODE~380 n610 n482
11-0 1
1-00 1
.names top^FF_NODE~228 top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 \
top^FF_NODE~384 top^FF_NODE~385 n610
011-0- 1
011--0 1
1-0--- 1
-00--- 1
---111 1
.names top^FF_NODE~378 top^FF_NODE~379 top^FF_NODE~380 n612 n487
11-0 1
1-00 1
.names top^FF_NODE~228 top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 \
top^FF_NODE~384 top^FF_NODE~385 n612
0111-- 1
1--0-- 1
-0-0-- 1
--00-- 1
----11 1
.names top^FF_NODE~378 top^FF_NODE~379 top^FF_NODE~380 n614 n492
11-0 1
1-00 1
.names top^FF_NODE~228 top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 \
top^FF_NODE~384 top^FF_NODE~385 n614
01110- 0
1---10 0
-0--10 0
--0-10 0
---01- 0
.names top^FF_NODE~378 top^FF_NODE~379 top^FF_NODE~380 n616 n497
11-0 1
1-00 1
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top^FF_NODE~384 top^FF_NODE~385 n616
011110 0
---0-1 0
----01 0
.names top^tm3_vidin_cref top^tm3_vidin_rts0 top^FF_NODE~40 n507
01- 1
1-1 1
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0-1 1
11- 1
.names top^tm3_vidin_cref top^FF_NODE~57 top^FF_NODE~81 n517
0-1 1
11- 1
.names top^tm3_vidin_cref top^tm3_vidin_vpo~1 top^FF_NODE~58 n522
0-1 1
11- 1
.names top^tm3_vidin_cref top^FF_NODE~58 top^FF_NODE~82 n527
0-1 1
11- 1
.names top^tm3_vidin_cref top^tm3_vidin_vpo~2 top^FF_NODE~69 n632
0-1 1
11- 1
.names top^tm3_vidin_cref top^FF_NODE~69 top^FF_NODE~93 n637
0-1 1
11- 1
.names top^FF_NODE~230 top^tm3_vidin_sda
1 1
.names top^FF_NODE~229 top^tm3_vidin_scl
1 1
.names top^FF_NODE~136 top^vidin_new_data
1 1
.names top^FF_NODE~137 top^vidin_rgb_reg~0
1 1
.names top^FF_NODE~138 top^vidin_rgb_reg~1
1 1
.names top^FF_NODE~139 top^vidin_rgb_reg~2
1 1
.names top^FF_NODE~140 top^vidin_rgb_reg~3
1 1
.names top^FF_NODE~141 top^vidin_rgb_reg~4
1 1
.names top^FF_NODE~142 top^vidin_rgb_reg~5
1 1
.names top^FF_NODE~143 top^vidin_rgb_reg~6
1 1
.names top^FF_NODE~144 top^vidin_rgb_reg~7
1 1
.names top^FF_NODE~117 top^vidin_addr_reg~0
1 1
.names top^FF_NODE~118 top^vidin_addr_reg~1
1 1
.names top^FF_NODE~128 top^vidin_addr_reg~2
1 1
.names top^FF_NODE~129 top^vidin_addr_reg~3
1 1
.names top^FF_NODE~130 top^vidin_addr_reg~4
1 1
.names top^FF_NODE~131 top^vidin_addr_reg~5
1 1
.names top^FF_NODE~132 top^vidin_addr_reg~6
1 1
.names top^FF_NODE~133 top^vidin_addr_reg~7
1 1
.names top^FF_NODE~134 top^vidin_addr_reg~8
1 1
.names top^FF_NODE~135 top^vidin_addr_reg~9
1 1
.names top^FF_NODE~119 top^vidin_addr_reg~10
1 1
.names top^FF_NODE~120 top^vidin_addr_reg~11
1 1
.names top^FF_NODE~121 top^vidin_addr_reg~12
1 1
.names top^FF_NODE~122 top^vidin_addr_reg~13
1 1
.names top^FF_NODE~123 top^vidin_addr_reg~14
1 1
.names top^FF_NODE~124 top^vidin_addr_reg~15
1 1
.names top^FF_NODE~125 top^vidin_addr_reg~16
1 1
.names top^FF_NODE~126 top^vidin_addr_reg~17
1 1
.names top^FF_NODE~127 top^vidin_addr_reg~18
1 1
.names top^FF_NODE~41 top^FF_NODE~135 n292 n122
1-1 1
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1-1 1
-10 1
.names top^FF_NODE~43 top^FF_NODE~120 n292 n152
1-1 1
-10 1
.names top^FF_NODE~44 top^FF_NODE~121 n292 n167
1-1 1
-10 1
.names top^FF_NODE~45 top^FF_NODE~122 n292 n182
1-1 1
-10 1
.names top^FF_NODE~46 top^FF_NODE~123 n292 n197
1-1 1
-10 1
.names top^FF_NODE~47 top^FF_NODE~124 n292 n212
1-1 1
-10 1
.names top^FF_NODE~48 top^FF_NODE~125 n292 n227
1-1 1
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.names top^tm3_vidin_cref top^FF_NODE~20 top^FF_NODE~38 n232
01- 1
1-1 1
.names top^FF_NODE~117 top^FF_NODE~39 n292 n237
1-0 1
-11 1
.names top^FF_NODE~118 top^FF_NODE~49 n292 n242
1-0 1
-11 1
.names top^FF_NODE~128 top^FF_NODE~50 n292 n257
1-0 1
-11 1
.names top^FF_NODE~129 top^FF_NODE~51 n292 n262
1-0 1
-11 1
.names top^FF_NODE~130 top^FF_NODE~52 n292 n267
1-0 1
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.names top^FF_NODE~131 top^FF_NODE~53 n292 n272
1-0 1
-11 1
.names top^FF_NODE~132 top^FF_NODE~54 n292 n277
1-0 1
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.names top^FF_NODE~133 top^FF_NODE~55 n292 n282
1-0 1
-11 1
.names top^FF_NODE~134 top^FF_NODE~56 n292 n287
1-0 1
-11 1
.names top^FF_NODE~137 top^FF_NODE~81 n292 n297
1-0 1
-11 1
.names top^FF_NODE~138 top^FF_NODE~82 n292 n302
1-0 1
-11 1
.names top^FF_NODE~139 top^FF_NODE~93 n292 n307
1-0 1
-11 1
.names top^FF_NODE~140 top^FF_NODE~98 n292 n312
1-0 1
-11 1
.names top^FF_NODE~141 top^FF_NODE~99 n292 n317
1-0 1
-11 1
.names top^FF_NODE~142 top^FF_NODE~100 n292 n322
1-0 1
-11 1
.names top^FF_NODE~143 top^FF_NODE~101 n292 n327
1-0 1
-11 1
.names top^FF_NODE~144 top^FF_NODE~102 n292 n332
1-0 1
-11 1
.names top^tm3_vidin_cref top^FF_NODE~22 top^FF_NODE~49 n352
01- 1
1-1 1
.names top^tm3_vidin_cref top^FF_NODE~23 top^FF_NODE~50 n362
01- 1
1-1 1
.names n529 n531 n533 n539 n543 n546 n427
1----- 1
-01111 1
.names top^FF_NODE~228 top^FF_NODE~378 top^FF_NODE~379 top^FF_NODE~380 n552 \
n553 n432
1---0- 1
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--01-- 1
-----1 1
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01- 0
101 0
.names n528 n557 n558 n559 n562 n563 n442
100100 0
.names n528 n566 n567 n574 top^FF_NODE~391 top^FF_NODE~392 n447
1011-- 0
1--10- 0
1--1-1 0
.names top^FF_NODE~228 top^FF_NODE~386 top^FF_NODE~387 n555 n452
001- 1
010- 1
1-11 1
.names top^FF_NODE~228 top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 n555 \
n457
00-1- 1
0110- 1
0-01- 1
1--11 1
.names top^FF_NODE~228 top^FF_NODE~389 n561 n555 n462
001- 1
010- 1
11-1 1
.names top^FF_NODE~228 top^FF_NODE~389 top^FF_NODE~390 n561 n555 n467
001-- 1
0101- 1
0-10- 1
1-1-1 1
.names top^FF_NODE~228 top^FF_NODE~391 n561 n555 top^FF_NODE~389 \
top^FF_NODE~390 n472
001-11 1
010--- 1
01--0- 1
01---0 1
11-1-- 1
.names top^FF_NODE~228 top^FF_NODE~391 top^FF_NODE~392 n561 n587 n555 n477
001--- 1
01011- 1
0-10-- 1
0-1-0- 1
1-1--1 1
.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \
top^FF_NODE~385 top^FF_NODE~378 n502
10000- 1
-----1 1
.names top^tm3_vidin_cref top^tm3_vidin_vpo~0 top^FF_NODE~74 n682
01- 1
1-1 1
.names top^tm3_vidin_cref top^FF_NODE~74 top^FF_NODE~98 n687
0-1 1
11- 1
.names top^tm3_vidin_cref top^tm3_vidin_vpo~1 top^FF_NODE~75 n692
01- 1
1-1 1
.names top^tm3_vidin_cref top^FF_NODE~75 top^FF_NODE~99 n697
0-1 1
11- 1
.names top^tm3_vidin_cref top^tm3_vidin_vpo~2 top^FF_NODE~76 n702
01- 1
1-1 1
.names top^tm3_vidin_cref top^FF_NODE~76 top^FF_NODE~100 n707
0-1 1
11- 1
.names top^tm3_vidin_cref top^tm3_vidin_vpo~3 top^FF_NODE~77 n712
01- 1
1-1 1
.names top^tm3_vidin_cref top^FF_NODE~77 top^FF_NODE~101 n717
0-1 1
11- 1
.names top^tm3_vidin_cref top^tm3_vidin_vpo~4 top^FF_NODE~78 n722
01- 1
1-1 1
.names top^tm3_vidin_cref top^FF_NODE~78 top^FF_NODE~102 n727
0-1 1
11- 1
.names top^tm3_vidin_cref n751
1 1
.names top^FF_NODE~114 n755
1 1
.names top^FF_NODE~115 n759
1 1
.names top^tm3_vidin_rts0 n763
1 1
.names top^FF_NODE~379 n767
1 1
.end

413
fpga_flow/benchmarks/FPGA_SPICE_bench/tbk.blif Normal file
View File

@ -0,0 +1,413 @@
.model tbk.kiss2
.inputs v0 v1 v2 v3 v4 v5
.outputs v11.5 v11.6 v11.7
.latch v11.0 v6 0
.latch v11.1 v7 0
.latch v11.2 v8 0
.latch v11.3 v9 0
.latch v11.4 v10 0
.names [186] v11.5
0 1
.names [188] v11.6
0 1
.names [190] v11.7
0 1
.names [176] v11.0
0 1
.names [178] v11.1
0 1
.names [180] v11.2
0 1
.names [182] v11.3
0 1
.names [184] v11.4
0 1
.names v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [0]
11001110001 1
.names v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [1]
11001100010 1
.names v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [2]
01001110001 1
.names v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [3]
10000001100 1
.names v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [4]
01001001000 1
.names v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [5]
00100101001 1
.names v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [6]
00011010100 1
.names v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [7]
0101110000 1
.names v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [8]
01001000100 1
.names v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [9]
01001010010 1
.names v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [10]
00010001000 1
.names v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [11]
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.names v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [12]
00100100000 1
.names v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [13]
10001000001 1
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1001110010 1
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00101000101 1
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.names v0 v1 v2 v4 v5 v7 v8 v9 v10 [35]
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.names v0 v1 v2 v3 v5 v6 v7 v8 v9 v10 [36]
0100100000 1
.names v0 v1 v2 v3 v4 v6 v7 v8 v9 v10 [37]
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.names v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [41]
10000011001 1
.names v0 v1 v2 v3 v5 v6 v7 v8 v9 v10 [42]
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.names v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [43]
01000001000 1
.names v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [44]
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.names v0 v1 v2 v3 v4 v6 v7 v8 v9 v10 [45]
0001000000 1
.names v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [46]
10000101000 1
.names v0 v1 v2 v3 v5 v6 v7 v8 v9 v10 [47]
0001000000 1
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10000111100 1
.names v0 v1 v2 v4 v5 v6 v8 v9 v10 [50]
110110000 1
.names v0 v1 v2 v4 v5 v6 v7 v8 v10 [51]
101110100 1
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001110000 1
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0001010000 1
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.names v0 v1 v2 v3 v4 v5 v6 v8 v9 v10 [58]
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fpga_flow/benchmarks/FPGA_SPICE_bench/traffic.blif Normal file
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.model tlc.sim
.inputs in1
.inputs in2
.inputs in3
.outputs out11
.outputs out12
.outputs out13
.outputs out14
.outputs out15
.latch out1 in4 0
.latch out2 in5 0
.latch out3 in6 0
.latch out4 in7 0
.latch out5 in8 0
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.latch out10 in13 0
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11111 1
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11111 1
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111 1
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1111 1
.names in1* in4* in5 in7* g_1and7
1111 1
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.names g_2and28 g_2and29 out11
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.names g_2and4 g_2and11 g_2and12 g_2and13 g_2and19 g_2and22 g_2and23 g_2and24 g_2and30 g_2and32 out12
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.names g_2and2 g_2and15 g_2and16 g_2and17 g_2and20 g_2and26 g_2and33 out13
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.names g_2and1 g_2and5 g_2and6 g_2and7 g_2and14 g_2and21 g_2and25 g_2and31 out14
00000000 0
.names g_2and3 g_2and8 g_2and9 g_2and10 g_2and11 g_2and12 g_2and13 g_2and18 g_2and19 g_2and27 out15
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.end

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.model s298.bench
.inputs G0 G1 G2
.outputs G117 G132 G66 G118 G133 G67
.wire_load_slope 0.00
.latch G29 G10 0
.latch G30 G11 0
.latch G34 G12 0
.latch G39 G13 0
.latch G44 G14 0
.latch G56 G15 0
.latch G86 G16 0
.latch G92 G17 0
.latch G98 G18 0
.latch G102 G19 0
.latch G107 G20 0
.latch G113 G21 0
.latch G119 G22 0
.latch G125 G23 0
.names II210 G117
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.names II155 G66
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.names II213 G118
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.names II238 G133
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.names II158 G67
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.names G10 G130 G29
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.names G31 G32 G33 G130 G30
0000 1
.names G35 G36 G37 G130 G34
0000 1
.names G42 G43 G39
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.names G48 G49 G53 G44
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.names G57 G58 G130 G56
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.names G88 G89 G90 G112 G86
0000 1
.names G94 G95 G97 G92
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.names G51 G28 G27
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.names G38 G46 G33
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.names G10 G11 G12 G35
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.names G38 G45 G36
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.names G46 G45 G37
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.names G12 G11 G10 G41
0-- 1
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1111 1
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0--- 1
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.names G64 G65 G63
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.names G71 G72 G73 G14 G109
0--- 1
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--0- 1
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.names G108 G109 G110
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.names G103 G18 G69
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.end

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# Circuit Names, fixed routint channel width,
s298.blif, 60
elliptic.blif, 60
simple_spi.blif, 60
i2c.blif, 60
pci_conf_cyc_addr_dec.blif, 60
sasc.blif, 60
usb_phy.blif, 60
steppermotordrive.blif, 60
stereovision3.blif, 60
dalu.blif, 60
C1355.blif, 60
alu4.blif, 60
priority.blif, 60
apex7.blif, 60
int2float.blif, 60
planet.blif, 60
alu2.blif, 60
mult32a.blif, 60
tbk.blif, 60
sqrt8ml.blif, 60
ss_pcm.blif, 60
scf.blif, 60
s820.blif, 60
ctrl.blif, 60
cavlc.blif, 60
router.blif, 60
traffic.blif, 60
e64.blif, 60
s1488.blif, 60
fsm8_8_13.blif, 60

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# Circuit Names, fixed routint channel width,
#alu4.blif, 120
#apex2.blif, 120
#apex4.blif, 120
#bigkey.blif, 120
#clma.blif, 120
#des.blif, 120
#diffeq.blif, 120
#dsip.blif, 120
#elliptic.blif, 120
#ex1010.blif, 120
#ex5p.blif, 120
#frisc.blif, 120
#mcnc_big20.txt
#misex3.blif, 120
#pdc.blif, 120
s298.blif, 30
#s38417.blif, 120
#s38584.1.blif, 120
#seq.blif, 120
#spla.blif, 120
#tseng.blif, 120

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# Standard Configuration Example
[dir_path]
#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_verilog
#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_blif
#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/MCNC_big20
benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/FPGA_SPICE_bench
odin2_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ODIN_II/odin_II.exe
cirkit_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_majccmap/abc
abc_path = /research/ece/lnis/USERS/tang/research/ABC/abc70930/abc
abc_mccl_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_vtrccmap/abc
abc_with_bb_support_path = /research/ece/lnis/USERS/tang/research/vtr7_release/abc_with_bb_support/abc
mpack1_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v1.5b/mpack
m2net_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/scripts/m2net.pl
mpack2_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v2/mpack2
#vpr_path = /research/ece/lnis/USERS/tang/research/vtr7_release/vpr/vpr
vpr_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/vpr
rpt_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/results
ace_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ace2/ace
[flow_conf]
flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr
#flow_type = vtr #standard|mpack2|mpack1|vtr_standard|vtr
vpr_arch = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_FF.xml # Use relative path under VPR folder is OK
mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
m2net_conf = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
mpack2_arch = K6_pattern7_I24.arch
power_tech_xml = /research/ece/lnis/USERS/tang/research/vtr7_release/vtr_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
[csv_tags]
mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:
mpack2_tags = BLE Number:|BLE Fill Rate:
vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took
vpr_power_tags = PB Types|Routing

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# Standard Configuration Example
[dir_path]
#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_verilog
#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_blif
#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/MCNC_big20
benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/FPGA_SPICE_bench
odin2_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ODIN_II/odin_II.exe
cirkit_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_majccmap/abc
abc_path = /research/ece/lnis/USERS/tang/research/ABC/abc70930/abc
abc_mccl_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_vtrccmap/abc
abc_with_bb_support_path = /research/ece/lnis/USERS/tang/research/vtr7_release/abc_with_bb_support/abc
mpack1_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v1.5b/mpack
m2net_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/scripts/m2net.pl
mpack2_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v2/mpack2
#vpr_path = /research/ece/lnis/USERS/tang/research/vtr7_release/vpr/vpr
vpr_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/vpr
rpt_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/results
ace_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ace2/ace
[flow_conf]
flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr
#flow_type = vtr #standard|mpack2|mpack1|vtr_standard|vtr
vpr_arch = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_MC.xml # Use relative path under VPR folder is OK
mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
m2net_conf = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
mpack2_arch = K6_pattern7_I24.arch
power_tech_xml = /research/ece/lnis/USERS/tang/research/vtr7_release/vtr_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
[csv_tags]
mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:
mpack2_tags = BLE Number:|BLE Fill Rate:
vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took
vpr_power_tags = PB Types|Routing

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# Standard Configuration Example
[dir_path]
#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_verilog
#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_blif
#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/MCNC_big20
benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/FPGA_SPICE_bench
odin2_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ODIN_II/odin_II.exe
cirkit_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_majccmap/abc
abc_path = /research/ece/lnis/USERS/tang/research/ABC/abc70930/abc
abc_mccl_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_vtrccmap/abc
abc_with_bb_support_path = /research/ece/lnis/USERS/tang/research/vtr7_release/abc_with_bb_support/abc
mpack1_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v1.5b/mpack
m2net_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/scripts/m2net.pl
mpack2_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v2/mpack2
#vpr_path = /research/ece/lnis/USERS/tang/research/vtr7_release/vpr/vpr
vpr_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/vpr
rpt_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/results
ace_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ace2/ace
[flow_conf]
flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr
#flow_type = vtr #standard|mpack2|mpack1|vtr_standard|vtr
vpr_arch = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_SS.xml # Use relative path under VPR folder is OK
mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
m2net_conf = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
mpack2_arch = K6_pattern7_I24.arch
power_tech_xml = /research/ece/lnis/USERS/tang/research/vtr7_release/vtr_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
[csv_tags]
mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:
mpack2_tags = BLE Number:|BLE Fill Rate:
vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took
vpr_power_tags = PB Types|Routing

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# Standard Configuration Example
[dir_path]
#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_verilog
#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_blif
#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/MCNC_big20
benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/FPGA_SPICE_bench
odin2_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ODIN_II/odin_II.exe
cirkit_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_majccmap/abc
abc_path = /research/ece/lnis/USERS/tang/research/ABC/abc70930/abc
abc_mccl_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_vtrccmap/abc
abc_with_bb_support_path = /research/ece/lnis/USERS/tang/research/vtr7_release/abc_with_bb_support/abc
mpack1_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v1.5b/mpack
m2net_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/scripts/m2net.pl
mpack2_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v2/mpack2
#vpr_path = /research/ece/lnis/USERS/tang/research/vtr7_release/vpr/vpr
vpr_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/vpr
rpt_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/results
ace_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ace2/ace
[flow_conf]
flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr
#flow_type = vtr #standard|mpack2|mpack1|vtr_standard|vtr
vpr_arch = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml # Use relative path under VPR folder is OK
mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
m2net_conf = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
mpack2_arch = K6_pattern7_I24.arch
power_tech_xml = /research/ece/lnis/USERS/tang/research/vtr7_release/vtr_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
[csv_tags]
mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:
mpack2_tags = BLE Number:|BLE Fill Rate:
vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took
vpr_power_tags = PB Types|Routing

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# Standard Configuration Example
[dir_path]
#benchmark_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_verilog
#benchmark_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_blif
#benchmark_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/MCNC_big20
benchmark_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/fpga_spice_test_bench
odin2_path = /home/xitang/research/vtr_release/ODIN_II/odin_II.exe
cirkit_path = /home/xitang/tangxifan-eda-tools/branches/FPGA_MIG/abc_majccmap/abc
abc_path = /home/xitang/research/ABC/abc70930/abc
abc_mccl_path = /home/xitang/tangxifan-eda-tools/branches/FPGA_MIG/abc_vtrccmap/abc
abc_with_bb_support_path = /home/xitang/research/vtr_release/abc_with_bb_support/abc
mpack1_path = /home/xitang/tangxifan-eda-tools/branches/MPACK_v1.5b/mpack
m2net_path = /home/xitang/tangxifan-eda-tools/branches/scripts/m2net.pl
mpack2_path = /home/xitang/tangxifan-eda-tools/branches/MPACK_v2/mpack2
#vpr_path = /home/xitang/research/vtr_release/vpr/vpr
vpr_path = /home/xitang/tangxifan-eda-tools/branches/vpr7_rram/vpr/vpr
rpt_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/results
ace_path = /home/xitang/research/vtr_release/ace2/ace
[flow_conf]
flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr
#flow_type = vtr #standard|mpack2|mpack1|vtr_standard|vtr
vpr_arch = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm.xml # Use relative path under VPR folder is OK
mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
m2net_conf = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
mpack2_arch = K6_pattern7_I24.arch
#power_tech_xml = /home/xitang/research/vtr_release/vtr_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
power_tech_xml = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/power_tech_properties/tsmc40nm.xml # Use relative path under VPR folder is OK
[csv_tags]
mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:
mpack2_tags = BLE Number:|BLE Fill Rate:
vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles:
vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff

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#!usr/bin/perl -w
use strict;
#use Shell;
#Use the time
use Time::gmtime;
#Get Date
my $mydate = gmctime();
my ($fname,$frpt);
sub print_usage()
{
print "Usage:\n";
print " perl <script_name.pl> [-options]\n";
print " Options:(Mandatory!)\n";
print " -i <input_blif_path>\n";
print " -o <output_blif_path>\n";
print "\n";
return 1;
}
sub opts_read()
{
if (-1 == $#ARGV)
{
print "Error: No input argument!\n";
&print_usage();
exit(1);
}
else
{
for (my $iargv = 0; $iargv < $#ARGV+1; $iargv++)
{
if ("-i" eq $ARGV[$iargv])
{$fname = $ARGV[$iargv+1];}
elsif ("-o" eq $ARGV[$iargv])
{$frpt = $ARGV[$iargv+1];}
}
}
return 1;
}
sub scan_blif()
{
my ($line,$lines);
my @tokens;
# Open src file
open(FIN, "< $fname") or die "Fail to open $fname!\n";
# Open des file
open(FOUT, "> $frpt") or die "Fail to open $frpt!\n";
while(defined($line = <FIN>)) {
chomp $line;
# Replace the < and > with [ and ], VPR does not support...
$line =~ s/</[/g;
$line =~ s/>/]/g;
# Check if this line start with ".latch", which we cares only
if ($line =~ m/\.names/) {
# check the continue line
$lines = $line; # empty the buffer
while($lines =~ m/\\$/) {
$line = <FIN>;
chomp $line;
$lines =~ s/\\$//;
$lines = $lines.$line;
}
@tokens = split('\s+',$lines);
if (($#tokens - 1) == 3) {
print FOUT ".gate CARRY a=$tokens[1] b=$tokens[2] c=$tokens[3] O=$tokens[4]\n";
} elsif (($#tokens - 1) == 2) {
print FOUT ".gate AND a=$tokens[1] b=$tokens[2] O=$tokens[3]\n";
} elsif (($#tokens - 1) == 1) {
$line = <FIN>;
if ($line =~ m/^0/) {
print FOUT ".gate INV a=$tokens[1] O=$tokens[2]\n";
} else {
print FOUT ".gate BUF a=$tokens[1] O=$tokens[2]\n";
}
} elsif (($#tokens - 1) == 0) { # constant generator
$line = <FIN>;
if ($line =~ m/^0/) {
print FOUT ".gate ZERO O=$tokens[1]\n";
} else {
print FOUT ".gate ONE O=$tokens[1]\n";
}
}
} else {
print FOUT "$line\n";
}
}
close(FIN);
close(FOUT);
return 1;
}
sub main()
{
&opts_read();
&scan_blif();
return 1;
}
&main();
exit(1);

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#!usr/bin/perl -w
use strict;
#use Shell;
use Time::gmtime;
use Switch;
use File::Path;
use Cwd;
my $mydate = gmctime();
my $cwd = getcwd();
sub gen_fpga_arch($ $)
{
my ($k,$n) = @_;
my ($arch_file) = ("tmp.xml");
my ($i) = int(0.5+$k*($n+1)/2);
print "K=$k N=$n I=$i\n";
my ($seq_out_up) = (2*$n-1);
my %ble_h;
my $ble_ptr = \%ble_h;
my @comb;
my @seq;
my ($j);
for ($j=0; $j<$k*$n; $j++) {
my ($idx) = int($j/$k);
print "idx=$idx";
my ($input) = $j%$k;
print " input=$input\n";
$ble_ptr->{"ble_in$j"}->{ble_idx} = $idx;
$ble_ptr->{"ble_in$j"}->{ble_input_idx} = $input;
if ($input < $idx) {
$ble_ptr->{"ble_in$j"}->{comb_in} = $input;
}
else {
$ble_ptr->{"ble_in$j"}->{comb_in} = -1;
}
$ble_ptr->{"ble$idx"}->{"input$input"}->{idx} = $j;
}
my ($iseq,$icomb) = (0,0);
for (my $ible=0; $ible<$n; $ible++) {
for (my $in=0; $in<$ible; $in++) {
if ($in < $ible) {
$comb[$icomb] = $ble_ptr->{"ble$ible"}->{"input$in"}->{idx};
$icomb++;
}
}
for (my $in=$ible; $in<$k; $in++) {
if ($in < $k) {
$seq[$iseq] = $ble_ptr->{"ble$ible"}->{"input$in"}->{idx};
$iseq++;
}
}
}
open (FARCH," > $arch_file") or die "Fail to create $arch_file";
print FARCH "<pb_type name=\"clb\">\n";
print FARCH " <input name=\"I\" num_pins=\"$i\" equivalent=\"true\"/>\n";
print FARCH " <output name=\"O\" num_pins=\"$n\" equivalent=\"false\"/>\n";
print FARCH " <clock name=\"clk\" num_pins=\"1\"/>\n";
print FARCH " <interconnect>\n";
print FARCH " <complete name=\"clks\" input=\"clb.clk\" output=\"ble.clk\"/>\n";
print FARCH " <complete name=\"crossbar_in0\" input=\"clb.I ble.out[$seq_out_up:$n]\" output=\"";
foreach my $tmp(@seq) {
print FARCH "ble.in[$tmp] ";
}
print FARCH "\">\n";
print FARCH " <delay_constant max=\"9.5e-11\" in_port=\"clb.I\" out_port=\"";
foreach my $tmp(@seq) {
print FARCH "ble.in[$tmp] ";
}
print FARCH "\"/>\n";
print FARCH " <delay_constant max=\"7.5e-11\" in_port=\"ble.out[$seq_out_up:$n] \" out_port=\"";
foreach my $tmp(@seq) {
print FARCH "ble.in[$tmp] ";
}
print FARCH "\"/>\n";
print FARCH "</complete>\n";
my ($imux) = (0);
foreach my $tmp(@comb) {
print FARCH " <complete name=\"mux$imux\" input=\"clb.I ble.out[$seq_out_up:$n] ble.out[".$ble_ptr->{"ble_in$tmp"}->{comb_in}."]\" output=\"ble.in[$tmp]\">\n";
print FARCH " <delay_constant max=\"9.5e-11\" in_port=\"clb.I\" out_port=\"ble.in[$tmp]\"/>\n";
print FARCH " <delay_constant max=\"7.5e-11\" in_port=\"ble.out[$ble_ptr->{\"ble_in$tmp\"}->{comb_in}] \" out_port=\"ble.in[$tmp]\"/>\n";
print FARCH " </complete>\n";
$imux++;
}
for (my $i=0; $i<$n; $i++) {
my $j = $i + $n;
print FARCH " <mux name=\"mux$imux\" input=\"ble.out[$i] ble.out[$j]\" output=\"clb.O[$i]\">\n";
print FARCH " <delay_constant max=\"9.5e-11\" in_port=\"ble.out[$i]\" out_port=\"clb.O[$i]\"/>\n";
print FARCH " <delay_constant max=\"7.5e-11\" in_port=\"ble.out[$j]\" out_port=\"clb.O[$i]\"/>\n";
print FARCH " </mux>\n";
$imux++;
}
print FARCH " </interconnect>\n";
}
sub main()
{
my ($k,$n) = (6,7);
&gen_fpga_arch($k,$n);
}
&main();

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#!usr/bin/perl -w
use strict;
#use Shell;
use FileHandle;
#Use the time
use Time::gmtime;
#Get Date
my $mydate = gmctime();
my ($char_per_line) = (80);
my ($fname,$frpt);
my ($remove_buffers) = (0);
my ($default_clk_name) = ("clk");
my @buffers_to_remove;
my @buffers_to_rename;
sub print_usage()
{
print "Usage:\n";
print " perl <script_name.pl> [-options]\n";
print " Options:(Mandatory!)\n";
print " -i <input_blif_path>\n";
print " -o <output_blif_path>\n";
print " Options: (Optional)\n";
print " -remove_buffers\n";
print "\n";
return 1;
}
sub opts_read()
{
if (-1 == $#ARGV)
{
print "Error: No input argument!\n";
&print_usage();
exit(1);
}
else
{
for (my $iargv = 0; $iargv < $#ARGV+1; $iargv++)
{
if ("-i" eq $ARGV[$iargv])
{$fname = $ARGV[$iargv+1];}
elsif ("-o" eq $ARGV[$iargv])
{$frpt = $ARGV[$iargv+1];}
elsif ("-remove_buffers" eq $ARGV[$iargv]) {
$remove_buffers = 1;
}
}
}
return 1;
}
# Print a line of blif netlist
sub fprint_blifln($ $ $) {
my ($FH, $tokens_ref, $char_per_line) = @_;
my ($cur_line_len) = (0);
my @tokens = @$tokens_ref;
if ($char_per_line < 1) {
die "ERROR: (fprint_blifln) minimum acceptable number of chars in a line is 1!\n";
}
# if the length of current line exceed the char_per_line,
# A continue line '\' is added and start a new line
for (my $itok = 0; $itok < ($#tokens+1); $itok++) {
if (!($tokens[$itok])) {
next;
}
# Contain any buffer names to be removed won't show up
if (1 == $remove_buffers) {
for (my $ibuf = 0; $ibuf < $#buffers_to_remove + 1; $ibuf++) {
if ($tokens[$itok] eq $buffers_to_remove[$ibuf]) {
$tokens[$itok] = $buffers_to_rename[$ibuf];
}
}
}
$cur_line_len += length($tokens[$itok]);
if ($cur_line_len > $char_per_line) {
print $FH "\\"."\n";
$cur_line_len = 0;
}
print $FH "$tokens[$itok] ";
$cur_line_len += length($tokens[$itok]);
}
print $FH "\n";
}
sub read_blifline($ $) {
my ($FIN, $line_no_ptr) = @_;
my ($lines,$line) = ("","");
# Get one line
if (defined($line = <$FIN>)) {
chomp $line;
$lines = $line;
# Replace the < and > with [ and ], VPR does not support...
$lines =~ s/</[/g;
$lines =~ s/>/]/g;
while($lines =~ m/\\$/) {
$lines =~ s/\\$//;
if (defined($line = <$FIN>)) {
chomp $line;
$lines = $lines.$line;
$line =~ s/</[/g;
$line =~ s/>/]/g;
} else {
return $lines;
}
}
return $lines;
} else {
return $lines;
}
}
sub process_blifmodel($ $) {
my ($FIN,$line_no_ptr) = @_;
my ($blackbox) = (0);
my ($lines);
my ($clk_num,$have_default_clk,$need_default_clk,$clk_recorded) = (0,0,0,0);
my @model_input_tokens;
my ($input_lines);
while(!eof($FIN)) {
# Get one line
$lines = &read_blifline($FIN,$line_no_ptr);
# Check the tokens
if (!defined($lines)) {
next;
}
my @tokens = split('\s+',$lines);
# .end -> return
if (!defined($tokens[0])) {
next;
}
if (".end" eq $tokens[0]) {
return (\@model_input_tokens,$blackbox,$clk_num,$have_default_clk,$need_default_clk);
} elsif (".inputs" eq $tokens[0]) {
foreach my $temp(@tokens) {
if ($temp eq $default_clk_name) {
$have_default_clk = 1;
$clk_num++;
last;
}
}
@model_input_tokens = @tokens;
} elsif (".blackbox" eq $tokens[0]) {
$blackbox = 1;
} elsif (".latch" eq $tokens[0]) {
# illegal definition exit
if ((3 != $#tokens)&&(5 != $#tokens)) {
die "ERROR: [LINE: $$line_no_ptr]illegal definition of latch!\n";
} elsif (3 == $#tokens) {
# We need a default clock
if ($need_default_clk == 0) {
$need_default_clk = 1;
$clk_num++;
}
} elsif (5 == $#tokens) {
$clk_recorded = 0;
# Check if we have this clk names already
foreach my $tmp(@model_input_tokens) {
if ($tmp eq $tokens[4]) {
$clk_recorded = 1;
last;
}
}
# if have been recorded, we push it into the array
if (0 == $clk_recorded) {
$clk_num++;
push @model_input_tokens,$tokens[4];
}
}
# Could be subckt or .names
} elsif (".names" eq $tokens[0]) {
if ((3 == ($#tokens + 1))&&(1 == $remove_buffers)) {
# We want to know is this a buffer???
my $lut_lines = &read_blifline($FIN,$line_no_ptr);
my @lut_lines_tokens = split('\s+',$lut_lines);
if ((2 == ($#lut_lines_tokens + 1))&&("1" eq $lut_lines_tokens[0])&&("1" eq $lut_lines_tokens[1])) {
# push it to the array: buffers_to_remove
push @buffers_to_remove,$tokens[1];
push @buffers_to_rename,$tokens[2];
}
}
}
}
# Re-organise the input lines
#print @model_input_tokens;
$input_lines = ".inputs ";
foreach my $temp(@model_input_tokens) {
if (".inputs" ne $temp) {
$input_lines .= $temp." ";
}
}
$input_lines =~ s/\s+$//;
@model_input_tokens = split('\s+',$input_lines);
return (\@model_input_tokens,$blackbox,$clk_num,$have_default_clk,$need_default_clk);
}
sub scan_blif()
{
my ($line,$lines);
my @tokens;
my ($clk_num,$have_default_clk,$need_default_clk,$clk_recorded);
my ($blackbox,$model_clk_num);
my @input_tokens;
my $input_lines;
my (@input_buffer);
my ($line_no) = (0);
# Pre-process the netlist
# Open src file first-scan to check if we have clock
my ($FIN) = FileHandle->new;
if ($FIN->open("< $fname")) {
print "INFO: Parsing $fname...\n";
} else {
die "ERROR: Fail to open $fname!\n";
}
while(!eof($FIN)) {
# Get one line
$lines = &read_blifline($FIN);
if (!defined($lines)) {
next;
}
@tokens = split('\s+',$lines);
if (!defined($tokens[0])) {
next;
}
# When we found .model we should check it. until .end comes.
# Check if it is a black box
if (".model" eq $tokens[0]) {
($input_lines,$blackbox,$model_clk_num,$have_default_clk,$need_default_clk) = &process_blifmodel($FIN,\$line_no);
if (0 == $blackbox) {
@input_tokens = @$input_lines;
}
$clk_num += $model_clk_num;
}
}
close($FIN);
# Add default clock
print "INFO: $clk_num clock ports need to be added.\n";
print "INFO: have_default_clk: $have_default_clk, need_default_clk: $need_default_clk\n";
if ((0 == $have_default_clk)&&(1 == $need_default_clk)) {
push @input_tokens,$default_clk_name;
}
# Bypass some sensitive tokens
for(my $itok = 0; $itok < $#input_tokens+1; $itok++) {
if ("unconn" eq $input_tokens[$itok]) {
delete $input_tokens[$itok];
}
}
# Print Buffer names to be removed
my $num_buffer_to_remove = $#buffers_to_remove + 1;
print "INFO: $num_buffer_to_remove buffer to be removed:\n";
for(my $itok = 0; $itok < $#buffers_to_remove+1; $itok++) {
print $buffers_to_remove[$itok]." will be renamed to ".$buffers_to_rename[$itok]."\n";
}
# Second scan - write
my ($inputs_written) = (0);
my ($FIN2) = FileHandle->new;
if ($FIN2->open("< $fname")) {
print "INFO: Parsing $fname the second time...\n";
} else {
die "ERROR: Fail to open $fname!\n";
}
# Open des file
my ($FOUT) = (FileHandle->new);
if (!($FOUT->open("> $frpt"))) {
die "Fail to create output file: $frpt!\n";
}
while(!eof($FIN2)) {
$line = <$FIN2>;
chomp $line;
if ($line eq "") {
print $FOUT "\n";
next;
}
# Replace the < and > with [ and ], VPR does not support...
$line =~ s/</[/g;
$line =~ s/>/]/g;
# Check if this line start with ".latch", which we cares only
@tokens = split('\s+',$line);
if ((".inputs" eq $tokens[0])&&(0 == $inputs_written)) {
$lines = $line;
while($lines =~ m/\\$/) {
$line = <$FIN2>;
chomp $line;
# Replace the < and > with [ and ], VPR does not support...
$line =~ s/</[/g;
$line =~ s/>/]/g;
$lines =~ s/\\$//;
$lines = $lines.$line;
}
#print @input_tokens."\n";
&fprint_blifln($FOUT,\@input_tokens,$char_per_line);
$inputs_written = 1;
next;
}
if (".outputs" eq $tokens[0]) {
$lines = $line;
while($lines =~ m/\\$/) {
$line = <$FIN2>;
chomp $line;
# Replace the < and > with [ and ], VPR does not support...
$line =~ s/</[/g;
$line =~ s/>/]/g;
$lines =~ s/\\$//;
$lines = $lines.$line;
}
my @output_tokens = split('\s',$lines);
for(my $itok = 0; $itok < $#output_tokens+1; $itok++) {
if ("unconn" eq $output_tokens[$itok]) {
delete $output_tokens[$itok];
}
}
&fprint_blifln($FOUT,\@output_tokens,$char_per_line);
next;
}
if (".latch" eq $tokens[0]) {
# check if we need complete it
if ($#tokens == 3) {
# Complete it
for (my $i=0; $i<3; $i++) {
print $FOUT "$tokens[$i] ";
}
print $FOUT "re clk $tokens[3]\n";
} elsif ($#tokens == 5) {
# replace the clock name with clk
for (my $i=0; $i < ($#tokens+1); $i++) {
# if (4 == $i) {
# print $FOUT "clk ";
# } else {
print $FOUT "$tokens[$i] ";
# }
}
print $FOUT "\n";
} else {
die "ERROR: [LINE: $line_no]illegal definition of latch!\n";
}
next;
} elsif (".names" eq $tokens[0]) {
if ((3 == ($#tokens + 1))&&(1 == $remove_buffers)) {
# We want to know is this a buffer???
my $lut_lines = &read_blifline($FIN2,\$line_no);
my @lut_lines_tokens = split('\s+',$lut_lines);
if ((2 == ($#lut_lines_tokens + 1))&&("1" eq $lut_lines_tokens[0])&&("1" eq $lut_lines_tokens[1])) {
# pass it.
next;
} else {
print $FOUT "$line\n";
print $FOUT "$lut_lines\n";
}
} else {
print $FOUT "$line\n";
}
next;
} elsif ((".subckt" eq $tokens[0])&&(1 == $remove_buffers)) {
$lines = $line;
$lines =~ s/\s+$//;
while($lines =~ m/\\$/) {
$line = <$FIN2>;
chomp $line;
# Replace the < and > with [ and ], VPR does not support...
$line =~ s/</[/g;
$line =~ s/>/]/g;
$lines =~ s/\\$//;
$lines = $lines.$line;
$lines =~ s/\s+$//; #ODIN II has some shit space after \ !!!!!
}
my @subckt_tokens = split('\s+',$lines);
for(my $itok = 0; $itok < $#subckt_tokens+1; $itok++) {
if (($itok > 1)&&("" ne $subckt_tokens[$itok])) {
my @port_tokens = split('=',$subckt_tokens[$itok]);
for (my $ibuf = 0; $ibuf < $#buffers_to_remove + 1; $ibuf++) {
if ($port_tokens[1] eq $buffers_to_remove[$ibuf]) {
$port_tokens[1] = $buffers_to_rename[$ibuf];
}
}
$subckt_tokens[$itok] = join ('=',$port_tokens[0],$port_tokens[1]);
#print "See:".$subckt_tokens[$itok]."\n";
}
}
&fprint_blifln($FOUT,\@subckt_tokens,$char_per_line);
next;
}
print $FOUT "$line\n";
}
close($FIN2);
close($FOUT);
return 1;
}
sub main()
{
&opts_read();
&scan_blif();
return 1;
}
&main();
exit(1);

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fpga_flow/scripts/run_fpga_spice.pl Normal file
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#!/usr/bin/perl -w
use strict;
#use Shell;
my $i;
sub main{
for ($i=3;$i<7;$i++) {
my $pid = fork();
if (0 == $pid) {
my $n = $i + 1;
return `perl fpga_flow.pl -conf ./configs/K$i\_N$n\_22nm_new.conf -benchmark ./benchmarks/circuits.txt -rpt K$i\_N$n\_22nm_new_full.csv -N $n -K $i`;
}
}
#for ($i=3;$i<7;$i++) {
# my $pid = fork();
# if (0 == $pid) {
# my $n = $i + 1;
# return `perl fpga_flow.pl -conf ./configs/K$i\_N$n\_22nm.conf -benchmark ./benchmarks/circuits.txt -rpt K$i\_N$n\_22nm.csv -N $n -K $i`;
# }
#}
#for ($i=1;$i<7;$i++) {
# my $pid = fork();
# if (0 == $pid) {
# return `perl fpga_flow.pl -conf ./configs/K3M2_N$i\_22nm.conf -benchmark ./benchmarks/circuits.txt -rpt K3M2_N$i\_22nm.csv -N $i -K 3`;
# }
#}
#for ($i=1;$i<11;$i++) {
# my $pid = fork();
# if (0 == $pid) {
# return `perl fpga_flow.pl -conf ./configs/K6_N$i\_22nm.conf -benchmark ./benchmarks/circuits.txt -rpt K6_N$i\_22nm.csv -N $i -K 6`;
# }
#}
#wait(-1);
}
&main();

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[dir_path]
result_dir = results
shell_script_name = run_hspice_sim.sh
# dir names
pb_mux_tb_dir_name = pb_mux_tb
cb_mux_tb_dir_name = cb_mux_tb
sb_mux_tb_dir_name = sb_mux_tb
top_tb_dir_name = top_tb
grid_tb_dir_name = grid_tb
lut_tb_dir_name = lut_tb
hardlogic_tb_dir_name = hardlogic_tb
cb_tb_dir_name = cb_tb
sb_tb_dir_name = sb_tb
# Prefix
top_tb_prefix =
pb_mux_tb_prefix = _grid
cb_mux_tb_prefix = _cb
sb_mux_tb_prefix = _sb
lut_tb_prefix = _grid
hardlogic_tb_prefix = _grid
grid_tb_prefix = _grid
cb_tb_prefix = _cb
sb_tb_prefix = _sb
# Postfix
top_tb_postfix = _top.sp
pb_mux_tb_postfix = _pbmux_testbench.sp
cb_mux_tb_postfix = _cbmux_testbench.sp
sb_mux_tb_postfix = _sbmux_testbench.sp
lut_tb_postfix = _lut_testbench.sp
hardlogic_tb_postfix = _hardlogic_testbench.sp
grid_tb_postfix = _grid_testbench.sp
cb_tb_postfix = _cb_testbench.sp
sb_tb_postfix = _sb_testbench.sp
[task_conf]
auto_check = on
num_pb_mux_tb =
num_cb_mux_tb =
num_sb_mux_tb =
num_lut_mux_tb =
num_hardlogic_tb =
num_grid_mux_tb =
num_top_tb =
num_cb_tb =
num_sb_tb =
[csv_tags]
#top_tb_leakage_power_tags = leakage_power_sram_local_routing|leakage_power_sram_luts|leakage_power_sram_cbs|leakage_power_sram_sbs|leakage_power_io|leakage_power_local_interc|total_leakage_power_lut5|total_leakage_power_lut6|total_leakage_power_dff|leakage_power_cbs|leakage_power_sbs
top_tb_leakage_power_tags = leakage_power_sram_local_routing|leakage_power_sram_luts|leakage_power_sram_cbs|leakage_power_sram_sbs|leakage_power_local_interc|total_leakage_power_lut6|total_leakage_power_dff|leakage_power_cbs|leakage_power_sbs
#top_tb_dynamic_power_tags = energy_per_cycle_sram_local_routing|energy_per_cycle_sram_luts|energy_per_cycle_sram_cbs|energy_per_cycle_sram_sbs|energy_per_cycle_io|energy_per_cycle_local_routing|total_energy_per_cycle_lut5|total_energy_per_cycle_lut6|total_energy_per_cycle_dff|energy_per_cycle_cbs|energy_per_cycle_sbs
top_tb_dynamic_power_tags = energy_per_cycle_sram_local_routing|energy_per_cycle_sram_luts|energy_per_cycle_sram_cbs|energy_per_cycle_sram_sbs|energy_per_cycle_local_routing|total_energy_per_cycle_lut6|total_energy_per_cycle_dff|energy_per_cycle_cbs|energy_per_cycle_sbs #|crit_path_delay
pb_mux_tb_leakage_power_tags = total_leakage_srams|total_leakage_power_pb_mux
cb_mux_tb_leakage_power_tags = total_leakage_srams|total_leakage_power_cb_mux
sb_mux_tb_leakage_power_tags = total_leakage_srams|total_leakage_power_sb_mux
pb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams|total_energy_per_cycle_pb_mux
cb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams|total_energy_per_cycle_cb_mux
sb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams|total_energy_per_cycle_sb_mux
lut_tb_leakage_power_tags = leakage_power_sram_luts|total_leakage_power_lut6
lut_tb_dynamic_power_tags = energy_per_cycle_sram_luts|total_energy_per_cycle_lut6
hardlogic_tb_leakage_power_tags = total_leakage_power_dff
hardlogic_tb_dynamic_power_tags = total_energy_per_cycle_dff
grid_tb_leakage_power_tags = leakage_power_sram_local_routing|leakage_power_sram_luts|leakage_power_local_routing|total_leakage_power_lut6|total_leakage_power_dff
grid_tb_dynamic_power_tags = total_energy_per_cycle_sram_local_routing|total_energy_per_cycle_sram_luts|total_energy_per_cycle_local_routing|total_energy_per_cycle_lut6|total_energy_per_cycle_dff
cb_tb_leakage_power_tags = leakage_power_cb|leakage_power_sram_cb
cb_tb_dynamic_power_tags = energy_per_cycle_cb|energy_per_cycle_sram_cb
sb_tb_leakage_power_tags = leakage_power_sb|leakage_power_sram_sb
sb_tb_dynamic_power_tags = energy_per_cycle_sb|energy_per_cycle_sram_sb

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# Make sure a clear start
# Sweep Corner Cases
set corner_list = (TT)
#set corner_list = (TT FF SS MC)
foreach j ($corner_list)
#rm -rf ./results
cd ./scripts
if ($j == MC) then
set mc_opt = (-monte_carlo detail_rpt)
else
set mc_opt = ()
endif
perl fpga_flow.pl -conf ../configs/fpga_spice/k6_N10_sram_tsmc40nm_$j\.conf -benchmark ../benchmarks/fpga_spice_bench.txt -rpt ../csv_rpts/fpga_spice/k6_N10_sram_tsmc40nm_bench_$j\.csv -N 10 -K 6 -power -remove_designs -multi_thread 1 -vpr_fpga_spice ../vpr_fpga_spice_task_lists/k6_N10_sram_tsmc40nm -vpr_fpga_spice_rename_illegal_port -vpr_fpga_spice_sim_mt_num 16 -vpr_fpga_spice_print_top_tb #-vpr_fpga_spice_parasitic_net_estimation_off #-vpr_fpga_spice_leakage_only -vpr_fpga_spice_print_component_tb -vpr_fpga_spice_print_grid_tb
perl run_fpga_spice.pl -conf ../vpr_fpga_spice_conf/sample.conf -task ../vpr_fpga_spice_task_lists/k6_N10_sram_tsmc40nm_standard.txt -rpt ../vpr_fpga_spice_csv_rpts/k6_N10_sram_tsmc40_spice_bench_$j\.csv $mc_opt -parse_top_tb -multi_thread 6 #-parse_pb_mux_tb -parse_cb_mux_tb -parse_sb_mux_tb -parse_lut_tb -parse_hardlogic_tb -parse_grid_tb -parse_cb_tb -parse_sb_tb
cd ..
end

1
tangxifan-eda-tools

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Subproject commit 2d51da57b826d6984fd3141c1b36fd64d63c2256

44
vpr7_rram/Makefile Executable file
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#####################################################################
# Makefile to build CAD tools in Verilog-to-Routing (VTR) Framework #
#####################################################################
SUBDIRS = vpr libarchfpga pcre printhandler
all: notifications subdirs
subdirs: $(SUBDIRS)
$(SUBDIRS):
@ $(MAKE) -C $@ --no-print-directory
notifications:
# checks if required packages are installed, and notifies the user if not
@ if cat /etc/issue | grep Ubuntu -c >>/dev/null; then if ! dpkg -l | grep exuberant-ctags -c >>/dev/null; then echo "\n\n\n\n***************************************************************\n* Required package 'ctags' not found. *\n* Type 'make packages' to install all packages, or *\n* 'sudo apt-get install exuberant-ctags' to install manually. *\n***************************************************************\n\n\n\n"; fi; fi
@ if cat /etc/issue | grep Ubuntu -c >>/dev/null; then if ! dpkg -l | grep bison -c >>/dev/null; then echo "\n\n\n\n*****************************************************\n* Required package 'bison' not found. *\n* Type 'make packages' to install all packages, or *\n* 'sudo apt-get install bison' to install manually. *\n*****************************************************\n\n\n\n"; fi; fi
@ if cat /etc/issue | grep Ubuntu -c >>/dev/null; then if ! dpkg -l | grep flex -c >>/dev/null; then echo "\n\n\n\n*****************************************************\n* Required package 'flex' not found. *\n* Type 'make packages' to install all packages, or *\n* 'sudo apt-get install flex' to install manually. *\n*****************************************************\n\n\n\n"; fi; fi
@ if cat /etc/issue | grep Ubuntu -c >>/dev/null; then if ! dpkg -l | grep g++ -c >>/dev/null; then echo "\n\n\n\n*****************************************************\n* Required package 'g++' not found. * \n* Type 'make packages' to install all packages, or *\n* 'sudo apt-get install g++' to install manually. *\n*****************************************************\n\n\n\n"; fi; fi
packages:
# checks if required packages are installed, and installs them if not
@ if cat /etc/issue | grep Ubuntu -c >>/dev/null; then if ! dpkg -l | grep exuberant-ctags -c >>/dev/null; then sudo apt-get install exuberant-ctags; fi; fi
@ if cat /etc/issue | grep Ubuntu -c >>/dev/null; then if ! dpkg -l | grep bison -c >>/dev/null; then sudo apt-get install bison; fi; fi
@ if cat /etc/issue | grep Ubuntu -c >>/dev/null; then if ! dpkg -l | grep flex -c >>/dev/null; then sudo apt-get install flex; fi; fi
@ if cat /etc/issue | grep Ubuntu -c >>/dev/null; then if ! dpkg -l | grep g++ -c >>/dev/null; then sudo apt-get install g++; fi; fi
@ cd vpr && make packages
vpr: libarchfpga
libarchfpga: printhandler
printhandler: pcre
clean:
@ cd vpr && make clean
@ cd libarchfpga && make clean
@ cd printhandler && make clean
@ cd pcre && make clean
clean_vpr:
@ cd vpr && make clean
.PHONY: packages subdirs $(SUBDIRS)

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################################ MAKEFILE OPTIONS ####################################
# By default, libarchfpga's build type (debug/release) is inherited from VPR's makefile.
# However, by uncommenting out the line BUILD_TYPE = debug, you can override this
# and set libarchfpga's build type independently.
# BUILD_TYPE = release
# (can be debug or release)
#############################################################################################
CC = g++
AR = ar
WARN_FLAGS = -Wall -Wpointer-arith -Wcast-qual -D__USE_FIXED_PROTOTYPES__ -pedantic -Wshadow -Wcast-align -D_POSIX_SOURCE -Wno-write-strings
DEBUG_FLAGS = -g
OPT_FLAGS = -O3
INC_FLAGS = -Iinclude -Ifpga_spice_include -I../printhandler/SRC/TIO_InputOutputHandlers
LIB_FLAGS = rcs
EXE = read_arch
FLAGS = $(INC_FLAGS) $(WARN_FLAGS) -MD -MP
ifneq (,$(findstring release, $(BUILD_TYPE)))
FLAGS := $(FLAGS) $(OPT_FLAGS)
else # DEBUG build
FLAGS := $(FLAGS) $(DEBUG_FLAGS)
endif
SRC = read_xml_mrfpga.c linkedlist.c read_xml_spice_util.c read_xml_spice.c read_xml_arch_file.c read_xml_util.c ezxml.c ReadLine.c util.c
OBJS = $(SRC:.c=.o)
DEPS = $(OBJS:.o=.d) main.d
# Standalone executable to test architecture reader
$(EXE): main.o libarchfpga.a
$(CC) main.o -o $(EXE) $(INC_FLAGS) -L. -lm -larchfpga
libarchfpga.a: $(OBJS) ../pcre/libpcre.a ../printhandler/libprinthandler.a
cp ../printhandler/libprinthandler.a $@
ar rcs $@ $(OBJS)
../pcre/libpcre.a:
@ cd ../pcre && make
../printhandler/libprinthandler.a:
@ cd ../printhandler && make
%.o: %.c
$(CC) $(FLAGS) -c $< -o $@
-include $(DEPS)
clean :
@ rm -f libarchfpga.a
@ rm -f $(OBJS) $(OBJS:.o=.d)
@ rm -f read_arch
@ rm -f main.o main.d

189
vpr7_rram/libarchfpga/ReadLine.c Normal file
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#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <assert.h>
#include "util.h"
#include "ReadLine.h"
/* Pass in a pointer to a token list. Is freed and then set to null */
void FreeTokens(INOUTP char ***TokensPtr) {
assert(*TokensPtr);
assert(**TokensPtr);
free(**TokensPtr); /* Free the string data */
free(*TokensPtr); /* Free token list */
*TokensPtr = NULL; /* Invalidate pointer since mem is gone */
}
/* Returns number of tokens in list. Zero if null list */
int CountTokens(INP char **Tokens) {
int count = 0;
if (NULL == Tokens) {
return 0;
};
while (Tokens[count]) {
++count;
};
return count;
}
/* Reads in a single line from file, splits into tokens and allocates
* a list of tokens. Returns the an array of character arrays with the
* final item being marked by an empty string.
* Returns NULL on EOF
* NB: Token list is does as two allocations, one for pointer list
* and one for character array. Free what pointer points to and then
* free the pointer itself */
char **
ReadLineTokens(INOUTP FILE * InFile, INOUTP int *LineNum) {
enum {
BUFFSIZE = 65536
};
/* This is much more than enough */
char Buffer[BUFFSIZE]; /* Must match BUFFSIZE */
char *Res;
char *Last;
char *Cur;
char *Dst;
char **Tokens;
int TokenCount;
int Len;
int CurToken;
boolean InToken;
do {
/* Read the string */
Res = fgets(Buffer, BUFFSIZE, InFile);
if (NULL == Res) {
if (feof(InFile)) {
return NULL; /* Return NULL on EOF */
} else {
vpr_printf(TIO_MESSAGE_ERROR, "Unexpected error reading file\n");
exit(1);
}
}
++(*LineNum);
/* Strip newline if any */
Last = Buffer + strlen(Buffer);
if ((Last > Buffer) && ('\n' == Last[-1])) {
--Last;
}
if ((Last > Buffer) && ('\r' == Last[-1])) {
--Last;
}
/* Handle continued lines */
while ((Last > Buffer) && ('\\' == Last[-1])) {
/* Strip off the backslash */
--Last;
/* Read next line by giving pointer to null-char as start for next */
Res = fgets(Last, (BUFFSIZE - (Last - Buffer)), InFile);
if (NULL == Res) {
if (feof(InFile)) {
return NULL; /* Return NULL on EOF */
} else {
vpr_printf(TIO_MESSAGE_ERROR,
"Unexpected error reading file\n");
exit(1);
}
}
++(*LineNum);
/* Strip newline */
Last = Buffer + strlen(Buffer);
if ((Last > Buffer) && ('\n' == Last[-1])) {
--Last;
}
if ((Last > Buffer) && ('\r' == Last[-1])) {
--Last;
}
}
/* Strip comment if any */
Cur = Buffer;
while (Cur < Last) {
if ('#' == *Cur) {
Last = Cur;
break;
}
++Cur;
}
/* Count tokens and find size */
assert(Last < (Buffer + BUFFSIZE));
Len = 0;
TokenCount = 0;
Cur = Buffer;
InToken = FALSE;
while (Cur < Last) {
if (InToken) {
if ((' ' == *Cur) || ('\t' == *Cur)) {
InToken = FALSE;
} else {
++Len;
}
} else {
if ((' ' != *Cur) && ('\t' != *Cur)) {
++TokenCount;
++Len;
InToken = TRUE;
}
}
++Cur; /* Advance pointer */
}
} while (0 == TokenCount);
/* Find the size of mem to alloc. Use a contiguous block so is
* easy to deallocate */
Len = (sizeof(char) * Len) + /* Length of actual data */
(sizeof(char) * TokenCount); /* Null terminators */
/* Alloc the pointer list and data list. Count the final
* empty string we will use as list terminator */
Tokens = (char **) my_malloc(sizeof(char *) * (TokenCount + 1));
*Tokens = (char *) my_malloc(sizeof(char) * Len);
/* Copy tokens to result */
Cur = Buffer;
Dst = *Tokens;
InToken = FALSE;
CurToken = 0;
while (Cur < Last) {
if (InToken) {
if ((' ' == *Cur) || ('\t' == *Cur)) {
InToken = FALSE;
*Dst = '\0'; /* Null term token */
++Dst;
++CurToken;
} else {
*Dst = *Cur; /* Copy char */
++Dst;
}
} else {
if ((' ' != *Cur) && ('\t' != *Cur)) {
Tokens[CurToken] = Dst; /* Set token start pointer */
*Dst = *Cur; /* Copy char */
++Dst;
InToken = TRUE;
}
}
++Cur; /* Advance pointer */
}
if (InToken) {
*Dst = '\0'; /* Null term final token */
++Dst;
++CurToken;
}
assert(CurToken == TokenCount);
/* Set the final empty string entry */
Tokens[CurToken] = NULL;
/* Return the string list */
return Tokens;
}

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vpr7_rram/libarchfpga/arch/README.txt Normal file
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This directory contains sample architecture files that are used in testing
libarchfpga. In addition, the architecture files in this directory are used by
the regression testing facilities of Odin II.
Please be sure to retain sample_arch.xml and update it with any changes that
are made to the libvpr library.
Ken Kent
ken@unb.ca
06.18.2009

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vpr7_rram/libarchfpga/arch/mult_luts_arch.xml Normal file
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<architecture>
<!-- jluu and ken: ODIN II specific config -->
<models>
<model name="multiply">
<input_ports>
<port name="a"/>
<port name="b"/>
</input_ports>
<output_ports>
<port name="out"/>
</output_ports>
</model>
<model name="single_port_ram">
<input_ports>
<port name="we"/> <!-- control -->
<port name="addr"/> <!-- address lines -->
<port name="data"/> <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
<port name="clk" is_clock="1"/> <!-- memories are often clocked -->
</input_ports>
<output_ports>
<port name="out"/> <!-- output can be broken down into smaller bit widths minimum size 1 -->
</output_ports>
</model>
<model name="dual_port_ram">
<input_ports>
<port name="we1"/> <!-- write enable -->
<port name="we2"/> <!-- write enable -->
<port name="addr1"/> <!-- address lines -->
<port name="addr2"/> <!-- address lines -->
<port name="data1"/> <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
<port name="data2"/> <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
<port name="clk" is_clock="1"/> <!-- memories are often clocked -->
</input_ports>
<output_ports>
<port name="out1"/> <!-- output can be broken down into smaller bit widths minimum size 1 -->
<port name="out2"/> <!-- output can be broken down into smaller bit widths minimum size 1 -->
</output_ports>
</model>
</models>
<!-- jluu and ken: ODIN II specific config ends -->
<!-- jluu and ken: Physical descriptions begin -->
<!-- <layout width="20" height="20"/> -->
<layout auto="1.0"/>
<device>
<sizing R_minW_nmos="5726.870117" R_minW_pmos="15491.700195" ipin_mux_trans_size="1.000000"/>
<timing C_ipin_cblock="1.191000e-14" T_ipin_cblock="1.482000e-10"/>
<area grid_logic_tile_area="30000.000000"/>
<chan_width_distr>
<io width="1.000000"/>
<x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/>
</chan_width_distr>
<switch_block type="wilton" fs="3"/>
</device>
<switchlist>
<switch type="mux" name="0" R="94.841003" Cin="1.537000e-14" Cout="2.194000e-13" Tdel="6.562000e-11" mux_trans_size="10.000000" buf_size="1"/>
</switchlist>
<segmentlist>
<segment freq="1.000000" length="4" type="unidir" Rmetal="11.064550" Cmetal="4.727860e-14">
<mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
</segment>
</segmentlist>
<complexblocklist>
<pb_type name="io" capacity="7">
<input name="outpad" num_pins="1" equivalent="false"/>
<output name="inpad" num_pins="1"/>
<clock name="clock" num_pins="1"/>
<!-- IOs can operate as either inputs or outputs -->
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"/>
</interconnect>
</mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"/>
</interconnect>
</mode>
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
<!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-->
<pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad io.clock</loc>
<loc side="top">io.outpad io.inpad io.clock</loc>
<loc side="right">io.outpad io.inpad io.clock</loc>
<loc side="bottom">io.outpad io.inpad io.clock</loc>
</pinlocations>
<gridlocations>
<loc type="perimeter" priority="10"/>
</gridlocations>
</pb_type>
<pb_type name="clb">
<input name="I" num_pins="56" equivalent="true"/>
<output name="O" num_pins="16"/>
<clock name="clk" num_pins="1"/>
<pb_type name="ble" num_pb="8">
<input name="in" num_pins="7"/>
<output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/>
<pb_type name="soft_logic" num_pb="1">
<input name="in" num_pins="7"/>
<output name="out" num_pins="2"/>
<mode name="n2_lut5">
<pb_type name="lut5" blif_model=".names" num_pb="2" class="lut">
<input name="in" num_pins="5" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
</pb_type>
<interconnect>
<direct name="direct1" input="soft_logic.in[4:0]" output="lut5[0:0].in[4:0]"/>
<direct name="direct2" input="lut5[0:0].out" output="soft_logic.out[0:0]"/>
<direct name="direct3" input="soft_logic.in[6:2]" output="lut5[1:1].in[4:0]"/>
<direct name="direct4" input="lut5[1:1].out" output="soft_logic.out[1:1]"/>
</interconnect>
</mode>
<mode name="n1_lut6">
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="6" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
</pb_type>
<interconnect>
<direct name="direct1" input="soft_logic.in[5:0]" output="lut6[0:0].in[5:0]"/>
<direct name="direct2" input="lut6[0:0].out" output="soft_logic.out[0:0]"/>
</interconnect>
</mode>
</pb_type>
<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
</pb_type>
<interconnect>
<!-- Two ff, make ff available to only corresponding luts -->
<direct name="direct1" input="ble.in" output="soft_logic.in"/>
<direct name="direct2" input="soft_logic.out[0:0]" output="ff[0:0].D"/>
<direct name="direct3" input="soft_logic.out[1:1]" output="ff[1:1].D"/>
<direct name="direct4" input="ble.clk" output="ff[0:0].clk"/>
<direct name="direct5" input="ble.clk" output="ff[1:1].clk"/>
<mux name="mux1" input="ff[0:0].Q soft_logic.out[0:0]" output="ble.out[0:0]"/>
<mux name="mux2" input="ff[1:1].Q soft_logic.out[1:1]" output="ble.out[1:1]"/>
</interconnect>
</pb_type>
<interconnect>
<complete name="complete1" input="clb.I ble[7:0].out" output="ble[7:0].in"/>
<complete name="complete2" input="clb.clk" output="ble[7:0].clk"/>
<direct name="direct1" input="ble[7:0].out" output="clb.O"/>
</interconnect>
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
<pinlocations pattern="spread"/>
<gridlocations>
<loc type="fill" priority="1"/>
</gridlocations>
</pb_type>
<pb_type name="memory" height="4">
<input name="addr1" num_pins="16"/>
<input name="addr2" num_pins="16"/>
<input name="data" num_pins="64"/>
<input name="we1" num_pins="1"/>
<input name="we2" num_pins="1"/>
<output name="out" num_pins="64"/>
<clock name="clk" num_pins="1"/>
<mode name="mem_1024x64_sp">
<pb_type name="mem_1024x64_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1" area="1000">
<input name="addr" num_pins="10" port_class="address"/>
<input name="data" num_pins="64" port_class="data_in"/>
<input name="we" num_pins="1" port_class="write_en"/>
<output name="out" num_pins="64" port_class="data_out"/>
<clock name="clk" num_pins="1" port_class="clock"/>
</pb_type>
<interconnect>
<direct name="address1" input="memory.addr1[9:0]" output="mem_1024x64_sp.addr">
</direct>
<direct name="data1" input="memory.data[63:0]" output="mem_1024x64_sp.data">
</direct>
<direct name="writeen1" input="memory.we1" output="mem_1024x64_sp.we">
</direct>
<direct name="dataout1" input="mem_1024x64_sp.out" output="memory.out[63:0]">
</direct>
<direct name="clk" input="memory.clk" output="mem_1024x64_sp.clk">
</direct>
</interconnect>
</mode>
<mode name="mem_2048x32_dp">
<pb_type name="mem_2048x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1" area="1000">
<input name="addr1" num_pins="11" port_class="address1"/>
<input name="addr2" num_pins="11" port_class="address2"/>
<input name="data1" num_pins="32" port_class="data_in1"/>
<input name="data2" num_pins="32" port_class="data_in2"/>
<input name="we1" num_pins="1" port_class="write_en1"/>
<input name="we2" num_pins="1" port_class="write_en2"/>
<output name="out1" num_pins="32" port_class="data_out1"/>
<output name="out2" num_pins="32" port_class="data_out2"/>
<clock name="clk" num_pins="1" port_class="clock"/>
</pb_type>
<interconnect>
<direct name="address1" input="memory.addr1[10:0]" output="mem_2048x32_dp.addr1">
</direct>
<direct name="address2" input="memory.addr2[10:0]" output="mem_2048x32_dp.addr2">
</direct>
<direct name="data1" input="memory.data[31:0]" output="mem_2048x32_dp.data1">
</direct>
<direct name="data2" input="memory.data[63:32]" output="mem_2048x32_dp.data2">
</direct>
<direct name="writeen1" input="memory.we1" output="mem_2048x32_dp.we1">
</direct>
<direct name="writeen2" input="memory.we2" output="mem_2048x32_dp.we2">
</direct>
<direct name="dataout1" input="mem_2048x32_dp.out1" output="memory.out[31:0]">
</direct>
<direct name="dataout2" input="mem_2048x32_dp.out2" output="memory.out[63:32]">
</direct>
<direct name="clk" input="memory.clk" output="mem_2048x32_dp.clk">
</direct>
</interconnect>
</mode>
<mode name="mem_2048x32_sp">
<pb_type name="mem_2048x32_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1" area="1000">
<input name="addr" num_pins="11" port_class="address"/>
<input name="data" num_pins="32" port_class="data_in"/>
<input name="we" num_pins="1" port_class="write_en"/>
<output name="out" num_pins="32" port_class="data_out"/>
<clock name="clk" num_pins="1" port_class="clock"/>
</pb_type>
<interconnect>
<direct name="address1" input="memory.addr1[10:0]" output="mem_2048x32_sp.addr">
</direct>
<direct name="data1" input="memory.data[31:0]" output="mem_2048x32_sp.data">
</direct>
<direct name="writeen1" input="memory.we1" output="mem_2048x32_sp.we">
</direct>
<direct name="dataout1" input="mem_2048x32_sp.out" output="memory.out[31:0]">
</direct>
<direct name="clk" input="memory.clk" output="mem_2048x32_sp.clk">
</direct>
</interconnect>
</mode>
<mode name="mem_4096x16_dp">
<pb_type name="mem_4096x16_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1" area="1000">
<input name="addr1" num_pins="12" port_class="address1"/>
<input name="addr2" num_pins="12" port_class="address2"/>
<input name="data1" num_pins="16" port_class="data_in1"/>
<input name="data2" num_pins="16" port_class="data_in2"/>
<input name="we1" num_pins="1" port_class="write_en1"/>
<input name="we2" num_pins="1" port_class="write_en2"/>
<output name="out1" num_pins="16" port_class="data_out1"/>
<output name="out2" num_pins="16" port_class="data_out2"/>
<clock name="clk" num_pins="1" port_class="clock"/>
</pb_type>
<interconnect>
<direct name="address1" input="memory.addr1[11:0]" output="mem_4096x16_dp.addr1">
</direct>
<direct name="address2" input="memory.addr2[11:0]" output="mem_4096x16_dp.addr2">
</direct>
<direct name="data1" input="memory.data[15:0]" output="mem_4096x16_dp.data1">
</direct>
<direct name="data2" input="memory.data[31:16]" output="mem_4096x16_dp.data2">
</direct>
<direct name="writeen1" input="memory.we1" output="mem_4096x16_dp.we1">
</direct>
<direct name="writeen2" input="memory.we2" output="mem_4096x16_dp.we2">
</direct>
<direct name="dataout1" input="mem_4096x16_dp.out1" output="memory.out[15:0]">
</direct>
<direct name="dataout2" input="mem_4096x16_dp.out2" output="memory.out[31:16]">
</direct>
<direct name="clk" input="memory.clk" output="mem_4096x16_dp.clk">
</direct>
</interconnect>
</mode>
<mode name="mem_4096x16_sp">
<pb_type name="mem_4096x16_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1" area="1000">
<input name="addr" num_pins="12" port_class="address"/>
<input name="data" num_pins="16" port_class="data_in"/>
<input name="we" num_pins="1" port_class="write_en"/>
<output name="out" num_pins="16" port_class="data_out"/>
<clock name="clk" num_pins="1" port_class="clock"/>
</pb_type>
<interconnect>
<direct name="address1" input="memory.addr1[11:0]" output="mem_4096x16_sp.addr">
</direct>
<direct name="data1" input="memory.data[15:0]" output="mem_4096x16_sp.data">
</direct>
<direct name="writeen1" input="memory.we1" output="mem_4096x16_sp.we">
</direct>
<direct name="dataout1" input="mem_4096x16_sp.out" output="memory.out[15:0]">
</direct>
<direct name="clk" input="memory.clk" output="mem_4096x16_sp.clk">
</direct>
</interconnect>
</mode>
<mode name="mem_8192x8_dp">
<pb_type name="mem_8192x8_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1" area="1000">
<input name="addr1" num_pins="13" port_class="address1"/>
<input name="addr2" num_pins="13" port_class="address2"/>
<input name="data1" num_pins="8" port_class="data_in1"/>
<input name="data2" num_pins="8" port_class="data_in2"/>
<input name="we1" num_pins="1" port_class="write_en1"/>
<input name="we2" num_pins="1" port_class="write_en2"/>
<output name="out1" num_pins="8" port_class="data_out1"/>
<output name="out2" num_pins="8" port_class="data_out2"/>
<clock name="clk" num_pins="1" port_class="clock"/>
</pb_type>
<interconnect>
<direct name="address1" input="memory.addr1[12:0]" output="mem_8192x8_dp.addr1">
</direct>
<direct name="address2" input="memory.addr2[12:0]" output="mem_8192x8_dp.addr2">
</direct>
<direct name="data1" input="memory.data[7:0]" output="mem_8192x8_dp.data1">
</direct>
<direct name="data2" input="memory.data[15:8]" output="mem_8192x8_dp.data2">
</direct>
<direct name="writeen1" input="memory.we1" output="mem_8192x8_dp.we1">
</direct>
<direct name="writeen2" input="memory.we2" output="mem_8192x8_dp.we2">
</direct>
<direct name="dataout1" input="mem_8192x8_dp.out1" output="memory.out[7:0]">
</direct>
<direct name="dataout2" input="mem_8192x8_dp.out2" output="memory.out[15:8]">
</direct>
<direct name="clk" input="memory.clk" output="mem_8192x8_dp.clk">
</direct>
</interconnect>
</mode>
<mode name="mem_8192x8_sp">
<pb_type name="mem_8192x8_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1" area="1000">
<input name="addr" num_pins="13" port_class="address"/>
<input name="data" num_pins="8" port_class="data_in"/>
<input name="we" num_pins="1" port_class="write_en"/>
<output name="out" num_pins="8" port_class="data_out"/>
<clock name="clk" num_pins="1" port_class="clock"/>
</pb_type>
<interconnect>
<direct name="address1" input="memory.addr1[12:0]" output="mem_8192x8_sp.addr">
</direct>
<direct name="data1" input="memory.data[7:0]" output="mem_8192x8_sp.data">
</direct>
<direct name="writeen1" input="memory.we1" output="mem_8192x8_sp.we">
</direct>
<direct name="dataout1" input="mem_8192x8_sp.out" output="memory.out[7:0]">
</direct>
<direct name="clk" input="memory.clk" output="mem_8192x8_sp.clk">
</direct>
</interconnect>
</mode>
<mode name="mem_16384x4_dp">
<pb_type name="mem_16384x4_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1" area="1000">
<input name="addr1" num_pins="14" port_class="address1"/>
<input name="addr2" num_pins="14" port_class="address2"/>
<input name="data1" num_pins="4" port_class="data_in1"/>
<input name="data2" num_pins="4" port_class="data_in2"/>
<input name="we1" num_pins="1" port_class="write_en1"/>
<input name="we2" num_pins="1" port_class="write_en2"/>
<output name="out1" num_pins="4" port_class="data_out1"/>
<output name="out2" num_pins="4" port_class="data_out2"/>
<clock name="clk" num_pins="1" port_class="clock"/>
</pb_type>
<interconnect>
<direct name="address1" input="memory.addr1[13:0]" output="mem_16384x4_dp.addr1">
</direct>
<direct name="address2" input="memory.addr2[13:0]" output="mem_16384x4_dp.addr2">
</direct>
<direct name="data1" input="memory.data[3:0]" output="mem_16384x4_dp.data1">
</direct>
<direct name="data2" input="memory.data[7:4]" output="mem_16384x4_dp.data2">
</direct>
<direct name="writeen1" input="memory.we1" output="mem_16384x4_dp.we1">
</direct>
<direct name="writeen2" input="memory.we2" output="mem_16384x4_dp.we2">
</direct>
<direct name="dataout1" input="mem_16384x4_dp.out1" output="memory.out[3:0]">
</direct>
<direct name="dataout2" input="mem_16384x4_dp.out2" output="memory.out[7:4]">
</direct>
<direct name="clk" input="memory.clk" output="mem_16384x4_dp.clk">
</direct>
</interconnect>
</mode>
<mode name="mem_16384x4_sp">
<pb_type name="mem_16384x4_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1" area="1000">
<input name="addr" num_pins="14" port_class="address"/>
<input name="data" num_pins="4" port_class="data_in"/>
<input name="we" num_pins="1" port_class="write_en"/>
<output name="out" num_pins="4" port_class="data_out"/>
<clock name="clk" num_pins="1" port_class="clock"/>
</pb_type>
<interconnect>
<direct name="address1" input="memory.addr1[13:0]" output="mem_16384x4_sp.addr">
</direct>
<direct name="data1" input="memory.data[3:0]" output="mem_16384x4_sp.data">
</direct>
<direct name="writeen1" input="memory.we1" output="mem_16384x4_sp.we">
</direct>
<direct name="dataout1" input="mem_16384x4_sp.out" output="memory.out[3:0]">
</direct>
<direct name="clk" input="memory.clk" output="mem_16384x4_sp.clk">
</direct>
</interconnect>
</mode>
<mode name="mem_32768x2_dp">
<pb_type name="mem_32768x2_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1" area="1000">
<input name="addr1" num_pins="15" port_class="address1"/>
<input name="addr2" num_pins="15" port_class="address2"/>
<input name="data1" num_pins="2" port_class="data_in1"/>
<input name="data2" num_pins="2" port_class="data_in2"/>
<input name="we1" num_pins="1" port_class="write_en1"/>
<input name="we2" num_pins="1" port_class="write_en2"/>
<output name="out1" num_pins="2" port_class="data_out1"/>
<output name="out2" num_pins="2" port_class="data_out2"/>
<clock name="clk" num_pins="1" port_class="clock"/>
</pb_type>
<interconnect>
<direct name="address1" input="memory.addr1[14:0]" output="mem_32768x2_dp.addr1">
</direct>
<direct name="address2" input="memory.addr2[14:0]" output="mem_32768x2_dp.addr2">
</direct>
<direct name="data1" input="memory.data[1:0]" output="mem_32768x2_dp.data1">
</direct>
<direct name="data2" input="memory.data[3:2]" output="mem_32768x2_dp.data2">
</direct>
<direct name="writeen1" input="memory.we1" output="mem_32768x2_dp.we1">
</direct>
<direct name="writeen2" input="memory.we2" output="mem_32768x2_dp.we2">
</direct>
<direct name="dataout1" input="mem_32768x2_dp.out1" output="memory.out[1:0]">
</direct>
<direct name="dataout2" input="mem_32768x2_dp.out2" output="memory.out[3:2]">
</direct>
<direct name="clk" input="memory.clk" output="mem_32768x2_dp.clk">
</direct>
</interconnect>
</mode>
<mode name="mem_32768x2_sp">
<pb_type name="mem_32768x2_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1" area="1000">
<input name="addr" num_pins="15" port_class="address"/>
<input name="data" num_pins="2" port_class="data_in"/>
<input name="we" num_pins="1" port_class="write_en"/>
<output name="out" num_pins="2" port_class="data_out"/>
<clock name="clk" num_pins="1" port_class="clock"/>
</pb_type>
<interconnect>
<direct name="address1" input="memory.addr1[14:0]" output="mem_32768x2_sp.addr">
</direct>
<direct name="data1" input="memory.data[1:0]" output="mem_32768x2_sp.data">
</direct>
<direct name="writeen1" input="memory.we1" output="mem_32768x2_sp.we">
</direct>
<direct name="dataout1" input="mem_32768x2_sp.out" output="memory.out[1:0]">
</direct>
<direct name="clk" input="memory.clk" output="mem_32768x2_sp.clk">
</direct>
</interconnect>
</mode>
<mode name="mem_65536x1_dp">
<pb_type name="mem_65536x1_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1" area="1000">
<input name="addr1" num_pins="16" port_class="address1"/>
<input name="addr2" num_pins="16" port_class="address2"/>
<input name="data1" num_pins="1" port_class="data_in1"/>
<input name="data2" num_pins="1" port_class="data_in2"/>
<input name="we1" num_pins="1" port_class="write_en1"/>
<input name="we2" num_pins="1" port_class="write_en2"/>
<output name="out1" num_pins="1" port_class="data_out1"/>
<output name="out2" num_pins="1" port_class="data_out2"/>
<clock name="clk" num_pins="1" port_class="clock"/>
</pb_type>
<interconnect>
<direct name="address1" input="memory.addr1[15:0]" output="mem_65536x1_dp.addr1">
</direct>
<direct name="address2" input="memory.addr2[15:0]" output="mem_65536x1_dp.addr2">
</direct>
<direct name="data1" input="memory.data[0:0]" output="mem_65536x1_dp.data1">
</direct>
<direct name="data2" input="memory.data[1:1]" output="mem_65536x1_dp.data2">
</direct>
<direct name="writeen1" input="memory.we1" output="mem_65536x1_dp.we1">
</direct>
<direct name="writeen2" input="memory.we2" output="mem_65536x1_dp.we2">
</direct>
<direct name="dataout1" input="mem_65536x1_dp.out1" output="memory.out[0:0]">
</direct>
<direct name="dataout2" input="mem_65536x1_dp.out2" output="memory.out[1:1]">
</direct>
<direct name="clk" input="memory.clk" output="mem_65536x1_dp.clk">
</direct>
</interconnect>
</mode>
<mode name="mem_65536x1_sp">
<pb_type name="mem_65536x1_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1" area="1000">
<input name="addr" num_pins="16" port_class="address"/>
<input name="data" num_pins="1" port_class="data_in"/>
<input name="we" num_pins="1" port_class="write_en"/>
<output name="out" num_pins="1" port_class="data_out"/>
<clock name="clk" num_pins="1" port_class="clock"/>
</pb_type>
<interconnect>
<direct name="address1" input="memory.addr1[15:0]" output="mem_65536x1_sp.addr">
</direct>
<direct name="data1" input="memory.data[0:0]" output="mem_65536x1_sp.data">
</direct>
<direct name="writeen1" input="memory.we1" output="mem_65536x1_sp.we">
</direct>
<direct name="dataout1" input="mem_65536x1_sp.out" output="memory.out[0:0]">
</direct>
<direct name="clk" input="memory.clk" output="mem_65536x1_sp.clk">
</direct>
</interconnect>
</mode>
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
<pinlocations pattern="spread"/>
<gridlocations>
<loc type="col" start="2" repeat="5" priority="2"/>
</gridlocations>
</pb_type>
<!-- This is the 36*36 uniform mult -->
<pb_type name="mult_36" height="3">
<input name="a" num_pins="36"/>
<input name="b" num_pins="36"/>
<output name="out" num_pins="72"/>
<mode name="two_divisible_mult_18x18">
<pb_type name="divisible_mult_18x18" num_pb="2">
<input name="a" num_pins="18"/>
<input name="b" num_pins="18"/>
<output name="out" num_pins="36"/>
<mode name="two_mult_9x9">
<pb_type name="mult_9x9_slice" num_pb="2">
<input name="A_cfg" num_pins="9"/>
<input name="B_cfg" num_pins="9"/>
<output name="OUT_cfg" num_pins="18"/>
<pb_type name="mult_9x9" blif_model=".subckt multiply" num_pb="1" area="300">
<input name="a" num_pins="9"/>
<input name="b" num_pins="9"/>
<output name="out" num_pins="18"/>
<delay_constant max="2.03e-13" min="1.89e-13" in_port="{a b}" out_port="out"/>
</pb_type>
<interconnect>
<direct name="a2a" input="mult_9x9_slice.A_cfg" output="mult_9x9.a">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_9x9_slice.A_cfg" out_port="mult_9x9.a"/>
<C_constant C="1.89e-13" in_port="mult_9x9_slice.A_cfg" out_port="mult_9x9.a"/>
</direct>
<direct name="b2b" input="mult_9x9_slice.B_cfg" output="mult_9x9.b">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_9x9_slice.B_cfg" out_port="mult_9x9.b"/>
<C_constant C="1.89e-13" in_port="mult_9x9_slice.B_cfg" out_port="mult_9x9.b"/>
</direct>
<direct name="out2out" input="mult_9x9.out" output="mult_9x9_slice.OUT_cfg">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_9x9.out" out_port="mult_9x9_slice.OUT_cfg"/>
<C_constant C="1.89e-13" in_port="mult_9x9.out" out_port="mult_9x9_slice.OUT_cfg"/>
</direct>
</interconnect>
</pb_type>
<interconnect>
<direct name="a2a" input="divisible_mult_18x18.a" output="mult_9x9_slice[1:0].A_cfg">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="divisible_mult_18x18.a" out_port="mult_9x9_slice[1:0].A_cfg"/>
<C_constant C="1.89e-13" in_port="divisible_mult_18x18.a" out_port="mult_9x9_slice[1:0].A_cfg"/>
</direct>
<direct name="b2b" input="divisible_mult_18x18.b" output="mult_9x9_slice[1:0].B_cfg">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="divisible_mult_18x18.b" out_port="mult_9x9_slice[1:0].B_cfg"/>
<C_constant C="1.89e-13" in_port="divisible_mult_18x18.b" out_port="mult_9x9_slice[1:0].B_cfg"/>
</direct>
<direct name="out2out" input="mult_9x9_slice[1:0].OUT_cfg" output="divisible_mult_18x18.out">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_9x9_slice[1:0].OUT_cfg" out_port ="divisible_mult_18x18.out"/>
<C_constant C="1.89e-13" in_port="mult_9x9_slice[1:0].OUT_cfg" out_port="divisible_mult_18x18.out"/>
</direct>
</interconnect>
</mode>
<mode name="mult_18x18">
<pb_type name="mult_18x18_slice" num_pb="1">
<input name="A_cfg" num_pins="18"/>
<input name="B_cfg" num_pins="18"/>
<output name="OUT_cfg" num_pins="36"/>
<pb_type name="mult_18x18" blif_model=".subckt multiply" num_pb="1" area="1000">
<input name="a" num_pins="18"/>
<input name="b" num_pins="18"/>
<output name="out" num_pins="36"/>
<delay_constant max="2.03e-13" min="1.89e-13" in_port="{a b}" out_port="out"/>
</pb_type>
<interconnect>
<direct name="a2a" input="mult_18x18_slice.A_cfg" output="mult_18x18.a">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_18x18_slice.A_cfg" out_port="mult_18x18.a"/>
<C_constant C="1.89e-13" in_port="mult_18x18_slice.A_cfg" out_port="mult_18x18.a"/>
</direct>
<direct name="b2b" input="mult_18x18_slice.B_cfg" output="mult_18x18.b">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_18x18_slice.B_cfg" out_port="mult_18x18.b"/>
<C_constant C="1.89e-13" in_port="mult_18x18_slice.B_cfg" out_port="mult_18x18.b"/>
</direct>
<direct name="out2out" input="mult_18x18.out" output="mult_18x18_slice.OUT_cfg">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_18x18.out" out_port="mult_18x18_slice.OUT_cfg"/>
<C_constant C="1.89e-13" in_port="mult_18x18.out" out_port="mult_18x18_slice.OUT_cfg"/>
</direct>
</interconnect>
</pb_type>
<interconnect>
<direct name="a2a" input="divisible_mult_18x18.a" output="mult_18x18_slice.A_cfg">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="divisible_mult_18x18.a" out_port="mult_18x18_slice.A_cfg"/>
<C_constant C="1.89e-13" in_port="divisible_mult_18x18.a" out_port="mult_18x18_slice.A_cfg"/>
</direct>
<direct name="b2b" input="divisible_mult_18x18.b" output="mult_18x18_slice.B_cfg">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="divisible_mult_18x18.b" out_port="mult_18x18_slice.B_cfg"/>
<C_constant C="1.89e-13" in_port="divisible_mult_18x18.b" out_port="mult_18x18_slice.B_cfg"/>
</direct>
<direct name="out2out" input="mult_18x18_slice.OUT_cfg" output="divisible_mult_18x18.out">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_18x18_slice.OUT_cfg" out_port="divisible_mult_18x18.out"/>
<C_constant C="1.89e-13" in_port="mult_18x18_slice.OUT_cfg" out_port="divisible_mult_18x18.out"/>
</direct>
</interconnect>
</mode>
</pb_type>
<interconnect>
<direct name="a2a" input="mult_36.a" output="divisible_mult_18x18[1:0].a">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_36.a" out_port="divisible_mult_18x18[1:0].a"/>
<C_constant C="1.89e-13" in_port="mult_36.a" out_port="divisible_mult_18x18[1:0].a"/>
</direct>
<direct name="b2b" input="mult_36.b" output="divisible_mult_18x18[1:0].a">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_36.b" out_port="divisible_mult_18x18[1:0].a"/>
<C_constant C="1.89e-13" in_port="mult_36.b" out_port="divisible_mult_18x18[1:0].a"/>
</direct>
<direct name="out2out" input="divisible_mult_18x18[1:0].out" output="mult_36.out">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="divisible_mult_18x18[1:0].out" out_port ="mult_36.out"/>
<C_constant C="1.89e-13" in_port="divisible_mult_18x18[1:0].out" out_port="mult_36.out"/>
</direct>
</interconnect>
</mode>
<mode name="mult_36x36">
<pb_type name="mult_36x36_slice" num_pb="1">
<input name="A_cfg" num_pins="36"/>
<input name="B_cfg" num_pins="36"/>
<output name="OUT_cfg" num_pins="72"/>
<pb_type name="mult_36x36" blif_model=".subckt multiply" num_pb="1" area="4000">
<input name="a" num_pins="36"/>
<input name="b" num_pins="36"/>
<output name="out" num_pins="72"/>
<delay_constant max="2.03e-13" min="1.89e-13" in_port="{a b}" out_port="out"/>
</pb_type>
<interconnect>
<direct name="a2a" input="mult_36x36_slice.A_cfg" output="mult_36x36.a">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_36x36_slice.A_cfg" out_port="mult_36x36.a"/>
<C_constant C="1.89e-13" in_port="mult_36x36_slice.A_cfg" out_port="mult_36x36.a"/>
</direct>
<direct name="b2b" input="mult_36x36_slice.B_cfg" output="mult_36x36.b">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_36x36_slice.B_cfg" out_port="mult_36x36.b"/>
<C_constant C="1.89e-13" in_port="mult_36x36_slice.B_cfg" out_port="mult_36x36.b"/>
</direct>
<direct name="out2out" input="mult_36x36.out" output="mult_36x36_slice.OUT_cfg">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_36x36.out" out_port="mult_36x36_slice.OUT_cfg"/>
<C_constant C="1.89e-13" in_port="mult_36x36.out" out_port="mult_36x36_slice.OUT_cfg"/>
</direct>
</interconnect>
</pb_type>
<interconnect>
<direct name="a2a" input="mult_36.a" output="mult_36x36_slice.A_cfg">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_36.a" out_port="mult_36x36_slice.A_cfg"/>
<C_constant C="1.89e-13" in_port="mult_36.a" out_port="mult_36x36_slice.A_cfg"/>
</direct>
<direct name="b2b" input="mult_36.b" output="mult_36x36_slice.B_cfg">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_36.b" out_port="mult_36x36_slice.B_cfg"/>
<C_constant C="1.89e-13" in_port="mult_36.b" out_port="mult_36x36_slice.B_cfg"/>
</direct>
<direct name="out2out" input="mult_36x36_slice.OUT_cfg" output="mult_36.out">
<delay_constant max="2.03e-13" min="1.89e-13" in_port="mult_36x36_slice.OUT_cfg" out_port="mult_36.out"/>
<C_constant C="1.89e-13" in_port="mult_36x36_slice.OUT_cfg" out_port="mult_36.out"/>
</direct>
</interconnect>
</mode>
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
<pinlocations pattern="spread"/>
<gridlocations>
<loc type="col" start="4" repeat="5" priority="2"/>
</gridlocations>
</pb_type>
</complexblocklist>
</architecture>

815
vpr7_rram/libarchfpga/arch/sample_arch.xml Normal file
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<!--
Architecture based off Stratix IV
Use closest ifar architecture: K06 N10 45nm fc 0.15 area-delay optimized, scale to 40 nm using linear scaling
n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml
- because documentation sparser for soft logic (delays not in QUIP), harder to track down, not worth our time considering the level of accuracy is approximate
- delays multiplied by 40/45 to normalize for process difference between stratix 4 and 45 nm technology (called full scaling)
Use delay numbers off Altera device handbook:
http://www.altera.com/literature/hb/stratix-iv/stx4_5v1.pdf
http://www.altera.com/literature/hb/stratix-iv/stx4_siv51004.pdf
http://www.altera.com/literature/hb/stratix-iv/stx4_siv51003.pdf
multipliers at 600 MHz, no detail on 9x9 vs 36x36
- datasheets unclear
- claims 4 18x18 independant multipliers, following test indicates that this is not the case:
created 4 18x18 mulitpliers, logiclocked them to a single DSP block, compile
result - 2 18x18 multipliers got packed together, the other 2 got ejected out of the logiclock region without error
conclusion - just take the 600 MHz as is, and Quartus II logiclock hasn't fixed the bug that I've seen it do to registers when I worked at Altera (ie. eject without warning)
NOTE: Area numbers for hard blocks unknown!
-->
<architecture>
<!-- ODIN II specific config -->
<models>
<model name="multiply">
<input_ports>
<port name="a"/>
<port name="b"/>
</input_ports>
<output_ports>
<port name="out"/>
</output_ports>
</model>
<model name="single_port_ram">
<input_ports>
<port name="we"/> <!-- control -->
<port name="addr"/> <!-- address lines -->
<port name="data"/> <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
<port name="clk" is_clock="1"/> <!-- memories are often clocked -->
</input_ports>
<output_ports>
<port name="out"/> <!-- output can be broken down into smaller bit widths minimum size 1 -->
</output_ports>
</model>
<model name="dual_port_ram">
<input_ports>
<port name="we1"/> <!-- write enable -->
<port name="we2"/> <!-- write enable -->
<port name="addr1"/> <!-- address lines -->
<port name="addr2"/> <!-- address lines -->
<port name="data1"/> <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
<port name="data2"/> <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
<port name="clk" is_clock="1"/> <!-- memories are often clocked -->
</input_ports>
<output_ports>
<port name="out1"/> <!-- output can be broken down into smaller bit widths minimum size 1 -->
<port name="out2"/> <!-- output can be broken down into smaller bit widths minimum size 1 -->
</output_ports>
</model>
<!-- fake carry-chain example -->
<model name="alm">
<input_ports>
<port name="in"/>
<port name="cin"/>
</input_ports>
<output_ports>
<port name="out"/>
<port name="cout"/>
</output_ports>
</model>
<model name="adder">
<input_ports>
<port name="a"/>
<port name="b"/>
<port name="cin"/>
</input_ports>
<output_ports>
<port name="cout"/>
<port name="sumout"/>
</output_ports>
</model>
<!--
<model name="sub">
<input_ports>
<port name="a"/>
<port name="b"/>
<port name="cin"/>
</input_ports>
<output_ports>
<port name="cout"/>
<port name="sumout"/>
</output_ports>
</model>
-->
</models>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin (area optimized for N8-K6-L4 -->
<layout auto="1.0"/>
<device>
<sizing R_minW_nmos="6065.520020" R_minW_pmos="18138.500000" ipin_mux_trans_size="1.222260"/>
<timing C_ipin_cblock="0.000000e+00" T_ipin_cblock="7.247000e-11"/>
<area grid_logic_tile_area="14813.392"/>
<chan_width_distr>
<io width="1.000000"/>
<x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/>
</chan_width_distr>
<switch_block type="wilton" fs="3"/>
</device>
<switchlist>
<switch type="mux" name="0" R="0.000000" Cin="0.000000e+00" Cout="0.000000e+00" Tdel="6.837e-11" mux_trans_size="2.630740" buf_size="27.645901"/>
</switchlist>
<segmentlist>
<segment freq="1.000000" length="4" type="unidir" Rmetal="0.000000" Cmetal="0.000000e+00">
<mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
</segment>
</segmentlist>
<complexblocklist>
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<pb_type name="io" capacity="8">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<clock name="clock" num_pins="1"/>
<!-- IOs can operate as either inputs or outputs -->
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
</interconnect>
</mode>
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
<!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-->
<pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad io.clock</loc>
<loc side="top">io.outpad io.inpad io.clock</loc>
<loc side="right">io.outpad io.inpad io.clock</loc>
<loc side="bottom">io.outpad io.inpad io.clock</loc>
</pinlocations>
<gridlocations>
<loc type="perimeter" priority="10"/>
</gridlocations>
</pb_type>
<pb_type name="clb">
<input name="I" num_pins="33" equivalent="true"/>
<output name="O" num_pins="10" equivalent="false"/>
<clock name="clk" num_pins="1"/>
<!-- Describe basic logic element, with ifar delay numbers -->
<pb_type name="ble" num_pb="10">
<input name="in" num_pins="6"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<pb_type name="soft_logic" num_pb="1">
<input name="in" num_pins="6"/>
<output name="out" num_pins="1"/>
<mode name="n1_lut6">
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="6" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
2.690e-10
2.690e-10
2.690e-10
2.690e-10
2.690e-10
2.690e-10
</delay_matrix>
</pb_type>
<interconnect>
<direct name="direct1" input="soft_logic.in[5:0]" output="lut6[0:0].in[5:0]"/>
<direct name="direct2" input="lut6[0:0].out" output="soft_logic.out[0:0]">
<!-- CAD related parameters -->
<!-- Advanced "power-user" options: Describe connections that belong to forced pack blocks to give hints to the packer on what blocks to keep together
Assumes pattern nets must be single-fanout
-->
<pack_pattern name="ble" in_port="lut6[0:0].out" out_port="soft_logic.out[0:0]"/>
<!-- CAD related parameters -->
</direct>
</interconnect>
</mode>
</pb_type>
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="2.448e-10" port="ff.D" clock="clk"/>
<T_clock_to_Q max="7.732e-11" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<!-- Two ff, make ff available to only corresponding luts -->
<direct name="direct1" input="ble.in" output="soft_logic.in"/>
<direct name="direct2" input="soft_logic.out" output="ff.D">
<pack_pattern name="ble" in_port="soft_logic.out" out_port="ff.D"/>
</direct>
<direct name="direct4" input="ble.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q soft_logic.out" output="ble.out"/>
</interconnect>
</pb_type>
<interconnect>
<complete name="crossbar" input="clb.I ble[9:0].out" output="ble[9:0].in">
<delay_constant max="8.044000e-11" in_port="clb.I" out_port="ble[9:0].in" />
<delay_constant max="7.354000e-11" in_port="ble[9:0].out" out_port="ble[9:0].in" />
</complete>
<complete name="clks" input="clb.clk" output="ble[9:0].clk">
</complete>
<direct name="clbouts" input="ble[9:0].out" output="clb.O">
</direct>
</interconnect>
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
<pinlocations pattern="spread"/>
<gridlocations>
<loc type="fill" priority="1"/>
</gridlocations>
</pb_type>
<!-- This is the 36*36 uniform mult -->
<pb_type name="mult_36" height="4">
<input name="a" num_pins="36"/>
<input name="b" num_pins="36"/>
<output name="out" num_pins="72"/>
<mode name="two_divisible_mult_18x18">
<pb_type name="divisible_mult_18x18" num_pb="2">
<input name="a" num_pins="18"/>
<input name="b" num_pins="18"/>
<output name="out" num_pins="36"/>
<mode name="two_mult_9x9">
<pb_type name="mult_9x9_slice" num_pb="2">
<input name="A_cfg" num_pins="9"/>
<input name="B_cfg" num_pins="9"/>
<output name="OUT_cfg" num_pins="18"/>
<pb_type name="mult_9x9" blif_model=".subckt multiply" num_pb="1">
<input name="a" num_pins="9"/>
<input name="b" num_pins="9"/>
<output name="out" num_pins="18"/>
<delay_constant max="1.667e-9" in_port="mult_9x9.a" out_port="mult_9x9.out"/>
<delay_constant max="1.667e-9" in_port="mult_9x9.b" out_port="mult_9x9.out"/>
</pb_type>
<interconnect>
<direct name="a2a" input="mult_9x9_slice.A_cfg" output="mult_9x9.a">
</direct>
<direct name="b2b" input="mult_9x9_slice.B_cfg" output="mult_9x9.b">
</direct>
<direct name="out2out" input="mult_9x9.out" output="mult_9x9_slice.OUT_cfg">
</direct>
</interconnect>
</pb_type>
<interconnect>
<direct name="a2a" input="divisible_mult_18x18.a" output="mult_9x9_slice[1:0].A_cfg">
</direct>
<direct name="b2b" input="divisible_mult_18x18.b" output="mult_9x9_slice[1:0].B_cfg">
</direct>
<direct name="out2out" input="mult_9x9_slice[1:0].OUT_cfg" output="divisible_mult_18x18.out">
</direct>
</interconnect>
</mode>
<mode name="mult_18x18">
<pb_type name="mult_18x18_slice" num_pb="1">
<input name="A_cfg" num_pins="18"/>
<input name="B_cfg" num_pins="18"/>
<output name="OUT_cfg" num_pins="36"/>
<pb_type name="mult_18x18" blif_model=".subckt multiply" num_pb="1" >
<input name="a" num_pins="18"/>
<input name="b" num_pins="18"/>
<output name="out" num_pins="36"/>
<delay_constant max="1.667e-9" in_port="mult_18x18.a" out_port="mult_18x18.out"/>
<delay_constant max="1.667e-9" in_port="mult_18x18.b" out_port="mult_18x18.out"/>
</pb_type>
<interconnect>
<direct name="a2a" input="mult_18x18_slice.A_cfg" output="mult_18x18.a">
</direct>
<direct name="b2b" input="mult_18x18_slice.B_cfg" output="mult_18x18.b">
</direct>
<direct name="out2out" input="mult_18x18.out" output="mult_18x18_slice.OUT_cfg">
</direct>
</interconnect>
</pb_type>
<interconnect>
<direct name="a2a" input="divisible_mult_18x18.a" output="mult_18x18_slice.A_cfg">
</direct>
<direct name="b2b" input="divisible_mult_18x18.b" output="mult_18x18_slice.B_cfg">
</direct>
<direct name="out2out" input="mult_18x18_slice.OUT_cfg" output="divisible_mult_18x18.out">
</direct>
</interconnect>
</mode>
</pb_type>
<interconnect>
<direct name="a2a" input="mult_36.a" output="divisible_mult_18x18[1:0].a">
</direct>
<direct name="b2b" input="mult_36.b" output="divisible_mult_18x18[1:0].b">
</direct>
<direct name="out2out" input="divisible_mult_18x18[1:0].out" output="mult_36.out">
</direct>
</interconnect>
</mode>
<mode name="mult_36x36">
<pb_type name="mult_36x36_slice" num_pb="1">
<input name="A_cfg" num_pins="36"/>
<input name="B_cfg" num_pins="36"/>
<output name="OUT_cfg" num_pins="72"/>
<pb_type name="mult_36x36" blif_model=".subckt multiply" num_pb="1">
<input name="a" num_pins="36"/>
<input name="b" num_pins="36"/>
<output name="out" num_pins="72"/>
<delay_constant max="1.667e-9" in_port="mult_36x36.a" out_port="mult_36x36.out"/>
<delay_constant max="1.667e-9" in_port="mult_36x36.b" out_port="mult_36x36.out"/>
</pb_type>
<interconnect>
<direct name="a2a" input="mult_36x36_slice.A_cfg" output="mult_36x36.a">
</direct>
<direct name="b2b" input="mult_36x36_slice.B_cfg" output="mult_36x36.b">
</direct>
<direct name="out2out" input="mult_36x36.out" output="mult_36x36_slice.OUT_cfg">
</direct>
</interconnect>
</pb_type>
<interconnect>
<direct name="a2a" input="mult_36.a" output="mult_36x36_slice.A_cfg">
</direct>
<direct name="b2b" input="mult_36.b" output="mult_36x36_slice.B_cfg">
</direct>
<direct name="out2out" input="mult_36x36_slice.OUT_cfg" output="mult_36.out">
</direct>
</interconnect>
</mode>
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
<pinlocations pattern="spread"/>
<gridlocations>
<loc type="col" start="4" repeat="8" priority="2"/>
</gridlocations>
</pb_type>
<!-- Memory based off Stratix IV 144K memory. Setup time set to match flip-flop setup time at 45 nm. Clock to q based off 144K max MHz -->
<pb_type name="memory" height="6">
<input name="addr1" num_pins="17"/>
<input name="addr2" num_pins="17"/>
<input name="data" num_pins="72"/>
<input name="we1" num_pins="1"/>
<input name="we2" num_pins="1"/>
<output name="out" num_pins="72"/>
<clock name="clk" num_pins="1"/>
<mode name="mem_2048x72_sp">
<pb_type name="mem_2048x72_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
<input name="addr" num_pins="11" port_class="address"/>
<input name="data" num_pins="72" port_class="data_in"/>
<input name="we" num_pins="1" port_class="write_en"/>
<output name="out" num_pins="72" port_class="data_out"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="2.448e-10" port="mem_2048x72_sp.addr" clock="clk"/>
<T_setup value="2.448e-10" port="mem_2048x72_sp.data" clock="clk"/>
<T_setup value="2.448e-10" port="mem_2048x72_sp.we" clock="clk"/>
<T_clock_to_Q max="1.852e-9" port="mem_2048x72_sp.out" clock="clk"/>
</pb_type>
<interconnect>
<direct name="address1" input="memory.addr1[10:0]" output="mem_2048x72_sp.addr">
</direct>
<direct name="data1" input="memory.data[71:0]" output="mem_2048x72_sp.data">
</direct>
<direct name="writeen1" input="memory.we1" output="mem_2048x72_sp.we">
</direct>
<direct name="dataout1" input="mem_2048x72_sp.out" output="memory.out[71:0]">
</direct>
<direct name="clk" input="memory.clk" output="mem_2048x72_sp.clk">
</direct>
</interconnect>
</mode>
<mode name="mem_4096x36_dp">
<pb_type name="mem_4096x36_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
<input name="addr1" num_pins="12" port_class="address1"/>
<input name="addr2" num_pins="12" port_class="address2"/>
<input name="data1" num_pins="36" port_class="data_in1"/>
<input name="data2" num_pins="36" port_class="data_in2"/>
<input name="we1" num_pins="1" port_class="write_en1"/>
<input name="we2" num_pins="1" port_class="write_en2"/>
<output name="out1" num_pins="36" port_class="data_out1"/>
<output name="out2" num_pins="36" port_class="data_out2"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="2.448e-10" port="mem_4096x36_dp.addr1" clock="clk"/>
<T_setup value="2.448e-10" port="mem_4096x36_dp.data1" clock="clk"/>
<T_setup value="2.448e-10" port="mem_4096x36_dp.we1" clock="clk"/>
<T_setup value="2.448e-10" port="mem_4096x36_dp.addr2" clock="clk"/>
<T_setup value="2.448e-10" port="mem_4096x36_dp.data2" clock="clk"/>
<T_setup value="2.448e-10" port="mem_4096x36_dp.we2" clock="clk"/>
<T_clock_to_Q max="1.852e-9" port="mem_4096x36_dp.out1" clock="clk"/>
<T_clock_to_Q max="1.852e-9" port="mem_4096x36_dp.out2" clock="clk"/>
</pb_type>
<interconnect>
<direct name="address1" input="memory.addr1[11:0]" output="mem_4096x36_dp.addr1">
</direct>
<direct name="address2" input="memory.addr2[11:0]" output="mem_4096x36_dp.addr2">
</direct>
<direct name="data1" input="memory.data[35:0]" output="mem_4096x36_dp.data1">
</direct>
<direct name="data2" input="memory.data[71:36]" output="mem_4096x36_dp.data2">
</direct>
<direct name="writeen1" input="memory.we1" output="mem_4096x36_dp.we1">
</direct>
<direct name="writeen2" input="memory.we2" output="mem_4096x36_dp.we2">
</direct>
<direct name="dataout1" input="mem_4096x36_dp.out1" output="memory.out[35:0]">
</direct>
<direct name="dataout2" input="mem_4096x36_dp.out2" output="memory.out[71:36]">
</direct>
<direct name="clk" input="memory.clk" output="mem_4096x36_dp.clk">
</direct>
</interconnect>
</mode>
<mode name="mem_4096x36_sp">
<pb_type name="mem_4096x36_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
<input name="addr" num_pins="12" port_class="address"/>
<input name="data" num_pins="36" port_class="data_in"/>
<input name="we" num_pins="1" port_class="write_en"/>
<output name="out" num_pins="36" port_class="data_out"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="2.448e-10" port="mem_4096x36_sp.addr" clock="clk"/>
<T_setup value="2.448e-10" port="mem_4096x36_sp.data" clock="clk"/>
<T_setup value="2.448e-10" port="mem_4096x36_sp.we" clock="clk"/>
<T_clock_to_Q max="1.852e-9" port="mem_4096x36_sp.out" clock="clk"/>
</pb_type>
<interconnect>
<direct name="address1" input="memory.addr1[11:0]" output="mem_4096x36_sp.addr">
</direct>
<direct name="data1" input="memory.data[35:0]" output="mem_4096x36_sp.data">
</direct>
<direct name="writeen1" input="memory.we1" output="mem_4096x36_sp.we">
</direct>
<direct name="dataout1" input="mem_4096x36_sp.out" output="memory.out[35:0]">
</direct>
<direct name="clk" input="memory.clk" output="mem_4096x36_sp.clk">
</direct>
</interconnect>
</mode>
<mode name="mem_9182x18_dp">
<pb_type name="mem_9182x18_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
<input name="addr1" num_pins="13" port_class="address1"/>
<input name="addr2" num_pins="13" port_class="address2"/>
<input name="data1" num_pins="18" port_class="data_in1"/>
<input name="data2" num_pins="18" port_class="data_in2"/>
<input name="we1" num_pins="1" port_class="write_en1"/>
<input name="we2" num_pins="1" port_class="write_en2"/>
<output name="out1" num_pins="18" port_class="data_out1"/>
<output name="out2" num_pins="18" port_class="data_out2"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="2.448e-10" port="mem_9182x18_dp.addr1" clock="clk"/>
<T_setup value="2.448e-10" port="mem_9182x18_dp.data1" clock="clk"/>
<T_setup value="2.448e-10" port="mem_9182x18_dp.we1" clock="clk"/>
<T_setup value="2.448e-10" port="mem_9182x18_dp.addr2" clock="clk"/>
<T_setup value="2.448e-10" port="mem_9182x18_dp.data2" clock="clk"/>
<T_setup value="2.448e-10" port="mem_9182x18_dp.we2" clock="clk"/>
<T_clock_to_Q max="1.852e-9" port="mem_9182x18_dp.out1" clock="clk"/>
<T_clock_to_Q max="1.852e-9" port="mem_9182x18_dp.out2" clock="clk"/>
</pb_type>
<interconnect>
<direct name="address1" input="memory.addr1[12:0]" output="mem_9182x18_dp.addr1">
</direct>
<direct name="address2" input="memory.addr2[12:0]" output="mem_9182x18_dp.addr2">
</direct>
<direct name="data1" input="memory.data[17:0]" output="mem_9182x18_dp.data1">
</direct>
<direct name="data2" input="memory.data[35:18]" output="mem_9182x18_dp.data2">
</direct>
<direct name="writeen1" input="memory.we1" output="mem_9182x18_dp.we1">
</direct>
<direct name="writeen2" input="memory.we2" output="mem_9182x18_dp.we2">
</direct>
<direct name="dataout1" input="mem_9182x18_dp.out1" output="memory.out[17:0]">
</direct>
<direct name="dataout2" input="mem_9182x18_dp.out2" output="memory.out[35:18]">
</direct>
<direct name="clk" input="memory.clk" output="mem_9182x18_dp.clk">
</direct>
</interconnect>
</mode>
<mode name="mem_9182x18_sp">
<pb_type name="mem_9182x18_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
<input name="addr" num_pins="13" port_class="address"/>
<input name="data" num_pins="18" port_class="data_in"/>
<input name="we" num_pins="1" port_class="write_en"/>
<output name="out" num_pins="18" port_class="data_out"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="2.448e-10" port="mem_9182x18_sp.addr" clock="clk"/>
<T_setup value="2.448e-10" port="mem_9182x18_sp.data" clock="clk"/>
<T_setup value="2.448e-10" port="mem_9182x18_sp.we" clock="clk"/>
<T_clock_to_Q max="1.852e-9" port="mem_9182x18_sp.out" clock="clk"/>
</pb_type>
<interconnect>
<direct name="address1" input="memory.addr1[12:0]" output="mem_9182x18_sp.addr">
</direct>
<direct name="data1" input="memory.data[17:0]" output="mem_9182x18_sp.data">
</direct>
<direct name="writeen1" input="memory.we1" output="mem_9182x18_sp.we">
</direct>
<direct name="dataout1" input="mem_9182x18_sp.out" output="memory.out[17:0]">
</direct>
<direct name="clk" input="memory.clk" output="mem_9182x18_sp.clk">
</direct>
</interconnect>
</mode>
<mode name="mem_18194x9_dp">
<pb_type name="mem_18194x9_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
<input name="addr1" num_pins="14" port_class="address1"/>
<input name="addr2" num_pins="14" port_class="address2"/>
<input name="data1" num_pins="9" port_class="data_in1"/>
<input name="data2" num_pins="9" port_class="data_in2"/>
<input name="we1" num_pins="1" port_class="write_en1"/>
<input name="we2" num_pins="1" port_class="write_en2"/>
<output name="out1" num_pins="9" port_class="data_out1"/>
<output name="out2" num_pins="9" port_class="data_out2"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="2.448e-10" port="mem_18194x9_dp.addr1" clock="clk"/>
<T_setup value="2.448e-10" port="mem_18194x9_dp.data1" clock="clk"/>
<T_setup value="2.448e-10" port="mem_18194x9_dp.we1" clock="clk"/>
<T_setup value="2.448e-10" port="mem_18194x9_dp.addr2" clock="clk"/>
<T_setup value="2.448e-10" port="mem_18194x9_dp.data2" clock="clk"/>
<T_setup value="2.448e-10" port="mem_18194x9_dp.we2" clock="clk"/>
<T_clock_to_Q max="1.852e-9" port="mem_18194x9_dp.out1" clock="clk"/>
<T_clock_to_Q max="1.852e-9" port="mem_18194x9_dp.out2" clock="clk"/>
</pb_type>
<interconnect>
<direct name="address1" input="memory.addr1[13:0]" output="mem_18194x9_dp.addr1">
</direct>
<direct name="address2" input="memory.addr2[13:0]" output="mem_18194x9_dp.addr2">
</direct>
<direct name="data1" input="memory.data[8:0]" output="mem_18194x9_dp.data1">
</direct>
<direct name="data2" input="memory.data[17:9]" output="mem_18194x9_dp.data2">
</direct>
<direct name="writeen1" input="memory.we1" output="mem_18194x9_dp.we1">
</direct>
<direct name="writeen2" input="memory.we2" output="mem_18194x9_dp.we2">
</direct>
<direct name="dataout1" input="mem_18194x9_dp.out1" output="memory.out[8:0]">
</direct>
<direct name="dataout2" input="mem_18194x9_dp.out2" output="memory.out[17:9]">
</direct>
<direct name="clk" input="memory.clk" output="mem_18194x9_dp.clk">
</direct>
</interconnect>
</mode>
<mode name="mem_18194x9_sp">
<pb_type name="mem_18194x9_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
<input name="addr" num_pins="14" port_class="address"/>
<input name="data" num_pins="9" port_class="data_in"/>
<input name="we" num_pins="1" port_class="write_en"/>
<output name="out" num_pins="9" port_class="data_out"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="2.448e-10" port="mem_18194x9_sp.addr" clock="clk"/>
<T_setup value="2.448e-10" port="mem_18194x9_sp.data" clock="clk"/>
<T_setup value="2.448e-10" port="mem_18194x9_sp.we" clock="clk"/>
<T_clock_to_Q max="1.852e-9" port="mem_18194x9_sp.out" clock="clk"/>
</pb_type>
<interconnect>
<direct name="address1" input="memory.addr1[13:0]" output="mem_18194x9_sp.addr">
</direct>
<direct name="data1" input="memory.data[8:0]" output="mem_18194x9_sp.data">
</direct>
<direct name="writeen1" input="memory.we1" output="mem_18194x9_sp.we">
</direct>
<direct name="dataout1" input="mem_18194x9_sp.out" output="memory.out[8:0]">
</direct>
<direct name="clk" input="memory.clk" output="mem_18194x9_sp.clk">
</direct>
</interconnect>
</mode>
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
<pinlocations pattern="spread"/>
<gridlocations>
<loc type="col" start="2" repeat="8" priority="2"/>
</gridlocations>
</pb_type>
<!-- fake carry-chain example -->
<pb_type name="carry_chain_example">
<input name="I" num_pins="15" equivalent="true"/>
<input name="cin" num_pins="1"/>
<output name="O" num_pins="4" equivalent="false"/>
<output name="cout" num_pins="1" equivalent="false"/>
<clock name="clk" num_pins="1"/>
<!-- Describe basic logic element, with ifar delay numbers -->
<pb_type name="ble" num_pb="4">
<input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/>
<output name="out" num_pins="1"/>
<output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<pb_type name="alm" blif_model=".subckt alm" num_pb="1">
<input name="in" num_pins="6"/>
<input name="cin" num_pins="1" chain="carry_chain_alm"/>
<output name="out" num_pins="1"/>
<output name="cout" num_pins="1" chain="carry_chain_alm"/>
<!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="alm.in" out_port="alm.out">
2.690e-10
2.690e-10
2.690e-10
2.690e-10
2.690e-10
2.690e-10
</delay_matrix>
<!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="alm.cin" out_port="alm.out">
2.690e-10
</delay_matrix>
<!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="alm.cin" out_port="alm.cout">
1.690e-10
</delay_matrix>
</pb_type>
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="2.448e-10" port="ff.D" clock="clk"/>
<T_clock_to_Q max="7.732e-11" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<!-- Two ff, make ff available to only corresponding luts -->
<complete name="complete1" input="ble.in" output="alm.in ff.D"/>
<direct name="direct4" input="ble.clk" output="ff.clk"/>
<direct name="direct5" input="ble.cin" output="alm.cin"/>
<direct name="direct6" input="alm.cout" output="ble.cout"/>
<mux name="mux1" input="ff.Q alm.out" output="ble.out"/>
</interconnect>
</pb_type>
<interconnect>
<complete name="crossbar" input="carry_chain_example.I ble[3:0].out" output="ble[3:0].in">
<delay_constant max="8.044000e-11" in_port="carry_chain_example.I" out_port="ble[3:0].in" />
<delay_constant max="7.354000e-11" in_port="ble[3:0].out" out_port="ble[3:0].in" />
</complete>
<complete name="clks" input="carry_chain_example.clk" output="ble[3:0].clk">
</complete>
<direct name="clbouts" input="ble[3:0].out" output="carry_chain_example.O">
</direct>
<direct name="carry1" input="ble[0:0].cout" output="ble[1:1].cin"/>
<direct name="carry2" input="ble[1:1].cout" output="ble[2:2].cin"/>
<direct name="carry3" input="ble[2:2].cout" output="ble[3:3].cin"/>
<direct name="carry4" input="ble[3:3].cout" output="carry_chain_example.cout"/>
</interconnect>
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
<pinlocations pattern="spread"/>
<gridlocations>
<loc type="col" start="7" repeat="50" priority="7"/>
</gridlocations>
</pb_type>
<!-- This is a basic ripple-carry adder primitive
We will take care of the carry chain for it later, for now, get something that goes through the flow so that Odin II can be tested
-->
<pb_type name="adder" height="1">
<input name="a" num_pins="4"/>
<input name="b" num_pins="4"/>
<input name="cin" num_pins="1"/>
<output name="cout" num_pins="1"/>
<output name="sumout" num_pins="4"/>
<mode name="sample_adder">
<pb_type name="sample_adder" blif_model=".subckt adder" num_pb="1">
<input name="a" num_pins="4"/>
<input name="b" num_pins="4"/>
<input name="cin" num_pins="1"/>
<output name="cout" num_pins="1"/>
<output name="sumout" num_pins="4"/>
<delay_constant max="1.667e-9" in_port="sample_adder.a" out_port="sample_adder.cout"/>
<delay_constant max="1.667e-9" in_port="sample_adder.b" out_port="sample_adder.cout"/>
<delay_constant max="1.667e-9" in_port="sample_adder.cin" out_port="sample_adder.cout"/>
<delay_constant max="1.667e-9" in_port="sample_adder.a" out_port="sample_adder.sumout"/>
<delay_constant max="1.667e-9" in_port="sample_adder.b" out_port="sample_adder.sumout"/>
<delay_constant max="1.667e-9" in_port="sample_adder.cin" out_port="sample_adder.sumout"/>
</pb_type>
<interconnect>
<direct name="a2a" input="adder.a" output="sample_adder.a">
</direct>
<direct name="b2b" input="adder.b" output="sample_adder.b">
</direct>
<direct name="c2c" input="adder.cin" output="sample_adder.cin">
</direct>
<direct name="cout" input="sample_adder.cout" output="adder.cout">
</direct>
<direct name="sumout" input="sample_adder.sumout" output="adder.sumout">
</direct>
</interconnect>
</mode>
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
<pinlocations pattern="spread"/>
<gridlocations>
<loc type="col" start="2" repeat="13" priority="10"/>
</gridlocations>
</pb_type>
<!--
<pb_type name="sub" height="1">
<input name="a" num_pins="4"/>
<input name="b" num_pins="4"/>
<input name="cin" num_pins="1"/>
<output name="cout" num_pins="1"/>
<output name="sumout" num_pins="4"/>
<mode name="sample_sub">
<pb_type name="sample_sub" blif_model=".subckt sub" num_pb="1">
<input name="a" num_pins="4"/>
<input name="b" num_pins="4"/>
<input name="cin" num_pins="1"/>
<output name="cout" num_pins="1"/>
<output name="sumout" num_pins="4"/>
<delay_constant max="1.667e-9" in_port="sample_sub.a" out_port="sample_sub.cout"/>
<delay_constant max="1.667e-9" in_port="sample_sub.b" out_port="sample_sub.cout"/>
<delay_constant max="1.667e-9" in_port="sample_sub.cin" out_port="sample_sub.cout"/>
<delay_constant max="1.667e-9" in_port="sample_sub.a" out_port="sample_sub.sumout"/>
<delay_constant max="1.667e-9" in_port="sample_sub.b" out_port="sample_sub.sumout"/>
<delay_constant max="1.667e-9" in_port="sample_sub.cin" out_port="sample_sub.sumout"/>
</pb_type>
<interconnect>
<direct name="a2a" input="sub.a" output="sample_sub.a">
</direct>
<direct name="b2b" input="sub.b" output="sample_sub.b">
</direct>
<direct name="c2c" input="sub.cin" output="sample_sub.cin">
</direct>
<direct name="cout" input="sample_sub.cout" output="sub.cout">
</direct>
<direct name="sumout" input="sample_sub.sumout" output="sub.sumout">
</direct>
</interconnect>
</mode>
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
<pinlocations pattern="spread"/>
<gridlocations>
<loc type="col" start="2" repeat="13" priority="10"/>
</gridlocations>
</pb_type>
-->
</complexblocklist>
</architecture>

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<config>
<verilog_files>
<!-- Way of specifying multiple files in a project -->
<verilog_file>multiply72.v</verilog_file>
</verilog_files>
<output>
<!-- These are the output flags for the project -->
<output_type>blif_all_soft</output_type>
<output_path_and_name>./multiply72.blif</output_path_and_name>
<target>
<!-- This is the target device the output is being built for -->
<arch_file>fpga_arch_models.xml</arch_file>
</target>
</output>
<optimizations>
<!-- Options for hard multipliers: -->
<!-- if size <= min then soft logic used -->
<!-- if fixed == 1 then mults expanded to fixed hard block size -->
<multiply min="3" fixed="1"/>
</optimizations>
<debug_outputs>
<!-- Various debug options -->
<debug_output_path>.</debug_output_path>
<output_ast_graphs>1</output_ast_graphs>
<output_netlist_graphs>1</output_netlist_graphs>
</debug_outputs>
</config>

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ctags ./*.c ./*.h ./include/*.h

1285
vpr7_rram/libarchfpga/ezxml.c Normal file
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#ifndef LINKEDLIST_H
#define LINKEDLIST_H
/*General Purpose Linked List*/
typedef struct s_llist t_llist;
struct s_llist
{
void* dptr;
t_llist* next;
};
/***** Subroutines *****/
t_llist* create_llist(int len);
t_llist* insert_llist_node(t_llist* cur);
t_llist* insert_llist_node_before_head(t_llist* old_head);
void remove_llist_node(t_llist* cur);
t_llist* cat_llists(t_llist* head1,
t_llist* head2);
t_llist* search_llist_tail(t_llist* head);
int find_length_llist(t_llist* head);
void free_llist(t_llist* head);
t_llist* reverse_llist(t_llist* head);
#endif

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/* Xifan TANG: Spice Support*/
void ProcessSpiceSRAM(INOUTP ezxml_t Node, OUTP struct s_arch* arch);
void ProcessSpiceSettings(ezxml_t Parent,
t_spice* spice);

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/* Declaration of Subroutines */
void my_free(void* ptr);
void InitSpiceMeasParams(t_spice_meas_params* meas_params);
void FreeSpiceMeasParams(t_spice_meas_params* meas_params);
void InitSpiceStimulateParams(t_spice_stimulate_params* stimulate_params);
void FreeSpiceStimulateParams(t_spice_stimulate_params* stimulate_params);
void InitSpiceParams(t_spice_params* spice_params);
void FreeSpiceParams(t_spice_params* params);
void FreeSpiceModelNetlist(t_spice_model_netlist* spice_model_netlist);
void FreeSpiceModelBuffer(t_spice_model_buffer* spice_model_buffer);
void FreeSpiceModelPassGateLogic(t_spice_model_pass_gate_logic* spice_model_pass_gate_logic);
void FreeSpiceModelPort(t_spice_model_port* spice_model_port);
void FreeSpiceModelWireParam(t_spice_model_wire_param* spice_model_wire_param);
void FreeSpiceModel(t_spice_model* spice_model);
void InitSpice(t_spice* spice);
void FreeSpice(t_spice* spice);
void FreeSpiceMuxArch(t_spice_mux_arch* spice_mux_arch);
void FreeSramInf(t_sram_inf* sram_inf);

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vpr7_rram/libarchfpga/fpga_spice_include/spice_types.h Normal file
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#include "util.h"
#include "linkedlist.h"
/* Xifan TANG: Spice support*/
enum e_spice_tech_lib_type {
SPICE_LIB_INDUSTRY,SPICE_LIB_ACADEMIA
};
/*Struct for a SPICE model of a module*/
enum e_spice_model_type {
SPICE_MODEL_CHAN_WIRE,
SPICE_MODEL_WIRE,
SPICE_MODEL_MUX,
SPICE_MODEL_LUT,
SPICE_MODEL_FF,
SPICE_MODEL_SRAM,
SPICE_MODEL_HARDLOGIC,
SPICE_MODEL_SCFF,
SPICE_MODEL_IOPAD,
SPICE_MODEL_VDD,
SPICE_MODEL_GND,
SPICE_MODEL_INVBUF,
SPICE_MODEL_PASSGATE
};
enum e_spice_model_design_tech {
SPICE_MODEL_DESIGN_CMOS,
SPICE_MODEL_DESIGN_RRAM
};
enum e_spice_model_structure {
SPICE_MODEL_STRUCTURE_TREE,
SPICE_MODEL_STRUCTURE_ONELEVEL,
SPICE_MODEL_STRUCTURE_MULTILEVEL,
SPICE_MODEL_STRUCTURE_CROSSBAR
};
enum e_spice_model_buffer_type {
SPICE_MODEL_BUF_INV,
SPICE_MODEL_BUF_BUF
};
enum e_spice_model_pass_gate_logic_type {
SPICE_MODEL_PASS_GATE_TRANSMISSION, SPICE_MODEL_PASS_GATE_TRANSISTOR
};
/* Transistor-level basic informations*/
enum e_spice_trans_type {
SPICE_TRANS_NMOS, SPICE_TRANS_PMOS, SPICE_TRANS_IO_NMOS, SPICE_TRANS_IO_PMOS
};
enum e_wire_model_type {
WIRE_MODEL_PIE,
WIRE_MODEL_T
};
enum e_spice_model_port_type {
SPICE_MODEL_PORT_INPUT,
SPICE_MODEL_PORT_OUTPUT,
SPICE_MODEL_PORT_INOUT,
SPICE_MODEL_PORT_CLOCK,
SPICE_MODEL_PORT_SRAM,
SPICE_MODEL_PORT_BL,
SPICE_MODEL_PORT_BLB,
SPICE_MODEL_PORT_WL,
SPICE_MODEL_PORT_WLB
};
/* For SRAM */
enum e_sram_orgz {
SPICE_SRAM_STANDALONE,
SPICE_SRAM_SCAN_CHAIN,
SPICE_SRAM_MEMORY_BANK
};
enum e_spice_accuracy_type {
SPICE_FRAC, SPICE_ABS
};
/* typedef of structs */
typedef struct s_spice_transistor_type t_spice_transistor_type;
typedef struct s_spice_tech_lib t_spice_tech_lib;
typedef struct s_spice_model_buffer t_spice_model_buffer;
typedef struct s_spice_model_pass_gate_logic t_spice_model_pass_gate_logic;
typedef struct s_spice_model_port t_spice_model_port;
typedef struct s_spice_model_wire_param t_spice_model_wire_param;
typedef struct s_spice_model_netlist t_spice_model_netlist;
typedef struct s_spice_model_design_tech_info t_spice_model_design_tech_info;
typedef struct s_spice_model t_spice_model;
typedef struct s_spice_meas_params t_spice_meas_params;
typedef struct s_spice_stimulate_params t_spice_stimulate_params;
typedef struct s_spice_mc_variation_params t_spice_mc_variation_params;
typedef struct s_spice_mc_params t_spice_mc_params;
typedef struct s_spice_params t_spice_params;
typedef struct s_spice t_spice;
typedef struct s_spice_mux_arch t_spice_mux_arch;
typedef struct s_spice_mux_model t_spice_mux_model;
typedef struct s_sram_inf t_sram_inf;
typedef struct s_sram_inf_orgz t_sram_inf_orgz;
typedef struct s_spice_net_info t_spice_net_info;
typedef struct s_spicetb_info t_spicetb_info;
typedef struct s_conf_bit_info t_conf_bit_info;
typedef struct s_sram_orgz_info t_sram_orgz_info;
/* Struct defintions */
struct s_spice_transistor_type {
enum e_spice_trans_type type;
char* model_name;
float chan_length;
float min_width;
};
/* Properites for technology library*/
struct s_spice_tech_lib {
enum e_spice_tech_lib_type type;
char* transistor_type;
char* path;
float nominal_vdd;
float io_vdd;
float pn_ratio;
char* model_ref;
int num_transistor_type;
t_spice_transistor_type* transistor_types;
};
struct s_spice_model_buffer {
int exist;
enum e_spice_model_buffer_type type;
float size;
int tapered_buf; /*Valid only when this is a buffer*/
int tap_buf_level;
int f_per_stage;
char* spice_model_name;
t_spice_model* spice_model;
};
struct s_spice_model_pass_gate_logic {
enum e_spice_model_pass_gate_logic_type type;
float nmos_size;
float pmos_size;
char* spice_model_name;
t_spice_model* spice_model;
};
struct s_spice_model_port {
enum e_spice_model_port_type type;
int size;
char* prefix;
boolean mode_select;
int default_val;
boolean is_global;
boolean is_reset;
boolean is_set;
boolean is_config_enable;
boolean is_prog;
char* spice_model_name;
t_spice_model* spice_model;
char* inv_spice_model_name;
t_spice_model* inv_spice_model;
};
struct s_spice_model_wire_param {
enum e_wire_model_type type;
float res_val;
float cap_val;
int level;
};
struct s_spice_model_netlist {
char* path;
int included;
};
/* Information about design technology */
struct s_spice_model_design_tech_info {
/* Valid for SRAM technology */
t_spice_model_buffer* buffer_info;
t_spice_model_pass_gate_logic* pass_gate_info;
/* Vaild for RRAM technology only, and this is a mux*/
float ron;
float roff;
float wprog_set_nmos;
float wprog_set_pmos;
float wprog_reset_nmos;
float wprog_reset_pmos;
/* Mux information only */
enum e_spice_model_structure structure;
int mux_num_level;
/* Power gate information */
boolean power_gated;
boolean advanced_rram_design;
};
struct s_spice_model {
enum e_spice_model_type type;
char* name;
char* prefix; /* Prefix when it show up in the spice netlist */
char* model_netlist; /* SPICE netlist provided by user */
char* verilog_netlist; /* Verilog netlist provided by user */
t_spice_model_netlist* include_netlist;
int is_default;
boolean dump_structural_verilog;
/* type */
enum e_spice_model_design_tech design_tech;
t_spice_model_design_tech_info design_tech_info;
/* END*/
/* buffering information */
t_spice_model_buffer* lut_input_buffer;
t_spice_model_buffer* input_buffer;
t_spice_model_buffer* output_buffer;
t_spice_model_pass_gate_logic* pass_gate_logic;
/* Ports*/
int num_port;
t_spice_model_port* ports;
/* Wire Model*/
t_spice_model_wire_param* wire_param;
/* Counter for print spice netlist*/
int cnt;
int tb_cnt;
/* Grid index counter */
int** grid_index_low;
int** grid_index_high;
/* CBX index counter */
int** cbx_index_low;
int** cbx_index_high;
/* CBY index counter */
int** cby_index_low;
int** cby_index_high;
/* SB index counter */
int** sb_index_low;
int** sb_index_high;
};
struct s_spice_meas_params {
int auto_select_sim_num_clk_cycle;
int sim_num_clock_cycle; /* Number of clock cycle in simulation */
float accuracy;
enum e_spice_accuracy_type accuracy_type;
/* Upper/Lower threshold voltage for measuring slew (unit: percentage)*/
/* Rising edge */
float slew_upper_thres_pct_rise;
float slew_lower_thres_pct_rise;
/* Falling edge */
float slew_upper_thres_pct_fall;
float slew_lower_thres_pct_fall;
/*Input/Output threshold voltage for measuring delay (unit: percentage) */
/* Rising edge */
float input_thres_pct_rise;
float output_thres_pct_rise;
/* Falling edge */
float input_thres_pct_fall;
float output_thres_pct_fall;
};
struct s_spice_stimulate_params {
/* Clock slew (unit: percentage of clock freqency) */
float clock_slew_rise_time;
float clock_slew_fall_time;
enum e_spice_accuracy_type clock_slew_rise_type;
enum e_spice_accuracy_type clock_slew_fall_type;
/* Input signal slew (unit: percentage of clock freqency) */
float input_slew_rise_time;
float input_slew_fall_time;
enum e_spice_accuracy_type input_slew_rise_type;
enum e_spice_accuracy_type input_slew_fall_type;
/* clock freqency: could be custimized or following the estimated critical path */
int num_clocks;
float vpr_crit_path_delay; /* Reference operation clock frequency */
float op_clock_freq; /* Operation clock frequency*/
float prog_clock_freq; /* Programming clock frequency, used during programming phase only */
/* Simulation Clock frequency slack: In this case, we follow the estimated critical path.
* For simulation, usually we use a slack that make sure the circuit can run... */
float sim_clock_freq_slack;
};
struct s_spice_mc_variation_params {
/* on/off, abs_variation and num_sigma */
boolean variation_on;
float abs_variation;
int num_sigma;
};
struct s_spice_mc_params {
boolean mc_sim;
int num_mc_points;
/* cmos and rram variation */
t_spice_mc_variation_params cmos_variation;
t_spice_mc_variation_params rram_variation;
t_spice_mc_variation_params wire_variation;
};
struct s_spice_params {
int sim_temp; /* Simulation Temperature*/
int post;
int captab;
int fast;
t_spice_meas_params meas_params;
t_spice_stimulate_params stimulate_params;
t_spice_mc_params mc_params;
};
struct s_spice {
/* Parameters */
t_spice_params spice_params;
/* Included SPICE netlists */
int num_include_netlist;
t_spice_model_netlist* include_netlists;
/* Technical Library*/
t_spice_tech_lib tech_lib;
int num_spice_model;
t_spice_model* spice_models;
};
/* Information needed to build a Multiplexer architecture*/
struct s_spice_mux_arch {
enum e_spice_model_structure structure;
int num_input;
int num_level;
int num_input_basis;
int num_input_last_level;
int* num_input_per_level; /* [0...num_level] */
int* input_level; /* [0...num_input] */
int* input_offset; /* [0...num_input] */
};
/* For Multiplexer size*/
struct s_spice_mux_model {
int size;
t_spice_model* spice_model;
t_spice_mux_arch* spice_mux_arch;
int cnt; /* Used in mux_testbench only*/
};
struct s_sram_inf_orgz {
char* spice_model_name; // Xifan TANG: Spice Support
t_spice_model* spice_model; // Xifan TANG: Spice Support
enum e_sram_orgz type;
};
struct s_sram_inf {
float area; //Xifan TANG
t_sram_inf_orgz* verilog_sram_inf_orgz;
t_sram_inf_orgz* spice_sram_inf_orgz;
};
/* Xifan TANG: SPICE net information */
struct s_spice_net_info {
float probability;
float density;
/* The following paramters can be calculated by the above properties*/
int init_val;
float freq;
float pwl;
float pwh;
float slew_rise;
float slew_fall;
};
struct s_spicetb_info {
char* tb_name;
int num_sim_clock_cycles;
};
/* A struct containing a syntax_char that is reserved by Verilog or SPICE */
typedef struct s_reserved_syntax_char t_reserved_syntax_char;
struct s_reserved_syntax_char {
char syntax_char;
boolean verilog_reserved;
boolean spice_reserved;
};
/* A struct to contain Address and its value */
typedef struct s_conf_bit t_conf_bit;
struct s_conf_bit {
int addr; /* Address to write the value */
int val; /* binary value to be writtent: either 0 or 1 */
};
/* Data structure for storing configurtion bits*/
struct s_conf_bit_info {
/* index in all the srams/bit lines/word lines */
int index;
/* value stored in a SRAM*/
t_conf_bit* sram_bit;
/* If bl and wl is required, this is the value to be stored */
t_conf_bit* bl;
t_conf_bit* wl;
/* Which spice model this conf. bit belongs to */
t_spice_model* parent_spice_model;
int parent_spice_model_index;
/* index of this conf_bit in a top-level testbench */
int index_in_top_tb;
/* TODO: add location information?
* i.e. grid location? sb/cb location?
*/
};
/* Structs including information about SRAM organization:
* 1. Memory bank
* 2. Scan-chain FFs
* 3. Standalone SRAMs */
/* Memory bank information */
typedef struct s_mem_bank_info t_mem_bank_info;
struct s_mem_bank_info {
t_spice_model* mem_model; /* SPICE model of a memory bit */
int num_mem_bit; /* Number of memory bits in total */
int num_bl; /* Number of Bit Lines in total */
int num_wl; /* Number of Word Lines in total */
/* Reserved control lines always starts from index 0*/
int reserved_bl; /* Number of reserved BLs shared by overall RRAM circuits */
int reserved_wl; /* Number of reserved WLs shared by overall RRAM circuits */
};
/* Scan-chain Flip-flops information */
typedef struct s_scff_info t_scff_info;
struct s_scff_info {
t_spice_model* mem_model; /* SPICE model of a memory bit */
int num_mem_bit; /* Number of memory bits in total */
int num_scff; /* Number of Scan-chain flip-flops */
/* TODO: More to be added, SCFF support is naive now */
};
/* Standalone SRAMs information */
typedef struct s_standalone_sram_info t_standalone_sram_info;
struct s_standalone_sram_info {
t_spice_model* mem_model; /* SPICE model of a memory bit */
int num_mem_bit; /* Number of memory bits in total */
int num_sram; /* Number of SRAMs in total */
};
struct s_sram_orgz_info {
enum e_sram_orgz type;
t_mem_bank_info* mem_bank_info; /* Only be allocated when orgz type is memory bank */
t_scff_info* scff_info; /* Only be allocated when orgz type is scan-chain */
t_standalone_sram_info* standalone_sram_info; /* Only be allocated when orgz type is standalone */
/* Head of configuration bits,
* which is assigned according to orgz_type */
t_llist* conf_bit_head;
/* Conf bits information per grid */
int** grid_reserved_conf_bits;
int** grid_conf_bits_lsb;
int** grid_conf_bits_msb;
};
/* SPICE support end*/

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#ifndef READLINE_H
#define READLINE_H
#ifdef __cplusplus
extern "C" {
#endif
char **ReadLineTokens(INOUTP FILE * InFile, INOUTP int *LineNum);
int CountTokens(INP char **Tokens);
void FreeTokens(INOUTP char ***TokensPtr);
#ifdef __cplusplus
}
#endif
#endif

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/*
Data types describing the FPGA architecture.
Date: February 19, 2009
Authors: Jason Luu and Kenneth Kent
*/
#ifndef ARCH_TYPES_H
#define ARCH_TYPES_H
#include "logic_types.h"
#include "physical_types.h"
#include "cad_types.h"
/* Constant describing architecture library version number */
#define VPR_VERSION "7.0"
/* Input file parsing. */
#define TOKENS " \t\n"
/* Value for UNDEFINED data */
#define UNDEFINED -1
/* Maximum value for mininum channel width to avoid overflows of short data type. */
#define MAX_CHANNEL_WIDTH 8000
#endif

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/*mrFPGA specifications for read_xml_arch: Xifan TANG*/
/* mrFPGA : Reshaped by Xifan TANG*/
typedef struct s_buffer_inf t_buffer_inf;
struct s_buffer_inf {
float C;
float R;
float Tdel;
};
typedef struct s_memristor_inf t_memristor_inf;
struct s_memristor_inf {
float C;
float R;
float Tdel;
};
enum e_tech_comp {
CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM
};
/* end */
typedef struct s_arch_mrfpga t_arch_mrfpga;
struct s_arch_mrfpga {
boolean is_isolation;
boolean is_stack;
boolean is_junction;
boolean is_wire_buffer;
boolean is_mrFPGA;
boolean is_accurate;
t_buffer_inf wire_buffer_inf;
t_memristor_inf memristor_inf;
int max_pins_per_side;
t_linked_int* main_best_buffer_list;
short num_normal_switch;
short start_seg_switch;
/* show sram and pass transistor uasge*/
boolean is_show_sram;
boolean is_show_pass_trans;
enum e_tech_comp tech_comp;
float Rseg_global;
float Cseg_global;
float rram_pass_tran_value;
/* timing info to override the opin_to_wire connection block */
int is_opin_cblock_defined;
float R_opin_cblock;
float T_opin_cblock;
};

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/*
Data types used to give architectural hints for the CAD algorithm
*/
#ifndef CAD_TYPES_H
#define CAD_TYPES_H
#include "logic_types.h"
#include "physical_types.h"
#include "util.h"
struct s_pack_pattern_connections;
typedef struct s_pack_pattern_block {
int pattern_index; /* index of pattern that this block is a part of */
const t_pb_type *pb_type; /* pb_type that this block is an instance of */
struct s_pack_pattern_connections *connections; /* linked list of connections of logic blocks in pattern */
int block_id;
} t_pack_pattern_block;
/* Describes connections of s_pack_pattern_block */
typedef struct s_pack_pattern_connections {
t_pack_pattern_block *from_block;
t_pb_graph_pin *from_pin;
t_pack_pattern_block *to_block;
t_pb_graph_pin *to_pin;
struct s_pack_pattern_connections *next;
} t_pack_pattern_connections;
typedef struct s_pack_patterns {
char *name; /* name of this logic model pattern */
int index; /* array index for pattern*/
t_pack_pattern_block *root_block; /* root block used by this pattern */
float base_cost; /* base cost of pattern eg. If a group of logical blocks match a pattern of smaller primitives, that is better than the same group using bigger primitives */
int num_blocks; /* number of blocks in pattern */
boolean *is_block_optional; /* [0..num_blocks-1] is the block_id in this pattern mandatory or optional to form a molecule */
boolean is_chain; /* Does this pattern chain across logic blocks */
t_pb_graph_pin *chain_root_pin; /* pointer to logic block input pin that drives this chain from the preceding logic block */
} t_pack_patterns;
typedef struct s_model_chain_pattern {
char *name; /* name of this chain of logic */
t_model *model; /* block associated with chain */
t_model_ports *input_link_port; /* pointer to port of chain input */
int inport_link_pin; /* applicable pin of chain input port */
t_model_ports *output_link_port; /* pointer to port of chain output */
int outport_link_pin; /* applicable pin of chain output port */
struct s_model_chain_pattern *next; /* next chain (linked list) */
} t_model_chain_pattern;
/**
* Keeps track of locations that a primitive can go to during packing
* Linked list for easy insertion/deletion
*/
typedef struct s_cluster_placement_primitive {
t_pb_graph_node *pb_graph_node;
struct s_cluster_placement_primitive *next_primitive;
boolean valid;
float base_cost; /* cost independant of current status of packing */
float incremental_cost; /* cost dependant on current status of packing */
} t_cluster_placement_primitive;
#endif

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/* ezxml.h
*
* Copyright 2004-2006 Aaron Voisine <aaron@voisine.org>
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _EZXML_H
#define _EZXML_H
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#include <fcntl.h>
#ifdef __cplusplus
extern "C" {
#endif
#define EZXML_BUFSIZE 1024 /* size of internal memory buffers */
#define EZXML_NAMEM 0x80 /* name is malloced */
#define EZXML_TXTM 0x40 /* txt is malloced */
#define EZXML_DUP 0x20 /* attribute name and value are strduped */
#define EZXML_ERRL 128 /* maximum error string length */
typedef struct ezxml *ezxml_t;
struct ezxml {
char *name; /* tag name */
char **attr; /* tag attributes { name, value, name, value, ... NULL } */
char *txt; /* tag character content, empty string if none */
size_t off; /* tag offset from start of parent tag character content */
ezxml_t next; /* next tag with same name in this section at this depth */
ezxml_t sibling; /* next tag with different name in same section and depth */
ezxml_t ordered; /* next tag, same section and depth, in original order */
ezxml_t child; /* head of sub tag list, NULL if none */
ezxml_t parent; /* parent tag, NULL if current tag is root tag */
short flags; /* additional information */
/* Jason Luu June 22, 2010, Added line number support */
int line;
};
/* Jason Luu June 22, 2010, Moved root definition to header */
typedef struct ezxml_root *ezxml_root_t;
struct ezxml_root { /* additional data for the root tag */
struct ezxml xml; /* is a super-struct built on top of ezxml struct */
ezxml_t cur; /* current xml tree insertion point */
char *m; /* original xml string */
size_t len; /* length of allocated memory for mmap, -1 for malloc */
char *u; /* UTF-8 conversion of string if original was UTF-16 */
char *s; /* start of work area */
char *e; /* end of work area */
char **ent; /* general entities (ampersand sequences) */
char ***attr; /* default attributes */
char ***pi; /* processing instructions */
short standalone; /* non-zero if <?xml standalone="yes"?> */
char err[EZXML_ERRL]; /* error string */
};
/* Given a string of xml data and its length, parses it and creates an ezxml */
/* structure. For efficiency, modifies the data by adding null terminators */
/* and decoding ampersand sequences. If you don't want this, copy the data and */
/* pass in the copy. Returns NULL on failure. */
ezxml_t ezxml_parse_str(char *s, size_t len);
/* A wrapper for ezxml_parse_str() that accepts a file descriptor. First */
/* attempts to mem map the file. Failing that, reads the file into memory. */
/* Returns NULL on failure. */
ezxml_t ezxml_parse_fd(int fd);
/* a wrapper for ezxml_parse_fd() that accepts a file name */
ezxml_t ezxml_parse_file(const char *file);
/* Wrapper for ezxml_parse_str() that accepts a file stream. Reads the entire */
/* stream into memory and then parses it. For xml files, use ezxml_parse_file() */
/* or ezxml_parse_fd() */
ezxml_t ezxml_parse_fp(FILE * fp);
/* returns the first child tag (one level deeper) with the given name or NULL */
/* if not found */
ezxml_t ezxml_child(ezxml_t xml, const char *name);
/* returns the next tag of the same name in the same section and depth or NULL */
/* if not found */
#define ezxml_next(xml) ((xml) ? xml->next : NULL)
/* Returns the Nth tag with the same name in the same section at the same depth */
/* or NULL if not found. An index of 0 returns the tag given. */
ezxml_t ezxml_idx(ezxml_t xml, int idx);
/* returns the name of the given tag */
#define ezxml_name(xml) ((xml) ? xml->name : NULL)
/* returns the given tag's character content or empty string if none */
#define ezxml_txt(xml) ((xml) ? xml->txt : "")
/* returns the value of the requested tag attribute, or NULL if not found */
const char *ezxml_attr(ezxml_t xml, const char *attr);
/* Traverses the ezxml sturcture to retrieve a specific subtag. Takes a */
/* variable length list of tag names and indexes. The argument list must be */
/* terminated by either an index of -1 or an empty string tag name. Example: */
/* title = ezxml_get(library, "shelf", 0, "book", 2, "title", -1); */
/* This retrieves the title of the 3rd book on the 1st shelf of library. */
/* Returns NULL if not found. */
ezxml_t ezxml_get(ezxml_t xml, ...);
/* Converts an ezxml structure back to xml. Returns a string of xml data that */
/* must be freed. */
char *ezxml_toxml(ezxml_t xml);
/* returns a NULL terminated array of processing instructions for the given */
/* target */
char **ezxml_pi(ezxml_t xml, const char *target);
/* frees the memory allocated for an ezxml structure */
void ezxml_free(ezxml_t xml);
/* returns parser error message or empty string if none */
const char *ezxml_error(ezxml_t xml);
/* returns a new empty ezxml structure with the given root tag name */
ezxml_t ezxml_new(char *name);
/* wrapper for ezxml_new() that strdup()s name */
#define ezxml_new_d(name) ezxml_set_flag(ezxml_new(strdup(name)), EZXML_NAMEM)
/* Adds a child tag. off is the offset of the child tag relative to the start */
/* of the parent tag's character content. Returns the child tag. */
ezxml_t ezxml_add_child(ezxml_t xml, char *name, size_t off);
/* wrapper for ezxml_add_child() that strdup()s name */
#define ezxml_add_child_d(xml, name, off) \
ezxml_set_flag(ezxml_add_child(xml, strdup(name), off), EZXML_NAMEM)
/* sets the character content for the given tag and returns the tag */
ezxml_t ezxml_set_txt(ezxml_t xml, char *txt);
/* wrapper for ezxml_set_txt() that strdup()s txt */
#define ezxml_set_txt_d(xml, txt) \
ezxml_set_flag(ezxml_set_txt(xml, strdup(txt)), EZXML_TXTM)
/* Sets the given tag attribute or adds a new attribute if not found. A value */
/* of NULL will remove the specified attribute. Returns the tag given. */
ezxml_t ezxml_set_attr(ezxml_t xml, char *name, char *value);
/* Wrapper for ezxml_set_attr() that strdup()s name/value. Value cannot be NULL */
#define ezxml_set_attr_d(xml, name, value) \
ezxml_set_attr(ezxml_set_flag(xml, EZXML_DUP), strdup(name), strdup(value))
/* sets a flag for the given tag and returns the tag */
ezxml_t ezxml_set_flag(ezxml_t xml, short flag);
/* removes a tag along with its subtags without freeing its memory */
ezxml_t ezxml_cut(ezxml_t xml);
/* inserts an existing tag into an ezxml structure */
ezxml_t ezxml_insert(ezxml_t xml, ezxml_t dest, size_t off);
/* Moves an existing tag to become a subtag of dest at the given offset from */
/* the start of dest's character content. Returns the moved tag. */
#define ezxml_move(xml, dest, off) ezxml_insert(ezxml_cut(xml), dest, off)
/* removes a tag along with all its subtags */
#define ezxml_remove(xml) ezxml_free(ezxml_cut(xml))
#ifdef __cplusplus
}
#endif
#endif /* _EZXML_H */

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/*
Data types describing the logic (technology-mapped) models that the architecture can implement.
Logic models include LUT (.names), flipflop (.latch), inpad, outpad, memory slice, etc
Date: February 19, 2009
Authors: Jason Luu and Kenneth Kent
*/
#ifndef LOGIC_TYPES_H
#define LOGIC_TYPES_H
#include "util.h"
/*
Logic model data types
A logic model is described by its I/O ports and function name
*/
enum PORTS {
IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT
};
typedef struct s_model_ports {
enum PORTS dir; /* port direction */
char *name; /* name of this port */
int size; /* maximum number of pins */
int min_size; /* minimum number of pins */
boolean is_clock; /* clock? */
boolean is_non_clock_global; /* not a clock but is a special, global, control signal (eg global asynchronous reset, etc) */
struct s_model_ports *next; /* next port */
int index; /* indexing for array look-up */
} t_model_ports;
typedef struct s_model {
char *name; /* name of this logic model */
t_model_ports *inputs; /* linked list of input/clock ports */
t_model_ports *outputs; /* linked list of output ports */
void *instances;
int used;
struct s_linked_vptr *pb_types; /* Physical block types that implement this model */
struct s_model *next; /* next model (linked list) */
int index;
} t_model;
#endif

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/*
Data types describing the physical components on the FPGA architecture.
We assume an island style FPGA where complex logic blocks are arranged in a grid and each side of the logic block has access to the inter-block interconnect. To keep the logic blocks general,
we allow arbitrary hierarchy, modes, primitives, and interconnect within each complex logic block. The data structures here describe the properties of the island-style FPGA as well as the details on
hierarchy, modes, primitives, and intconnect within each logic block.
Data structures that flesh out
The data structures that store the
Key data types:
t_type_descriptor: describes a placeable complex logic block,
pb_type: describes the types of physical blocks within the t_type_descriptor in a hierarchy where the top block is the complex block and the leaf blocks implement one logical block
pb_graph_node: is a flattened version of pb_type so a pb_type with 10 instances will have 10 pb_graph_nodes representing each instance
Additional notes:
The interconnect specified in the architecture file gets flattened out in the pb_graph_node netlist. Each pb_graph_node contains pb_graph_pins which allow it to connect to other pb_graph_nodes.
These pins are in connected to other pins through pb_graph_edges. The pin connections are based on what is specified in the <interconnect> tags of the architecture file.
Date: February 19, 2009
Authors: Jason Luu and Kenneth Kent
*/
#ifndef PHYSICAL_TYPES_H
#define PHYSICAL_TYPES_H
#include "logic_types.h"
#include "util.h"
/* mrFPGA */
#include "arch_types_mrfpga.h"
/* END */
/* SPICE model Support: Xifan TANG*/
#include "spice_types.h"
/* END */
typedef struct s_clock_arch t_clock_arch;
typedef struct s_clock_network t_clock_network;
typedef struct s_power_arch t_power_arch;
typedef struct s_interconnect_pins t_interconnect_pins;
typedef struct s_power_usage t_power_usage;
typedef struct s_pb_type_power t_pb_type_power;
typedef struct s_mode_power t_mode_power;
typedef struct s_interconnect_power t_interconnect_power;
typedef struct s_port_power t_port_power;
typedef struct s_pb_graph_pin_power t_pb_graph_pin_power;
typedef struct s_mode t_mode;
typedef struct s_pb_graph_node_power t_pb_graph_node_power;
/*************************************************************************************************/
/* FPGA basic definitions */
/*************************************************************************************************/
/* Pins describe I/O into clustered logic block.
A pin may be unconnected, driving a net or in the fanout, respectively. */
enum e_pin_type {
OPEN = -1, DRIVER = 0, RECEIVER = 1
};
/* Type of interconnect within complex block: Complete for everything connected (full crossbar), direct for one-to-one connections, and mux for many-to-one connections */
enum e_interconnect {
COMPLETE_INTERC = 1, DIRECT_INTERC = 2, MUX_INTERC = 3
};
/* Orientations. */
enum e_side {
TOP = 0, RIGHT = 1, BOTTOM = 2, LEFT = 3
};
/* pin location distributions */
enum e_pin_location_distr {
E_SPREAD_PIN_DISTR = 1, E_CUSTOM_PIN_DISTR = 2
};
/* pb_type class */
enum e_pb_type_class {
UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3
};
/* Annotations for pin-to-pin connections */
enum e_pin_to_pin_annotation_type {
E_ANNOT_PIN_TO_PIN_DELAY = 0,
E_ANNOT_PIN_TO_PIN_CAPACITANCE,
E_ANNOT_PIN_TO_PIN_PACK_PATTERN,
/* Xifan TANG: FPGA-SPICE: mode selector */
E_ANNOT_PIN_TO_PIN_MODE_SELECT
};
enum e_pin_to_pin_annotation_format {
E_ANNOT_PIN_TO_PIN_MATRIX = 0, E_ANNOT_PIN_TO_PIN_CONSTANT
};
enum e_pin_to_pin_delay_annotations {
E_ANNOT_PIN_TO_PIN_DELAY_MIN = 0,
E_ANNOT_PIN_TO_PIN_DELAY_MAX,
E_ANNOT_PIN_TO_PIN_DELAY_TSETUP,
E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN,
E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX,
E_ANNOT_PIN_TO_PIN_DELAY_THOLD
};
enum e_pin_to_pin_capacitance_annotations {
E_ANNOT_PIN_TO_PIN_CAPACITANCE_C = 0
};
enum e_pin_to_pin_pack_pattern_annotations {
E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME = 0
};
/* Xifan TANG: FPGA-SPICE, mode select description */
enum e_pin_to_pin_mode_select_annotations {
E_ANNOT_PIN_TO_PIN_MODE_SELECT_MODE_NAME = 0
};
/* Power Estimation type for a PB */
enum e_power_estimation_method_ {
POWER_METHOD_UNDEFINED = 0, POWER_METHOD_IGNORE, /* Ignore power of this PB, and all children PB */
POWER_METHOD_SUM_OF_CHILDREN, /* Ignore power of this PB, but consider children */
POWER_METHOD_AUTO_SIZES, /* Transistor-level, auto-sized buffers/wires */
POWER_METHOD_SPECIFY_SIZES, /* Transistor-level, user-specified buffers/wires */
POWER_METHOD_TOGGLE_PINS, /* Dynamic: Energy per pin toggle, Static: Absolute */
POWER_METHOD_C_INTERNAL, /* Dynamic: Equiv. Internal capacitance, Static: Absolute */
POWER_METHOD_ABSOLUTE /* Dynamic: Aboslute, Static: Absolute */
};
typedef enum e_power_estimation_method_ e_power_estimation_method;
typedef enum e_power_estimation_method_ t_power_estimation_method;
/*************************************************************************************************/
/* FPGA grid layout data types */
/*************************************************************************************************/
/* Definition of how to place physical logic block in the grid
grid_loc_type - where the type goes and which numbers are valid
start_col - the absolute value of the starting column from the left to fill,
used with COL_REPEAT
repeat - the number of columns to skip before placing the same type,
used with COL_REPEAT. 0 means do not repeat
rel_col - the fractional column to place type
priority - in the event of conflict, which type gets picked?
*/
enum e_grid_loc_type {
BOUNDARY = 0, FILL, COL_REPEAT, COL_REL
};
typedef struct s_grid_loc_def {
enum e_grid_loc_type grid_loc_type;
int start_col;
int repeat;
float col_rel;
int priority;
} t_grid_loc_def;
/* Data type definitions */
/* Grid info */
struct s_clb_grid {
boolean IsAuto;
float Aspect;
int W;
int H;
};
/************************* POWER ***********************************/
/* Global clock architecture */
struct s_clock_arch {
int num_global_clocks;
t_clock_network *clock_inf; /* Details about each clock */
};
/* Architecture information for a single clock */
struct s_clock_network {
boolean autosize_buffer; /* autosize clock buffers */
float buffer_size; /* if not autosized, the clock buffer size */
float C_wire; /* Wire capacitance (per meter) */
float prob; /* Static probability of net assigned to this clock */
float dens; /* Switching density of net assigned to this clock */
float period; /* Period of clock */
};
/* Power-related architecture information */
struct s_power_arch {
float C_wire_local; /* Capacitance of local interconnect (per meter) */
//int seg_buffer_split; /* Split segment for distributed buffer (no split=1) */
float logical_effort_factor;
float local_interc_factor;
float transistors_per_SRAM_bit;
float mux_transistor_size;
float FF_size;
float LUT_transistor_size;
};
/* Power usage for an entity */
struct s_power_usage {
float dynamic;
float leakage;
};
/*************************************************************************************************/
/* FPGA Physical Logic Blocks data types */
/*************************************************************************************************/
/* A class of CLB pins that share common properties
* port_name: name of this class of pins
* type: DRIVER or RECEIVER (what is this pinclass?) *
* num_pins: The number of logically equivalent pins forming this *
* class. *
* pinlist[]: List of clb pin numbers which belong to this class. */
struct s_class {
enum e_pin_type type;
int num_pins;
int *pinlist; /* [0..num_pins - 1] */
};
typedef struct s_class t_class;
/* Cluster timing delays:
* C_ipin_cblock: Capacitance added to a routing track by the isolation *
* buffer between a track and the Cblocks at an (i,j) loc. *
* T_ipin_cblock: Delay through an input pin connection box (from a *
* routing track to a logic block input pin). */
typedef struct s_timing_inf {
boolean timing_analysis_enabled;
float C_ipin_cblock;
float T_ipin_cblock;
/* mrFPGA : Xifan TANG */
float R_opin_cblock;
float T_opin_cblock;
/* end */
char * SDCFile; /* only here for convenience of passing to path_delay.c */
} t_timing_inf;
struct s_pb_type;
/* declare before definition because pb_type contains modes and modes contain pb_types*/
/** Describes I/O and clock ports
* name: name of the port
* model_port: associated model port
* is_clock: whether or not this port is a clock
* is_non_clock_global: Applies to top level pb_type, this pin is not a clock but is a global signal (useful for stuff like global reset signals, perhaps useful for VCC and GND)
* num_pins: the number of pins this port has
* parent_pb_type: pointer to the parent pb_type
* port_class: port belongs to recognized set of ports in class library
* index: port index by index in array of parent pb_type
* port_index_by_type index of port by type (index by input, output, or clock)
* equivalence:
*/
struct s_port {
char* name;
t_model_ports *model_port;
enum PORTS type;
boolean is_clock;
boolean is_non_clock_global;
int num_pins;
boolean equivalent;
struct s_pb_type *parent_pb_type;
char * port_class;
int index;
int port_index_by_type;
char *chain_name;
t_port_power * port_power;
/* FPGA_SPICE_model support:
* mapped SPICE model port */
t_spice_model_port* spice_model_port;
};
typedef struct s_port t_port;
/**
* Info placed between pins that can be processed later for additional information
* value: value/property pair
* prop: value/property pair
* type: type of annotation
* format: formatting of data
* input_pins: input pins as string affected by annotation
* output_pins: output pins as string affected by annotation
* clock_pin: clock as string affected by annotation
*/
struct s_pin_to_pin_annotation {
char ** value; /* [0..num_value_prop_pairs - 1] */
int * prop; /* [0..num_value_prop_pairs - 1] */
int num_value_prop_pairs;
enum e_pin_to_pin_annotation_type type;
enum e_pin_to_pin_annotation_format format;
char * input_pins;
char * output_pins;
char * clock;
int line_num; /* used to report what line number this annotation is found in architecture file */
};
typedef struct s_pin_to_pin_annotation t_pin_to_pin_annotation;
struct s_pb_graph_edge;
/** Describes interconnect edge inside a cluster
* type: type of the interconnect
* name: indentifier for interconnect
* input_string: input string verbatim to parse later
* output_string: input string output to parse later
* annotations: Annotations for delay, power, etc
* num_annotations: Total number of annotations
* infer_annotations: This interconnect is autogenerated, if true,
infer pack_patterns such as carry-chains and forced packs based on interconnect linked to it
* parent_mode_index: Mode of parent as int
*/
struct s_interconnect {
enum e_interconnect type;
char *name;
char *input_string;
char *output_string;
t_pin_to_pin_annotation *annotations; /* [0..num_annotations-1] */
int num_annotations;
boolean infer_annotations;
int line_num; /* Interconnect is processed later, need to know what line number it messed up on to give proper error message */
int parent_mode_index;
/* Power related members */
t_mode * parent_mode;
/* Xifan TANG: SPICE Support*/
char* spice_model_name;
t_spice_model* spice_model;
int fan_in;
int fan_out;
int num_mux;
/* END */
t_interconnect_power * interconnect_power;
};
typedef struct s_interconnect t_interconnect;
struct s_interconnect_power {
t_power_usage power_usage;
/* These are not necessarily power-related; however, at the moment
* only power estimation uses them
*/
boolean port_info_initialized;
int num_input_ports;
int num_output_ports;
int num_pins_per_port;
float transistor_cnt;
};
struct s_interconnect_pins {
t_interconnect * interconnect;
struct s_pb_graph_pin *** input_pins; // [0..num_input_ports-1][0..num_pins_per_port-1]
struct s_pb_graph_pin *** output_pins; // [0..num_output_ports-1][0..num_pins_per_port-1]
};
/** Describes mode
* name: name of the mode
* pb_type_children: pb_types it contains
* interconnect: interconnect of parent pb_type to children pb_types or children to children pb_types
* num_interconnect: Total number of interconnect tags specified by user
* parent_pb_type: Which parent contains this mode
* index: Index of mode in array with other modes
*/
struct s_mode {
char* name;
struct s_pb_type *pb_type_children; /* [0..num_child_pb_types] */
int num_pb_type_children;
t_interconnect *interconnect;
int num_interconnect;
struct s_pb_type *parent_pb_type;
int index;
/* Spice Model Support: Xifan TANG
*/
int define_idle_mode;
int define_physical_mode;
int available_in_packing;
/* Power releated members */
t_mode_power * mode_power;
/* Xifan TANG: FPGA-SPICE and SynVerilog */
/* int default_mode_num_conf_bits; */
};
struct s_mode_power {
t_power_usage power_usage; /* Power usage of this mode */
};
/* Identify pb pin type for timing purposes */
enum e_pb_graph_pin_type {
PB_PIN_NORMAL = 0,
PB_PIN_SEQUENTIAL,
PB_PIN_INPAD,
PB_PIN_OUTPAD,
PB_PIN_TERMINAL,
PB_PIN_CLOCK
};
/** Describes a pb graph pin
* port: pointer to the port that this pin is associated with
* pin_number: pin number of the port that this pin is associated with
* input edges: [0..num_input_edges - 1]edges incoming
* num_input_edges: number edges incoming
* output edges: [0..num_output_edges - 1]edges out_going
* num_output_edges: number edges out_going
* parent_node: parent pb_graph_node
* pin_count_in_cluster: Unique number for pin inside cluster
*/
struct s_pb_graph_pin {
t_port *port;
int pin_number;
struct s_pb_graph_edge** input_edges; /* [0..num_input_edges] */
int num_input_edges;
struct s_pb_graph_edge** output_edges; /* [0..num_output_edges] */
int num_output_edges;
struct s_pb_graph_node *parent_node;
int pin_count_in_cluster;
/* Xifan TANG: FPGA-SPICE */
int temp_net_num;
int scratch_pad; /* temporary data structure useful to store traversal info */
/* timing information */
enum e_pb_graph_pin_type type; /* Is a sequential logic element (TRUE), inpad/outpad (TRUE), or neither (FALSE) */
float tsu_tco; /* For sequential logic elements, this is the setup time (if input) or clock-to-q time (if output) */
struct s_pb_graph_pin** pin_timing; /* primitive ipin to opin timing */
float *pin_timing_del_max; /* primitive ipin to opin timing */
int num_pin_timing; /* primitive ipin to opin timing */
/* Applies to clusters only */
int pin_class;
/* Applies to pins of primitive only */
int *parent_pin_class; /* [0..depth-1] the grouping of pins that this particular pin belongs to */
/* Applies to output pins of primitives only */
struct s_pb_graph_pin ***list_of_connectable_input_pin_ptrs; /* [0..depth-1][0..num_connectable_primtive_input_pins-1] what input pins this output can connect to without exiting cluster at given depth */
int *num_connectable_primtive_input_pins; /* [0..depth-1] number of input pins that this output pin can reach without exiting cluster at given depth */
boolean is_forced_connection; /* This output pin connects to one and only one input pin */
t_pb_graph_pin_power * pin_power;
};
typedef struct s_pb_graph_pin t_pb_graph_pin;
struct s_pb_graph_pin_power {
/* Transistor-level Power Properties */
float C_wire;
float buffer_size;
/* Pin-Toggle Power Properties */
t_pb_graph_pin * scaled_by_pin;
};
typedef enum {
POWER_WIRE_TYPE_UNDEFINED = 0,
POWER_WIRE_TYPE_IGNORED,
POWER_WIRE_TYPE_C,
POWER_WIRE_TYPE_ABSOLUTE_LENGTH,
POWER_WIRE_TYPE_RELATIVE_LENGTH,
POWER_WIRE_TYPE_AUTO
} e_power_wire_type;
typedef enum {
POWER_BUFFER_TYPE_UNDEFINED = 0,
POWER_BUFFER_TYPE_NONE,
POWER_BUFFER_TYPE_AUTO,
POWER_BUFFER_TYPE_ABSOLUTE_SIZE
} e_power_buffer_type;
struct s_port_power {
/* Transistor-Level Power Properties */
// Wire
e_power_wire_type wire_type;
union {
float C;
float absolute_length;
float relative_length;
} wire;
// Buffer
e_power_buffer_type buffer_type;
float buffer_size;
/* Pin-Toggle Power Properties */
boolean pin_toggle_initialized;
float energy_per_toggle;
t_port * scaled_by_port;
int scaled_by_port_pin_idx;
boolean reverse_scaled; /* Scale by (1-prob) */
};
struct s_pb_graph_node;
/** Describes a pb graph edge, this is a "fat" edge which means it supports bused based connections
* input_pins: array of pb_type graph input pins ptrs entering this edge
* num_input_pins: Number of input pins entering this edge
* output_pins: array of pb_type graph output pins ptrs entering this edge
* num_output_pins: Number of output pins entering this edge
*/
struct s_pb_graph_edge {
t_pb_graph_pin **input_pins;
int num_input_pins;
t_pb_graph_pin **output_pins;
int num_output_pins;
/* timing information */
float delay_max;
float delay_min;
float capacitance;
/* who drives this edge */
t_interconnect * interconnect;
int driver_set;
int driver_pin;
/* pack pattern info */
char **pack_pattern_names; /*[0..num_pack_patterns(of_edge)-1]*/
int *pack_pattern_indices; /*[0..num_pack_patterns(of_edge)-1]*/
int num_pack_patterns;
boolean infer_pattern; /*If TRUE, infer pattern based on patterns connected to it*/
};
typedef struct s_pb_graph_edge t_pb_graph_edge;
struct s_cluster_placement_primitive;
/* This structure stores the physical block graph nodes for a pb_type and mode of a cluster
* pb_type: Pointer to the type of pb graph node this belongs to
* mode: parent mode of operation
* placement_index: there are a certain number of pbs available, this gives the index of the node
* child_pb_graph_nodes: array of children pb graph nodes organized into modes
* parent_pb_graph_node: parent pb graph node
*/
typedef struct s_pb_graph_node t_pb_graph_node;
struct s_pb_graph_node {
struct s_pb_type *pb_type;
int placement_index;
t_pb_graph_pin **input_pins; /* [0..num_input_ports-1] [0..num_port_pins-1]*/
t_pb_graph_pin **output_pins; /* [0..num_output_ports-1] [0..num_port_pins-1]*/
t_pb_graph_pin **clock_pins; /* [0..num_clock_ports-1] [0..num_port_pins-1]*/
int num_input_ports;
int num_output_ports;
int num_clock_ports;
int *num_input_pins; /* [0..num_input_ports - 1] */
int *num_output_pins; /* [0..num_output_ports - 1] */
int *num_clock_pins; /* [0..num_clock_ports - 1] */
struct s_pb_graph_node ***child_pb_graph_nodes; /* [0..num_modes-1][0..num_pb_type_in_mode-1][0..num_pb-1] */
struct s_pb_graph_node *parent_pb_graph_node;
int total_pb_pins; /* only valid for top-level */
void *temp_scratch_pad; /* temporary data, useful for keeping track of things when traversing data structure */
struct s_cluster_placement_primitive *cluster_placement_primitive; /* pointer to indexing structure useful during packing stage */
int *input_pin_class_size; /* Stores the number of pins that belong to a particular input pin class */
int num_input_pin_class; /* number of pin classes that this input pb_graph_node has */
int *output_pin_class_size; /* Stores the number of pins that belong to a particular output pin class */
int num_output_pin_class; /* number of output pin classes that this pb_graph_node has */
/* Interconnect instances for this pb
* Only used for power
*/
t_pb_graph_node_power * pb_node_power;
t_interconnect_pins ** interconnect_pins; /* [0..num_modes-1][0..num_interconnect_in_mode] */
};
struct s_pb_graph_node_power {
float transistor_cnt_pb_children; /* Total transistor size of this pb */
float transistor_cnt_interc; /* Total transistor size of the interconnect in this pb */
float transistor_cnt_buffers;
};
/** Describes a physical block type
* name: name of the physical block type
* num_pb: maximum number of instances of this physical block type sharing one parent
* blif_model: the string in the blif circuit that corresponds with this pb type
* class_type: Special library name
* modes: Different modes accepted
* ports: I/O and clock ports
* num_clock_pins: A count of the total number of clock pins
* int num_input_pins: A count of the total number of input pins
* int num_output_pins: A count of the total number of output pins
* timing: Timing matrix of block [0..num_inputs-1][0..num_outputs-1]
* parent_mode: mode of the parent block
*/
struct s_pb_type {
char* name;
int num_pb;
char *blif_model;
t_model *model;
enum e_pb_type_class class_type;
t_mode *modes; /* [0..num_modes-1] */
int num_modes;
t_port *ports; /* [0..num_ports] */
int num_ports;
int num_clock_pins;
int num_input_pins; /* inputs not including clock pins */
int num_output_pins;
t_mode *parent_mode;
int depth; /* depth of pb_type */
float max_internal_delay;
t_pin_to_pin_annotation *annotations; /* [0..num_annotations-1] */
int num_annotations;
/* Spice model Support: Xifan TANG*/
char* idle_mode_name;
char* physical_mode_name;
char* spice_model_name;
t_spice_model* spice_model;
char* mode_bits; /* Mode bits to select */
/* Power related members */
t_pb_type_power * pb_type_power;
/* Xifan TANG: FPGA-SPICE and SynVerilog */
int physical_mode_num_reserved_conf_bits;
int physical_mode_num_conf_bits;
int physical_mode_num_iopads;
int default_mode_num_reserved_conf_bits;
int default_mode_num_conf_bits;
int default_mode_num_mode_bits;
int default_mode_num_iopads;
};
typedef struct s_pb_type t_pb_type;
struct s_pb_type_power {
/* Type of power estimation for this pb */
e_power_estimation_method estimation_method;
t_power_usage absolute_power_per_instance; /* User-provided absolute power per block */
float C_internal; /*Internal capacitance of the pb */
int leakage_default_mode; /* Default mode for leakage analysis, if block has no set mode */
t_power_usage power_usage; /* Total power usage of this pb type */
t_power_usage power_usage_bufs_wires; /* Power dissipated in local buffers and wire switching (Subset of total power) */
};
/* Describes the type for a physical logic block
name: unique identifier for type
num_pins: Number of pins for the block
capacity: Number of blocks of this type that can occupy one grid tile.
This is primarily used for IO pads.
height: Height of large block in grid tiles
pinloc: Is set to 1 if a given pin exists on a certain position of a block.
num_class: Number of logically-equivalent pin classes
class_inf: Information of each logically-equivalent class
pin_class: The class a pin belongs to
is_global_pin: Whether or not a pin is global (hence not routed)
is_Fc_frac: True if Fc fractional, else Fc absolute
is_Fc_out_full_flex: True means opins will connect to all available segments
pb_type: Internal subblocks and routing information for this physical block
pb_graph_head: Head of DAG of pb_types_nodes and their edges
area: Describes how much area this logic block takes, if undefined, use default
type_timing_inf: timing information unique to this type
num_drivers: Total number of output drivers supplied
num_receivers: Total number of input receivers supplied
index: Keep track of type in array for easy access
*/
struct s_type_descriptor /* TODO rename this. maybe physical type descriptor or complex logic block or physical logic block*/
{
char *name;
int num_pins;
int capacity;
int height;
int ***pinloc; /* [0..height-1][0..3][0..num_pins-1] */
int *pin_height; /* [0..num_pins-1] */
int **num_pin_loc_assignments; /* [0..height-1][0..3] */
char ****pin_loc_assignments; /* [0..height-1][0..3][0..num_tokens-1][0..string_name] */
enum e_pin_location_distr pin_location_distribution;
int num_class;
struct s_class *class_inf; /* [0..num_class-1] */
int *pin_class; /* [0..num_pins-1] */
boolean *is_global_pin; /* [0..num_pins-1] */
boolean *is_Fc_frac; /* [0..num_pins-1] */
boolean *is_Fc_full_flex; /* [0..num_pins-1] */
float *Fc; /* [0..num_pins-1] */
/* Clustering info */
struct s_pb_type *pb_type;
t_pb_graph_node *pb_graph_head;
/* Grid location info */
struct s_grid_loc_def *grid_loc_def; /* [0..num_def-1] */
int num_grid_loc_def;
float area;
/* This info can be determined from class_inf and pin_class but stored for faster access */
int num_drivers;
int num_receivers;
int index; /* index of type descriptor in array (allows for index referencing) */
/* mrFPGA: Xifan TANG */
int* pin_index_per_side;
int* pin_ptc_to_side;
/* end */
/* Xifan TANG: opin_to_cb support */
boolean opin_to_cb;
/* Xifan TANG: Pin equivalence auto detect */
boolean input_ports_eq_auto_detect;
boolean output_ports_eq_auto_detect;
};
typedef struct s_type_descriptor t_type_descriptor;
typedef const struct s_type_descriptor *t_type_ptr;
/*************************************************************************************************/
/* FPGA Routing architecture */
/*************************************************************************************************/
/* Description of routing channel distribution across the FPGA, only available for global routing
* Width is standard dev. for Gaussian. xpeak is where peak *
* occurs. dc is the dc offset for Gaussian and pulse waveforms. */
enum e_stat {
UNIFORM, GAUSSIAN, PULSE, DELTA
};
typedef struct s_chan {
enum e_stat type;
float peak;
float width;
float xpeak;
float dc;
} t_chan;
/* chan_width_io: The relative width of the I/O channel between the pads *
* and logic array. *
* chan_x_dist: Describes the x-directed channel width distribution. *
* chan_y_dist: Describes the y-directed channel width distribution. */
typedef struct s_chan_width_dist {
float chan_width_io;
t_chan chan_x_dist;
t_chan chan_y_dist;
} t_chan_width_dist;
enum e_directionality {
UNI_DIRECTIONAL, BI_DIRECTIONAL
};
enum e_switch_block_type {
SUBSET, WILTON, UNIVERSAL, FULL
};
typedef enum e_switch_block_type t_switch_block_type;
enum e_Fc_type {
ABSOLUTE, FRACTIONAL
};
/* Lists all the important information about a certain segment type. Only *
* used if the route_type is DETAILED. [0 .. det_routing_arch.num_segment] *
* frequency: ratio of tracks which are of this segment type. *
* length: Length (in clbs) of the segment. *
* wire_switch: Index of the switch type that connects other wires *to* *
* this segment. *
* opin_switch: Index of the switch type that connects output pins (OPINs) *
* *to* this segment. *
* frac_cb: The fraction of logic blocks along its length to which this *
* segment can connect. (i.e. internal population). *
* frac_sb: The fraction of the length + 1 switch blocks along the segment *
* to which the segment can connect. Segments that aren't long *
* lines must connect to at least two switch boxes. *
* Cmetal: Capacitance of a routing track, per unit logic block length. *
* Rmetal: Resistance of a routing track, per unit logic block length.
* (UDSD by AY) drivers: How do signals driving a routing track connect to *
* the track? */
typedef struct s_segment_inf {
int frequency;
int length;
short wire_switch;
short opin_switch;
float frac_cb;
float frac_sb;
boolean longline;
float Rmetal;
float Cmetal;
enum e_directionality directionality;
boolean *cb;
int cb_len;
boolean *sb;
int sb_len;
//float Cmetal_per_m; /* Wire capacitance (per meter) */
/* Xifan TANG: SPICE model support*/
char* spice_model_name;
t_spice_model* spice_model;
/* mrFPGA: Xifan TANG */
short seg_switch;
/* end */
} t_segment_inf;
/* Lists all the important information about a switch type. *
* [0 .. Arch.num_switch] *
* buffered: Does this switch include a buffer? *
* R: Equivalent resistance of the buffer/switch. *
* Cin: Input capacitance. *
* Cout: Output capacitance. *
* Tdel: Intrinsic delay. The delay through an unloaded switch is *
* Tdel + R * Cout. *
* mux_trans_size: The area of each transistor in the segment's driving mux *
* measured in minimum width transistor units *
* buf_size: The area of the buffer. If set to zero, area should be *
* calculated from R */
typedef struct s_switch_inf {
boolean buffered;
float R;
float Cin;
float Cout;
float Tdel;
float mux_trans_size;
float buf_size;
char *name;
e_power_buffer_type power_buffer_type;
float power_buffer_size;
/*Xifan TANG: Switch segment pattern support*/
char* type;
/* Xifan TANG: spice support*/
char* spice_model_name;
t_spice_model* spice_model;
/* Xifan TANG: switch structure */
enum e_spice_model_structure structure;
int switch_num_level;
} t_switch_inf;
/*Xifan TANG: switch segment pattern type*/
enum e_swseg_pattern_type {
SWSEG_UNBUF_SB, SWSEG_UNBUF_CB
};
/* Xifan TANG: Struct switch segment pattern*/
typedef struct s_swseg_pattern_inf t_swseg_pattern_inf;
struct s_swseg_pattern_inf {
enum e_swseg_pattern_type type;
short unbuf_switch;
int seg_length;
enum e_directionality seg_direction_type;
int pattern_length;
boolean* patterns;
};
/* Lists all the important information about a direct chain connection. *
* [0 .. det_routing_arch.num_direct] *
* name: Name of this direct chain connection *
* from_pin: The type of the pin that drives this chain connection *
In the format of <block_name>.<pin_name> *
* to_pin: The type of pin that is driven by this chain connection *
In the format of <block_name>.<pin_name> *
* x_offset: The x offset from the source to the sink of this connection *
* y_offset: The y offset from the source to the sink of this connection *
* line: The line number in the .arch file that specifies this *
* particular placement macro. *
*/
typedef struct s_direct_inf {
char *name;
char *from_pin;
char *to_pin;
int x_offset;
int y_offset;
int z_offset;
int line;
} t_direct_inf;
/* Detailed routing architecture */
typedef struct s_arch t_arch;
struct s_arch {
t_chan_width_dist Chans;
enum e_switch_block_type SBType;
float R_minW_nmos;
float R_minW_pmos;
int Fs;
float C_ipin_cblock;
float T_ipin_cblock;
/* mrFPGA: Xifan TANG */
t_arch_mrfpga arch_mrfpga;
/* END*/
float grid_logic_tile_area;
float ipin_mux_trans_size;
struct s_clb_grid clb_grid;
t_segment_inf * Segments;
int num_segments;
/* Xifan TANG: SRAM, SPICE Model Support*/
t_sram_inf sram_inf;
/*Xifan TANG: SPICE Model Support*/
boolean read_xml_spice;
t_spice* spice;
/*Xifan TANG: Connection Block Support*/
int num_cb_switch;
t_switch_inf* cb_switches;
/* Xifan TANG: switch segment pattern support*/
int num_swseg_pattern;
t_swseg_pattern_inf* swseg_patterns;
/* END */
struct s_switch_inf *Switches;
int num_switches;
t_direct_inf *Directs;
int num_directs;
t_model *models;
t_model *model_library;
t_power_arch * power;
t_clock_arch * clocks;
};
#endif

33
vpr7_rram/libarchfpga/include/read_xml_arch_file.h Normal file
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#ifndef READ_XML_ARCH_FILE_H
#define READ_XML_ARCH_FILE_H
#include "util.h"
#include "arch_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/* special type indexes, necessary for initialization, everything afterwards
should use the pointers to these type indices*/
#define NUM_MODELS_IN_LIBRARY 4
#define EMPTY_TYPE_INDEX 0
#define IO_TYPE_INDEX 1
/* function declarations */
void
XmlReadArch( INP const char *ArchFile, INP boolean timing_enabled,
OUTP struct s_arch *arch, OUTP t_type_descriptor ** Types,
OUTP int *NumTypes);
void
EchoArch( INP const char *EchoFile, INP const t_type_descriptor * Types,
INP int NumTypes, struct s_arch *arch);
#ifdef __cplusplus
}
#endif
#endif

19
vpr7_rram/libarchfpga/include/read_xml_mrfpga.h Normal file
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/* mrFPGA */
void init_buffer_inf(t_buffer_inf* buffer_inf);
void init_memristor_inf(t_memristor_inf* memristor_inf);
void init_arch_mrfpga(t_arch_mrfpga* arch_mrfpga);
void ProcessTechHack(INOUTP ezxml_t Node,
OUTP struct s_arch *arch);
void ProcessmrFPGA(INOUTP ezxml_t Node,
OUTP struct s_arch *arch);
void ProcessTechnology(INOUTP ezxml_t Node,
OUTP struct s_arch *arch);
void ProcessWireBuffer(INOUTP ezxml_t Node,
OUTP struct s_arch *arch);
void ProcessMrFPGATiming(INOUTP ezxml_t Cur,
OUTP t_arch* arch);
/* end */

36
vpr7_rram/libarchfpga/include/read_xml_util.h Normal file
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#ifndef READ_XML_UTIL_H
#define READ_XML_UTIL_H
#include "util.h"
#include "ezxml.h"
#ifdef __cplusplus
extern "C" {
#endif
ezxml_t FindElement(INP ezxml_t Parent, INP const char *Name,
INP boolean Required);
ezxml_t FindFirstElement(INP ezxml_t Parent, INP const char *Name,
INP boolean Required);
void CheckElement(INP ezxml_t Node, INP const char *Name);
void FreeNode(INOUTP ezxml_t Node);
const char * FindProperty(INP ezxml_t Parent, INP const char *Name,
INP boolean);
boolean IsWhitespace(char c);
void CountTokensInString(INP const char *Str, OUTP int *Num,
OUTP int *Len);
char **GetNodeTokens(INP ezxml_t Node);
char **LookaheadNodeTokens(INP ezxml_t Node);
int CountChildren(INP ezxml_t Node, INP const char *Name,
INP int min_count);
int GetIntProperty(INP ezxml_t Parent, INP char *Name,
INP boolean Required, INP int default_value);
float GetFloatProperty(INP ezxml_t Parent, INP char *Name,
INP boolean Required, INP float default_value);
boolean GetBooleanProperty(INP ezxml_t Parent, INP char *Name,
INP boolean Required, INP boolean default_value);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef UTIL_H
#define UTIL_H
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include "TIO_PrintHandlerExtern.h"
#ifndef TRUE /* Some compilers predefine TRUE, FALSE */
typedef enum {
FALSE, TRUE
} boolean;
#else
typedef int boolean;
#endif
/* Parameter tags for preprocessor to strip */
#define INP
#define OUTP
#define INOUTP
#define BUFSIZE 4096 /* Maximum line length for various parsing proc. */
#define nint(a) ((int) floor (a + 0.5))
#define ERRTAG "ERROR:\t"
#define WARNTAG "WARNING:\t"
int limit_value(int cur, int max, const char *name);
/* Linked lists of void pointers and integers, respectively. */
typedef struct s_linked_vptr {
void *data_vptr;
struct s_linked_vptr *next;
} t_linked_vptr;
typedef struct s_linked_int {
int data;
struct s_linked_int *next;
} t_linked_int;
/* Integer vector. nelem stores length, list[0..nelem-1] stores list of *
* integers. */
typedef struct s_ivec {
int nelem;
int *list;
} t_ivec;
/* This structure is to keep track of chunks of memory that is being *
* allocated to save overhead when allocating very small memory pieces. *
* For a complete description, please see the comment in my_chunk_malloc*
* in libarchfpga/utils.c. */
typedef struct s_chunk {
struct s_linked_vptr *chunk_ptr_head;
/* chunk_ptr_head->data_vptr: head of the entire linked
* list of allocated "chunk" memory;
* chunk_ptr_head->next: pointer to the next chunk on the linked list*/
int mem_avail; /* number of bytes left in the current chunk */
char *next_mem_loc_ptr;/* pointer to the first available (free) *
* byte in the current chunk */
} t_chunk;
#ifdef __cplusplus
extern "C" {
#endif
extern int file_line_number; /* line in file being parsed */
extern char *out_file_prefix; /* Default prefix string for output files */
/************************ Memory allocation routines *************************/
void* my_malloc(size_t size);
void* my_calloc(size_t nelem, size_t size);
void *my_realloc(void *ptr, size_t size);
void *my_chunk_malloc(size_t size, t_chunk *chunk_info);
void free_chunk_memory(t_chunk *chunk_info);
/******************* Linked list, matrix and vector utilities ****************/
void free_ivec_vector(struct s_ivec *ivec_vector, int nrmin, int nrmax);
void free_ivec_matrix(struct s_ivec **ivec_matrix, int nrmin, int nrmax,
int ncmin, int ncmax);
void free_ivec_matrix3(struct s_ivec ***ivec_matrix3, int nrmin,
int nrmax, int ncmin, int ncmax, int ndmin, int ndmax);
void** alloc_matrix(int nrmin, int nrmax, int ncmin, int ncmax,
size_t elsize);
void ***alloc_matrix3(int nrmin, int nrmax, int ncmin, int ncmax,
int ndmin, int ndmax, size_t elsize);
void ****alloc_matrix4(int nrmin, int nrmax, int ncmin, int ncmax,
int ndmin, int ndmax, int nemin, int nemax, size_t elsize);
void free_matrix(void *vptr, int nrmin, int nrmax, int ncmin,
size_t elsize);
void free_matrix3(void *vptr, int nrmin, int nrmax, int ncmin, int ncmax,
int ndmin, size_t elsize);
void free_matrix4(void *vptr, int nrmin, int nrmax, int ncmin, int ncmax,
int ndmin, int ndmax, int nemin, size_t elsize);
void print_int_matrix3(int ***vptr, int nrmin, int nrmax, int ncmin,
int ncmax, int ndmin, int ndmax, char *file);
struct s_linked_vptr *insert_in_vptr_list(struct s_linked_vptr *head,
void *vptr_to_add);
struct s_linked_vptr *delete_in_vptr_list(struct s_linked_vptr *head);
t_linked_int *insert_in_int_list(t_linked_int * head, int data,
t_linked_int ** free_list_head_ptr);
/* Xifan TANG: Search the int list */
t_linked_int* insert_node_to_int_list(struct s_linked_int *head, int int_to_add);
t_linked_int* search_in_int_list(t_linked_int* int_list_head, int data_target);
/* END */
void free_int_list(t_linked_int ** int_list_head_ptr);
void alloc_ivector_and_copy_int_list(t_linked_int ** list_head_ptr,
int num_items, struct s_ivec *ivec, t_linked_int ** free_list_head_ptr);
/****** Xifan TANG's utils ******/
int spot_int_in_array(int array_len, int* array, int targ);
/****************** File and parsing utilities *******************************/
int my_atoi(const char *str);
char* my_strdup(const char *str);
char *my_strncpy(char *dest, const char *src, size_t size);
char *my_strtok(char *ptr, const char *tokens, FILE * fp, char *buf);
FILE* my_fopen(const char *fname, const char *flag, int prompt);
char *my_fgets(char *buf, int max_size, FILE * fp);
boolean file_exists(const char * filename);
/*********************** Portable random number generators *******************/
void my_srandom(int seed);
int my_irand(int imax);
float my_frand(void);
typedef unsigned char (*messagelogger)( TIO_MessageMode_t messageMode,
char* pszMessage,
... );
extern messagelogger vpr_printf;
#ifdef __cplusplus
}
#endif
/*********************** Math operations *************************************/
int ipow(int base, int exp);
#endif

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<?xml version="1.0" encoding="utf-8"?>
<Project DefaultTargets="Build" ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
<ItemGroup Label="ProjectConfigurations">
<ProjectConfiguration Include="Debug|Win32">
<Configuration>Debug</Configuration>
<Platform>Win32</Platform>
</ProjectConfiguration>
<ProjectConfiguration Include="Release|Win32">
<Configuration>Release</Configuration>
<Platform>Win32</Platform>
</ProjectConfiguration>
</ItemGroup>
<PropertyGroup Label="Globals">
<ProjectGuid>{CBBA36E0-CD88-4586-AFB6-A0E603D16796}</ProjectGuid>
<TargetFrameworkVersion>v4.0</TargetFrameworkVersion>
<Keyword>ManagedCProj</Keyword>
<RootNamespace>libarchfpga</RootNamespace>
</PropertyGroup>
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.Default.props" />
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'" Label="Configuration">
<ConfigurationType>StaticLibrary</ConfigurationType>
<UseDebugLibraries>true</UseDebugLibraries>
<CLRSupport>false</CLRSupport>
<CharacterSet>Unicode</CharacterSet>
</PropertyGroup>
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
<ConfigurationType>StaticLibrary</ConfigurationType>
<UseDebugLibraries>false</UseDebugLibraries>
<CLRSupport>false</CLRSupport>
<CharacterSet>Unicode</CharacterSet>
</PropertyGroup>
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.props" />
<ImportGroup Label="ExtensionSettings">
</ImportGroup>
<ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
<Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
</ImportGroup>
<ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
<Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
</ImportGroup>
<PropertyGroup Label="UserMacros" />
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
<LinkIncremental>true</LinkIncremental>
</PropertyGroup>
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
<LinkIncremental>false</LinkIncremental>
</PropertyGroup>
<ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
<ClCompile>
<WarningLevel>Level3</WarningLevel>
<Optimization>Disabled</Optimization>
<PreprocessorDefinitions>_CRT_SECURE_NO_WARNINGS;_DEBUG;%(PreprocessorDefinitions)</PreprocessorDefinitions>
<PrecompiledHeader>NotUsing</PrecompiledHeader>
<DebugInformationFormat>EditAndContinue</DebugInformationFormat>
<CompileAsManaged>
</CompileAsManaged>
<AdditionalIncludeDirectories>include;../printhandler/SRC/TIO_InputOutputHandlers</AdditionalIncludeDirectories>
<RuntimeLibrary>MultiThreaded</RuntimeLibrary>
<CompileAs>CompileAsCpp</CompileAs>
</ClCompile>
<Link>
<GenerateDebugInformation>true</GenerateDebugInformation>
<AdditionalDependencies>
</AdditionalDependencies>
</Link>
<ProjectReference>
<LinkLibraryDependencies>true</LinkLibraryDependencies>
</ProjectReference>
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<ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
<ClCompile>
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<CompileAsManaged>false</CompileAsManaged>
<RuntimeLibrary>MultiThreaded</RuntimeLibrary>
<AdditionalIncludeDirectories>include;../printhandler/SRC/TIO_InputOutputHandlers</AdditionalIncludeDirectories>
<Optimization>Full</Optimization>
<CallingConvention>Cdecl</CallingConvention>
<CompileAs>CompileAsCpp</CompileAs>
</ClCompile>
<Link>
<GenerateDebugInformation>true</GenerateDebugInformation>
<AdditionalDependencies>
</AdditionalDependencies>
</Link>
</ItemDefinitionGroup>
<ItemGroup>
<ClInclude Include="include\arch_types.h" />
<ClInclude Include="include\ezxml.h" />
<ClInclude Include="include\logic_types.h" />
<ClInclude Include="include\physical_types.h" />
<ClInclude Include="include\ReadLine.h" />
<ClInclude Include="include\read_xml_arch_file.h" />
<ClInclude Include="include\read_xml_util.h" />
<ClInclude Include="include\util.h" />
</ItemGroup>
<ItemGroup>
<ClCompile Include="ezxml.c" />
<ClCompile Include="ReadLine.c" />
<ClCompile Include="read_xml_arch_file.c" />
<ClCompile Include="read_xml_util.c" />
<ClCompile Include="util.c" />
</ItemGroup>
<ItemGroup>
<ProjectReference Include="..\printhandler\printhandler.vcxproj">
<Project>{a5092a9c-6dfd-4dec-9951-51606f5eaf3b}</Project>
</ProjectReference>
</ItemGroup>
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>
</Project>

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<?xml version="1.0" encoding="utf-8"?>
<Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
<ItemGroup>
<Filter Include="Source Files">
<UniqueIdentifier>{4FC737F1-C7A5-4376-A066-2A32D752A2FF}</UniqueIdentifier>
<Extensions>cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx</Extensions>
</Filter>
<Filter Include="Header Files">
<UniqueIdentifier>{93995380-89BD-4b04-88EB-625FBE52EBFB}</UniqueIdentifier>
<Extensions>h;hpp;hxx;hm;inl;inc;xsd</Extensions>
</Filter>
<Filter Include="Resource Files">
<UniqueIdentifier>{67DA6AB6-F800-4c08-8B7A-83BB121AAD01}</UniqueIdentifier>
<Extensions>rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms</Extensions>
</Filter>
</ItemGroup>
<ItemGroup>
<ClInclude Include="include\arch_types.h">
<Filter>Header Files</Filter>
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<Filter>Header Files</Filter>
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<Filter>Header Files</Filter>
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</ClInclude>
<ClInclude Include="include\read_xml_arch_file.h">
<Filter>Header Files</Filter>
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<Filter>Header Files</Filter>
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<ClCompile Include="ezxml.c">
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<Filter>Source Files</Filter>
</ClCompile>
</ItemGroup>
</Project>

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/**
* Filename : linkedlist.c
* Author : Xifan TANG, EPFL
* Description : Define most useful functions for a general purpose linked list
*/
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include "util.h"
/* Data structures*/
#include "linkedlist.h"
/**
* Create, insert, delete, cat
* General purpose linked list
*/
/**
* Create fixed length of Linked list
* Node struct must have a pointor named after "next"!
*/
t_llist* create_llist(int len) {
t_llist* head;
t_llist* tmp_head;
int ind;
/* Create a scout, this is a blank node*/
head = (t_llist*)my_malloc(sizeof(t_llist));
head->next = NULL;
for (ind=0; ind<(len-1); ind++) {
/* Create a node ahead of the current*/
tmp_head = (t_llist*)my_malloc(sizeof(t_llist));
tmp_head->next = head;
head = tmp_head;
}
return head;
}
/**
* Insert a node inside the linked list
* Cur is pointer which a new node will be inserted after.
* If Cur is a NULL pointer, we create a linked-list head
* If Cur is not NULL, we add a node after the tail of linked-list
*/
t_llist* insert_llist_node(t_llist* cur) {
t_llist* cur_next;
/* Store the current next*/
cur_next = cur->next;
/* Allocate new node*/
cur->next = (t_llist*)my_malloc(sizeof(t_llist));
/* Configure the new node*/
cur->next->next = cur_next;
return cur->next;
}
/**
* Insert a node inside the linked list
* The inserted node will be before the old head, becoming the new head
*/
t_llist* insert_llist_node_before_head(t_llist* old_head) {
/* Allocate new node*/
t_llist* new_head = (t_llist*)my_malloc(sizeof(t_llist));
/* Store the current next*/
new_head->next = old_head;
return new_head;
}
/**
* Romove a node from linked list
* cur is the node whose next node is to be removed
*/
void remove_llist_node(t_llist* cur) {
t_llist* rm_node = cur->next;
/* Connect the next next node*/
cur->next = cur->next->next;
/* free the node*/
free(rm_node);
}
/**
* Cat the linked list
* head2 is connected to the tail of head1
* return head1
*/
t_llist* cat_llists(t_llist* head1,
t_llist* head2) {
t_llist* tmp = head1;
/* Reach the tail of head1*/
while(tmp->next != NULL) {
tmp = tmp->next;
}
/* Cat*/
tmp->next = head2->next;
/* Free head2*/
free(head2);
return head1;
}
t_llist* search_llist_tail(t_llist* head) {
t_llist* temp = head;
if (NULL == temp) {
return temp;
}
while(temp->next != NULL) {
temp = temp->next;
}
return temp;
}
int find_length_llist(t_llist* head) {
int length = 0;
t_llist* temp = head;
if (NULL == temp) {
/* A NULL head means zero length */
return length;
} else {
/* Otherwise, we have already one element */
length++;
}
while (temp->next != NULL) {
length++;
temp = temp->next;
}
return length;
}
/* Free a linked list, Make sure before this function,
* the dptr has been freed! I cannot free them here!!!
*/
void free_llist(t_llist* head) {
t_llist* temp = head;
t_llist* node_to_free = NULL;
/* From the head to tail,
* free each linked node and move on to the next
*/
while(temp) { /*Until we reach the tail, which is a null pointer*/
if (NULL != temp->dptr) {
printf("ERROR: The data pointer in linked list is not NULL!\n");
printf(" It is possible that the data pointer is not freed!\n");
exit(1);
}
/* Store the current node to be freed*/
node_to_free = temp;
/* Move on to the next*/
temp = temp->next;
/* Now it is time to free*/
free(node_to_free);
}
return;
}
/* Reverse a linked list and return the new head */
t_llist* reverse_llist(t_llist* head) {
t_llist* temp = head;
t_llist* next = NULL;
t_llist* last = NULL; /* pointor to the last-visited llist node */
while (NULL != temp) {
/* Modify the next pointor of current node */
next = temp->next;
temp->next = last;
/* Update the last node */
last = temp;
/* Go to next */
temp = next;
}
return last;
}

66
vpr7_rram/libarchfpga/main.c Normal file
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/*
Test libarchfpga, try reading an architecture and print the results to a file
Date: February 19, 2009
Author: Jason Luu
*/
#include <stdio.h>
#include <stdlib.h>
#include "read_xml_arch_file.h"
void print_help();
int main(int argc, char **argv) {
struct s_arch arch;
t_type_descriptor *types;
int numTypes;
;
if (argc - 1 != 3) {
printf(
"Error: Unexpected # of arguments. Expected 3 found %d arguments\n",
argc);
print_help();
}
printf(
"------------------------------------------------------------------------------\n");
printf(
"- Read architecture file and print library data structures into an output file\n");
printf(
"------------------------------------------------------------------------------\n\n");
printf("Inputs: \n"
"architecture %s \n"
"timing_driven %d \n"
"output file %s\n", argv[1], atoi(argv[2]), argv[3]);
printf("Reading in architecture\n");
/* function declarations */
XmlReadArch(argv[1], (boolean) atoi(argv[2]), &arch, &types, &numTypes);
printf("Printing Results\n");
EchoArch(argv[3], types, numTypes, &arch);
printf("Done\n");
return 0;
}
void print_help() {
printf(
"\n---------------------------------------------------------------------------------------\n");
printf(
"read_arch: Read a VPR architecture file and output internal data structures");
printf(
"Usage: read_arch <arch_file.xml> <timing_driven (0|1)> <output_file>\n");
printf(" ex: read_arch k4_n10.xml 1 arch_data.out\n");
printf(
" Read timing-driven architecture k4_n10.xml and output the results to arch_data.out\n");
printf(
"\n---------------------------------------------------------------------------------------\n");
}

3989
vpr7_rram/libarchfpga/read_xml_arch_file.c Normal file
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