built a conversion from spice_models to circuit_library and plug in

vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp

@@ -193,6 +193,15 @@ std::string CircuitLibrary::port_inv_prefix(const CircuitModelId& circuit_model_
   return port_inv_prefix_[circuit_model_id][circuit_port_id];
 }
 
+/* Return the default value of a port of a circuit model */
+size_t CircuitLibrary::port_default_value(const CircuitModelId& circuit_model_id, 
+                                        const CircuitPortId& circuit_port_id) const {
+  /* validate the circuit_port_id */
+  VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id));
+  return port_default_values_[circuit_model_id][circuit_port_id];
+}
+
+
 /* Return a flag if the port is used in mode-selection purpuse of a circuit model */
 bool CircuitLibrary::port_is_mode_select(const CircuitModelId& circuit_model_id, 
                                          const CircuitPortId& circuit_port_id) const {
@@ -303,6 +312,7 @@ CircuitModelId CircuitLibrary::add_circuit_model() {
   buffer_existence_.emplace_back();
   buffer_circuit_model_names_.emplace_back();
   buffer_circuit_model_ids_.emplace_back();
+  buffer_location_maps_.emplace_back();
 
   /* Pass-gate-related parameters */
   pass_gate_logic_circuit_model_names_.emplace_back();
@@ -314,6 +324,8 @@ CircuitModelId CircuitLibrary::add_circuit_model() {
   port_sizes_.emplace_back();
   port_prefix_.emplace_back();
   port_lib_names_.emplace_back();
+  port_inv_prefix_.emplace_back();
+  port_default_values_.emplace_back();
   port_is_mode_select_.emplace_back();
   port_is_global_.emplace_back();
   port_is_reset_.emplace_back();
@@ -348,7 +360,6 @@ CircuitModelId CircuitLibrary::add_circuit_model() {
 
   /* Buffer/Inverter-related parameters */
   buffer_types_.push_back(NUM_CIRCUIT_MODEL_BUF_TYPES);
-  buffer_location_maps_.emplace_back();
   buffer_sizes_.push_back(-1);
   buffer_num_levels_.push_back(-1);
   buffer_f_per_stage_.push_back(-1);
@@ -367,6 +378,9 @@ CircuitModelId CircuitLibrary::add_circuit_model() {
   /* LUT-related parameters */
   lut_is_fracturable_.push_back(false);
 
+  /* Gate-related parameters */
+  gate_types_.push_back(NUM_SPICE_MODEL_GATE_TYPES);
+
   /* RRAM-related design technology information */
   rram_res_.emplace_back();
   wprog_set_.emplace_back();
@@ -519,6 +533,15 @@ void CircuitLibrary::set_circuit_model_lut_intermediate_buffer(const CircuitMode
   return;
 }
 
+void CircuitLibrary::set_circuit_model_lut_intermediate_buffer_location_map(const CircuitModelId& circuit_model_id,
+                                                                            const std::string& location_map) {
+  /* validate the circuit_model_id */
+  VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id));
+  buffer_location_maps_[circuit_model_id][LUT_INTER_BUFFER] = location_map; 
+  return;
+}
+
+
 /* Set pass-gate logic information of a circuit model */
 void CircuitLibrary::set_circuit_model_pass_gate_logic(const CircuitModelId& circuit_model_id, const std::string& circuit_model_name) {
   /* validate the circuit_model_id */
@@ -542,6 +565,7 @@ CircuitPortId CircuitLibrary::add_circuit_model_port(const CircuitModelId& circu
   port_prefix_[circuit_model_id].emplace_back();
   port_lib_names_[circuit_model_id].emplace_back();
   port_inv_prefix_[circuit_model_id].emplace_back();
+  port_default_values_[circuit_model_id].push_back(-1);
   port_is_mode_select_[circuit_model_id].push_back(false);
   port_is_global_[circuit_model_id].push_back(false);
   port_is_reset_[circuit_model_id].push_back(false);
@@ -561,9 +585,9 @@ CircuitPortId CircuitLibrary::add_circuit_model_port(const CircuitModelId& circu
 }
 
 /* Set the type for a port of a circuit model */
-void CircuitLibrary::set_port_types(const CircuitModelId& circuit_model_id, 
+void CircuitLibrary::set_port_type(const CircuitModelId& circuit_model_id, 
-                                    const CircuitPortId& circuit_port_id, 
+                                   const CircuitPortId& circuit_port_id, 
-                                    const enum e_spice_model_port_type& port_type) {
+                                   const enum e_spice_model_port_type& port_type) {
   /* validate the circuit_port_id */
   VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id));
   port_types_[circuit_model_id][circuit_port_id] = port_type;
@@ -571,9 +595,9 @@ void CircuitLibrary::set_port_types(const CircuitModelId& circuit_model_id,
 }
 
 /* Set the size for a port of a circuit model */
-void CircuitLibrary::set_port_sizes(const CircuitModelId& circuit_model_id, 
+void CircuitLibrary::set_port_size(const CircuitModelId& circuit_model_id, 
-                                    const CircuitPortId& circuit_port_id, 
+                                   const CircuitPortId& circuit_port_id, 
-                                    const size_t& port_size) {
+                                   const size_t& port_size) {
   /* validate the circuit_port_id */
   VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id));
   port_sizes_[circuit_model_id][circuit_port_id] = port_size;
@@ -610,6 +634,16 @@ void CircuitLibrary::set_port_inv_prefix(const CircuitModelId& circuit_model_id,
   return;
 }
 
+/* Set the default value for a port of a circuit model */
+void CircuitLibrary::set_port_default_value(const CircuitModelId& circuit_model_id, 
+                                            const CircuitPortId& circuit_port_id, 
+                                            const size_t& default_value) {
+  /* validate the circuit_port_id */
+  VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id));
+  port_default_values_[circuit_model_id][circuit_port_id] = default_value;
+  return;
+}
+
 /* Set the is_mode_select for a port of a circuit model */
 void CircuitLibrary::set_port_is_mode_select(const CircuitModelId& circuit_model_id, 
                                              const CircuitPortId& circuit_port_id, 
@@ -822,18 +856,8 @@ void CircuitLibrary::set_buffer_type(const CircuitModelId& circuit_model_id,
   return;
 }
 
-void CircuitLibrary::set_buffer_location_map(const CircuitModelId& circuit_model_id,
-                                             const std::string& location_map) {
-  /* validate the circuit_model_id */
-  VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id));
-  /* validate that the type of this circuit_model should be BUFFER or INVERTER */
-  VTR_ASSERT_SAFE(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id));
-  buffer_location_maps_[circuit_model_id] = location_map; 
-  return;
-}
-
 void CircuitLibrary::set_buffer_size(const CircuitModelId& circuit_model_id,
-                                     const size_t& buffer_size) {
+                                     const float& buffer_size) {
   /* validate the circuit_model_id */
   VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id));
   /* validate that the type of this circuit_model should be BUFFER or INVERTER */
@@ -874,7 +898,7 @@ void CircuitLibrary::set_pass_gate_logic_type(const CircuitModelId& circuit_mode
 }
 
 void CircuitLibrary::set_pass_gate_logic_nmos_size(const CircuitModelId& circuit_model_id,
-                                                   const size_t& nmos_size) {
+                                                   const float& nmos_size) {
   /* validate the circuit_model_id */
   VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id));
   /* validate that the type of this circuit_model should be BUFFER or INVERTER */
@@ -884,7 +908,7 @@ void CircuitLibrary::set_pass_gate_logic_nmos_size(const CircuitModelId& circuit
 }
 
 void CircuitLibrary::set_pass_gate_logic_pmos_size(const CircuitModelId& circuit_model_id,
-                                                   const size_t& pmos_size) {
+                                                   const float& pmos_size) {
   /* validate the circuit_model_id */
   VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id));
   /* validate that the type of this circuit_model should be BUFFER or INVERTER */
@@ -955,6 +979,18 @@ void CircuitLibrary::set_lut_is_fracturable(const CircuitModelId& circuit_model_
   return;
 }
 
+/* Gate-related parameters */
+void CircuitLibrary::set_gate_type(const CircuitModelId& circuit_model_id,
+                                   const enum e_spice_model_gate_type& gate_type) {
+  /* validate the circuit_model_id */
+  VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id));
+  /* validate that the type of this circuit_model should be GATE */
+  VTR_ASSERT_SAFE(SPICE_MODEL_GATE == circuit_model_type(circuit_model_id));
+  gate_types_[circuit_model_id] = gate_type; 
+  return;
+}
+
+
 /* RRAM-related design technology information */
 void CircuitLibrary::set_rram_rlrs(const CircuitModelId& circuit_model_id,
                                    const float& rlrs) {
@@ -1079,6 +1115,7 @@ void CircuitLibrary::set_circuit_model_buffer(const CircuitModelId& circuit_mode
     buffer_existence_[circuit_model_id].resize(size_t(buffer_type) + 1); 
     buffer_circuit_model_names_[circuit_model_id].resize(size_t(buffer_type) + 1); 
     buffer_circuit_model_ids_[circuit_model_id].resize(size_t(buffer_type) + 1); 
+    buffer_location_maps_[circuit_model_id].resize(size_t(buffer_type) + 1); 
   }
   /* Now we are in the range, assign values */
   buffer_existence_[circuit_model_id][size_t(buffer_type)] = existence;

vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h

@@ -55,7 +55,7 @@
 #include "vtr_vector.h"
 #include "vtr_range.h"
 
-#include "spice_types.h"
+#include "circuit_types.h"
 
 /************************************************************************
  * Create strong id for Circuit Models/Ports to avoid illegal type casting 
@@ -238,6 +238,7 @@ class CircuitLibrary {
     std::string port_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const;
     std::string port_lib_name(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const;
     std::string port_inv_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const;
+    size_t port_default_value(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const;
     bool port_is_mode_select(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const;
     bool port_is_global(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const;
     bool port_is_reset(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const;
@@ -273,16 +274,18 @@ class CircuitLibrary {
                                               const bool& existence, const std::string& circuit_model_name);
     void set_circuit_model_lut_intermediate_buffer(const CircuitModelId& circuit_model_id, 
                                                    const bool& existence, const std::string& circuit_model_name);
+    void set_circuit_model_lut_intermediate_buffer_location_map(const CircuitModelId& circuit_model_id,
+                                                                const std::string& location_map);
     /* Pass-gate-related parameters */
     void set_circuit_model_pass_gate_logic(const CircuitModelId& circuit_model_id, const std::string& circuit_model_name);
     /* Port information */
     CircuitPortId add_circuit_model_port(const CircuitModelId& circuit_model_id);
-    void set_port_types(const CircuitModelId& circuit_model_id, 
+    void set_port_type(const CircuitModelId& circuit_model_id, 
-                        const CircuitPortId& circuit_port_id, 
+                       const CircuitPortId& circuit_port_id, 
-                        const enum e_spice_model_port_type& port_type);
+                       const enum e_spice_model_port_type& port_type);
-    void set_port_sizes(const CircuitModelId& circuit_model_id, 
+    void set_port_size(const CircuitModelId& circuit_model_id, 
-                        const CircuitPortId& circuit_port_id, 
+                       const CircuitPortId& circuit_port_id, 
-                        const size_t& port_size);
+                       const size_t& port_size);
     void set_port_prefix(const CircuitModelId& circuit_model_id, 
                          const CircuitPortId& circuit_port_id, 
                          const std::string& port_prefix);
@@ -292,6 +295,9 @@ class CircuitLibrary {
     void set_port_inv_prefix(const CircuitModelId& circuit_model_id, 
                              const CircuitPortId& circuit_port_id, 
                              const std::string& inv_prefix);
+    void set_port_default_value(const CircuitModelId& circuit_model_id, 
+                                const CircuitPortId& circuit_port_id, 
+                                const size_t& default_val);
     void set_port_is_mode_select(const CircuitModelId& circuit_model_id, 
                                  const CircuitPortId& circuit_port_id, 
                                  const bool& is_mode_select);
@@ -349,10 +355,8 @@ class CircuitLibrary {
     /* Buffer/Inverter-related parameters */
     void set_buffer_type(const CircuitModelId& circuit_model_id,
                          const enum e_spice_model_buffer_type& buffer_type);
-    void set_buffer_location_map(const CircuitModelId& circuit_model_id,
-                                 const std::string& location_map);
     void set_buffer_size(const CircuitModelId& circuit_model_id,
-                         const size_t& buffer_size);
+                         const float& buffer_size);
     void set_buffer_num_levels(const CircuitModelId& circuit_model_id,
                                const size_t& num_levels);
     void set_buffer_f_per_stage(const CircuitModelId& circuit_model_id,
@@ -361,9 +365,9 @@ class CircuitLibrary {
     void set_pass_gate_logic_type(const CircuitModelId& circuit_model_id,
                                   const enum e_spice_model_pass_gate_logic_type& pass_gate_logic_type);
     void set_pass_gate_logic_nmos_size(const CircuitModelId& circuit_model_id,
-                                       const size_t& nmos_size);
+                                       const float& nmos_size);
     void set_pass_gate_logic_pmos_size(const CircuitModelId& circuit_model_id,
-                                       const size_t& pmos_size);
+                                       const float& pmos_size);
     /* Multiplexer-related parameters */
     void set_mux_structure(const CircuitModelId& circuit_model_id,
                            const enum e_spice_model_structure& mux_structure);
@@ -378,6 +382,9 @@ class CircuitLibrary {
     /* LUT-related parameters */
     void set_lut_is_fracturable(const CircuitModelId& circuit_model_id,
                                 const bool& is_fracturable);
+    /* Gate-related parameters */
+    void set_gate_type(const CircuitModelId& circuit_model_id,
+                       const enum e_spice_model_gate_type& gate_type);
     /* RRAM-related design technology information */
     void set_rram_rlrs(const CircuitModelId& circuit_model_id,
                        const float& rlrs);
@@ -444,6 +451,7 @@ class CircuitLibrary {
     vtr::vector<CircuitModelId, std::vector<bool>> buffer_existence_;
     vtr::vector<CircuitModelId, std::vector<std::string>> buffer_circuit_model_names_;
     vtr::vector<CircuitModelId, std::vector<CircuitModelId>> buffer_circuit_model_ids_;
+    vtr::vector<CircuitModelId, std::vector<std::string>> buffer_location_maps_;
 
     /* Pass-gate-related parameters */
     vtr::vector<CircuitModelId, std::string> pass_gate_logic_circuit_model_names_;
@@ -456,6 +464,7 @@ class CircuitLibrary {
     vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::string>> port_prefix_;
     vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::string>> port_lib_names_;
     vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::string>> port_inv_prefix_;
+    vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, size_t>> port_default_values_;
     vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, bool>> port_is_mode_select_;
     vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, bool>> port_is_global_;
     vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, bool>> port_is_reset_;
@@ -490,14 +499,13 @@ class CircuitLibrary {
 
     /* Buffer/Inverter-related parameters */
     vtr::vector<CircuitModelId, enum e_spice_model_buffer_type> buffer_types_;
-    vtr::vector<CircuitModelId, std::string> buffer_location_maps_;
+    vtr::vector<CircuitModelId, float> buffer_sizes_;
-    vtr::vector<CircuitModelId, size_t> buffer_sizes_;
     vtr::vector<CircuitModelId, size_t> buffer_num_levels_;
     vtr::vector<CircuitModelId, size_t> buffer_f_per_stage_;
 
     /* Pass-gate-related parameters */
     vtr::vector<CircuitModelId, enum e_spice_model_pass_gate_logic_type> pass_gate_logic_types_;
-    vtr::vector<CircuitModelId, vtr::Point<size_t>> pass_gate_logic_sizes_; /* x=> nmos_size; y => pmos_size */
+    vtr::vector<CircuitModelId, vtr::Point<float>> pass_gate_logic_sizes_; /* x=> nmos_size; y => pmos_size */
 
     /* Multiplexer-related parameters */
     vtr::vector<CircuitModelId, enum e_spice_model_structure> mux_structure_;
@@ -509,6 +517,9 @@ class CircuitLibrary {
     /* LUT-related parameters */
     vtr::vector<CircuitModelId, bool> lut_is_fracturable_;
 
+    /* Gate-related parameters */
+    vtr::vector<CircuitModelId, enum e_spice_model_gate_type> gate_types_;
+
     /* RRAM-related design technology information */
     vtr::vector<CircuitModelId, vtr::Point<float>> rram_res_; /* x => R_LRS, y => R_HRS */
     vtr::vector<CircuitModelId, vtr::Point<float>> wprog_set_; /* x => wprog_set_nmos, y=> wprog_set_pmos */

vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_types.h

@@ -0,0 +1,144 @@
+/**********************************************************
+ * MIT License
+ *
+ * Copyright (c) 2018 LNIS - The University of Utah
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ***********************************************************************/
+
+/************************************************************************
+ * Filename:    circuit_types.h
+ * Created by:   Xifan Tang
+ * Change history:
+ * +-------------------------------------+
+ * |  Date       |    Author   | Notes
+ * +-------------------------------------+
+ * | 2019/08/08  |  Xifan Tang | Created 
+ * +-------------------------------------+
+ ***********************************************************************/
+
+/* IMPORTANT:
+ * The following preprocessing flags are added to 
+ * avoid compilation error when this headers are included in more than 1 times 
+ */
+#ifndef CIRCUIT_TYPES_H
+#define CIRCUIT_TYPES_H
+
+/************************************************************************
+ * This file includes basic enumeration types for circuit models
+ ***********************************************************************/
+/*
+ * Notes in include header files in a head file 
+ * Only include the neccessary header files 
+ * that is required by the data types in the function/class declarations!
+ */
+/* Header files should be included in a sequence */
+/* Standard header files required go first */
+
+enum spice_model_delay_type {
+  SPICE_MODEL_DELAY_RISE, 
+  SPICE_MODEL_DELAY_FALL,
+  NUM_CIRCUIT_MODEL_DELAY_TYPES
+};
+
+/*Struct for a SPICE model of a module*/
+enum e_spice_model_type {
+  SPICE_MODEL_CHAN_WIRE, 
+  SPICE_MODEL_WIRE, 
+  SPICE_MODEL_MUX, 
+  SPICE_MODEL_LUT, 
+  SPICE_MODEL_FF, 
+  SPICE_MODEL_SRAM, 
+  SPICE_MODEL_HARDLOGIC,
+  SPICE_MODEL_SCFF,
+  SPICE_MODEL_IOPAD, 
+  SPICE_MODEL_INVBUF, 
+  SPICE_MODEL_PASSGATE, 
+  SPICE_MODEL_GATE,
+  NUM_CIRCUIT_MODEL_TYPES
+};
+
+enum e_spice_model_design_tech {
+  SPICE_MODEL_DESIGN_CMOS, 
+  SPICE_MODEL_DESIGN_RRAM,
+  NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES
+};
+
+enum e_spice_model_structure {
+  SPICE_MODEL_STRUCTURE_TREE, 
+  SPICE_MODEL_STRUCTURE_ONELEVEL, 
+  SPICE_MODEL_STRUCTURE_MULTILEVEL, 
+  SPICE_MODEL_STRUCTURE_CROSSBAR,
+  NUM_CIRCUIT_MODEL_STRUCTURE_TYPES
+};
+
+enum e_spice_model_buffer_type {
+  SPICE_MODEL_BUF_INV, 
+  SPICE_MODEL_BUF_BUF,
+  NUM_CIRCUIT_MODEL_BUF_TYPES
+};
+
+enum e_spice_model_pass_gate_logic_type {
+  SPICE_MODEL_PASS_GATE_TRANSMISSION, 
+  SPICE_MODEL_PASS_GATE_TRANSISTOR,
+  NUM_CIRCUIT_MODEL_PASS_GATE_TYPES
+};
+
+enum e_spice_model_gate_type {
+  SPICE_MODEL_GATE_AND, 
+  SPICE_MODEL_GATE_OR,
+  SPICE_MODEL_GATE_MUX2,
+  NUM_SPICE_MODEL_GATE_TYPES
+};
+
+enum e_wire_model_type {
+  WIRE_MODEL_PIE,
+  WIRE_MODEL_T,
+  NUM_WIRE_MODEL_TYPES,
+};
+
+enum e_spice_model_port_type {
+  SPICE_MODEL_PORT_INPUT, 
+  SPICE_MODEL_PORT_OUTPUT, 
+  SPICE_MODEL_PORT_INOUT, 
+  SPICE_MODEL_PORT_CLOCK, 
+  SPICE_MODEL_PORT_SRAM,
+  SPICE_MODEL_PORT_BL,
+  SPICE_MODEL_PORT_BLB,
+  SPICE_MODEL_PORT_WL,
+  SPICE_MODEL_PORT_WLB,
+  NUM_CIRCUIT_MODEL_PORT_TYPES
+};
+
+/* For SRAM */
+enum e_sram_orgz {
+  SPICE_SRAM_STANDALONE,   /* SRAMs are organized and accessed as standalone elements */
+  SPICE_SRAM_SCAN_CHAIN,   /* SRAMs are organized and accessed by a scan-chain */
+  SPICE_SRAM_MEMORY_BANK,  /* SRAMs are organized and accessed by memory bank */
+  SPICE_SRAM_LOCAL_ENCODER,  /* SRAMs are organized and accessed by a local encoder */
+  NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES
+};
+
+
+#endif
+
+/************************************************************************
+ * End of file : circuit_types.h
+ ***********************************************************************/
+

vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h

@@ -3,6 +3,7 @@
 
 #include "util.h"
 #include "linkedlist.h"
+#include "circuit_library.h"
 
 /* Xifan TANG: Spice support*/
 enum e_spice_tech_lib_type {
@@ -10,61 +11,6 @@ enum e_spice_tech_lib_type {
   SPICE_LIB_ACADEMIA
 };
 
-enum spice_model_delay_type {
-  SPICE_MODEL_DELAY_RISE, 
-  SPICE_MODEL_DELAY_FALL,
-  NUM_CIRCUIT_MODEL_DELAY_TYPES
-};
-
-/*Struct for a SPICE model of a module*/
-enum e_spice_model_type {
-  SPICE_MODEL_CHAN_WIRE, 
-  SPICE_MODEL_WIRE, 
-  SPICE_MODEL_MUX, 
-  SPICE_MODEL_LUT, 
-  SPICE_MODEL_FF, 
-  SPICE_MODEL_SRAM, 
-  SPICE_MODEL_HARDLOGIC,
-  SPICE_MODEL_SCFF,
-  SPICE_MODEL_IOPAD, 
-  SPICE_MODEL_INVBUF, 
-  SPICE_MODEL_PASSGATE, 
-  SPICE_MODEL_GATE,
-  NUM_CIRCUIT_MODEL_TYPES
-};
-
-enum e_spice_model_design_tech {
-  SPICE_MODEL_DESIGN_CMOS, 
-  SPICE_MODEL_DESIGN_RRAM,
-  NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES
-};
-
-enum e_spice_model_structure {
-  SPICE_MODEL_STRUCTURE_TREE, 
-  SPICE_MODEL_STRUCTURE_ONELEVEL, 
-  SPICE_MODEL_STRUCTURE_MULTILEVEL, 
-  SPICE_MODEL_STRUCTURE_CROSSBAR,
-  NUM_CIRCUIT_MODEL_STRUCTURE_TYPES
-};
-
-enum e_spice_model_buffer_type {
-  SPICE_MODEL_BUF_INV, 
-  SPICE_MODEL_BUF_BUF,
-  NUM_CIRCUIT_MODEL_BUF_TYPES
-};
-
-enum e_spice_model_pass_gate_logic_type {
-  SPICE_MODEL_PASS_GATE_TRANSMISSION, 
-  SPICE_MODEL_PASS_GATE_TRANSISTOR,
-  NUM_CIRCUIT_MODEL_PASS_GATE_TYPES
-};
-
-enum e_spice_model_gate_type {
-  SPICE_MODEL_GATE_AND, 
-  SPICE_MODEL_GATE_OR,
-  SPICE_MODEL_GATE_MUX2
-};
-
 /* Transistor-level basic informations*/
 enum e_spice_trans_type {
   SPICE_TRANS_NMOS, 
@@ -73,25 +19,6 @@ enum e_spice_trans_type {
   SPICE_TRANS_IO_PMOS
 };
 
-enum e_wire_model_type {
-  WIRE_MODEL_PIE,
-  WIRE_MODEL_T,
-  NUM_WIRE_MODEL_TYPES,
-};
-
-enum e_spice_model_port_type {
-  SPICE_MODEL_PORT_INPUT, 
-  SPICE_MODEL_PORT_OUTPUT, 
-  SPICE_MODEL_PORT_INOUT, 
-  SPICE_MODEL_PORT_CLOCK, 
-  SPICE_MODEL_PORT_SRAM,
-  SPICE_MODEL_PORT_BL,
-  SPICE_MODEL_PORT_BLB,
-  SPICE_MODEL_PORT_WL,
-  SPICE_MODEL_PORT_WLB,
-  NUM_CIRCUIT_MODEL_PORT_TYPES
-};
-
 /* For process corner */
 enum e_process_corner {
  BEST_CORNER,
@@ -99,15 +26,6 @@ enum e_process_corner {
  WORST_CORNER
 };
 
-/* For SRAM */
-enum e_sram_orgz {
-  SPICE_SRAM_STANDALONE,   /* SRAMs are organized and accessed as standalone elements */
-  SPICE_SRAM_SCAN_CHAIN,   /* SRAMs are organized and accessed by a scan-chain */
-  SPICE_SRAM_MEMORY_BANK,  /* SRAMs are organized and accessed by memory bank */
-  SPICE_SRAM_LOCAL_ENCODER,  /* SRAMs are organized and accessed by a local encoder */
-  NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES
-};
-
 enum e_spice_accuracy_type {
   SPICE_FRAC, SPICE_ABS
 };
@@ -450,6 +368,8 @@ struct s_spice {
   t_spice_tech_lib tech_lib;
   int num_spice_model;
   t_spice_model* spice_models;
+  /* Circuit library, object to replace the legacy spice_models */
+  CircuitLibrary circuit_lib;
 };
 
 /* Information needed to build a Multiplexer architecture*/

vpr7_x2p/libarchfpga/SRC/read_xml_spice.c

@@ -10,6 +10,8 @@
 #include "read_xml_spice_util.h"
 #include "read_xml_spice.h"
 
+#include "circuit_library.h"
+
 /*********** Subroutines Declaration (only called in this source file) **********/
 static void ProcessSpiceMeasParams(ezxml_t Parent,
                                    t_spice_meas_params* meas_params);
@@ -768,6 +770,8 @@ static void ProcessSpiceModelPort(ezxml_t Node,
     ||(SPICE_MODEL_PORT_WLB == port->type)) {
     port->inv_spice_model_name = my_strdup(FindProperty(Node, "inv_circuit_model_name", FALSE));
     ezxml_set_attr(Node, "inv_circuit_model_name", NULL);
+  } else {
+    port->inv_spice_model_name = NULL;
   }
 
   /* Add a feature to enable/disable the configuration encoders for multiplexers */
@@ -914,6 +918,13 @@ static void ProcessSpiceModel(ezxml_t Parent,
  
   /* Check the design technology settings*/
   Node = ezxml_child(Parent, "design_technology");
+  /* Initialize */
+  spice_model->design_tech_info.buffer_info = NULL;
+  spice_model->design_tech_info.pass_gate_info = NULL;
+  spice_model->design_tech_info.rram_info = NULL;
+  spice_model->design_tech_info.mux_info = NULL;
+  spice_model->design_tech_info.lut_info = NULL;
+  spice_model->design_tech_info.gate_info = NULL;
   if (Node) {
     /* Specify if this spice_model is power gated or not*/
     spice_model->design_tech_info.power_gated = GetBooleanProperty(Node,"power_gated", FALSE, FALSE);
@@ -941,7 +952,7 @@ static void ProcessSpiceModel(ezxml_t Parent,
     } else if (0 == strcmp(FindProperty(Node,"type",TRUE),"rram")) {
       spice_model->design_tech = SPICE_MODEL_DESIGN_RRAM;
       /* Malloc RRAM info */
-      spice_model->design_tech_info.rram_info = (t_spice_model_rram*)my_malloc(sizeof(t_spice_model_rram));
+      spice_model->design_tech_info.rram_info = (t_spice_model_rram*)my_calloc(1, sizeof(t_spice_model_rram));
       /* Fill information */
       ProcessSpiceModelRRAM(Node, spice_model->design_tech_info.rram_info);
     } else {
@@ -955,7 +966,7 @@ static void ProcessSpiceModel(ezxml_t Parent,
     spice_model->design_tech_info.mux_info = NULL;
     if (SPICE_MODEL_MUX == spice_model->type) {
       /* Malloc */
-      spice_model->design_tech_info.mux_info = (t_spice_model_mux*)my_malloc(sizeof(t_spice_model_mux));
+      spice_model->design_tech_info.mux_info = (t_spice_model_mux*)my_calloc(1, sizeof(t_spice_model_mux));
       /* Fill information */
       ProcessSpiceModelMUX(Node, spice_model, spice_model->design_tech_info.mux_info);
     }
@@ -964,11 +975,11 @@ static void ProcessSpiceModel(ezxml_t Parent,
     spice_model->design_tech_info.lut_info = NULL;
     if (SPICE_MODEL_LUT == spice_model->type) {
       /* Malloc */
-      spice_model->design_tech_info.lut_info = (t_spice_model_lut*)my_malloc(sizeof(t_spice_model_lut));
+      spice_model->design_tech_info.lut_info = (t_spice_model_lut*)my_calloc(1, sizeof(t_spice_model_lut));
       /* Fill information */
       ProcessSpiceModelLUT(Node, spice_model->design_tech_info.lut_info);
       /* Malloc */
-      spice_model->design_tech_info.mux_info = (t_spice_model_mux*)my_malloc(sizeof(t_spice_model_mux));
+      spice_model->design_tech_info.mux_info = (t_spice_model_mux*)my_calloc(1, sizeof(t_spice_model_mux));
       /* Fill information */
       /* Default: tree, no const_inputs */
       spice_model->design_tech_info.mux_info->structure = SPICE_MODEL_STRUCTURE_TREE;
@@ -1041,7 +1052,7 @@ static void ProcessSpiceModel(ezxml_t Parent,
   spice_model->input_buffer = NULL;
   if (Node) {
     /*Alloc*/
-    spice_model->input_buffer = (t_spice_model_buffer*)my_malloc(sizeof(t_spice_model_buffer));
+    spice_model->input_buffer = (t_spice_model_buffer*)my_calloc(1, sizeof(t_spice_model_buffer));
     ProcessSpiceModelBuffer(Node,spice_model->input_buffer);
     FreeNode(Node);
   } else if (SPICE_MODEL_INVBUF != spice_model->type) {
@@ -1053,7 +1064,7 @@ static void ProcessSpiceModel(ezxml_t Parent,
   Node = ezxml_child(Parent, "output_buffer");
   spice_model->output_buffer = NULL;
   if (Node) {
-    spice_model->output_buffer = (t_spice_model_buffer*)my_malloc(sizeof(t_spice_model_buffer));
+    spice_model->output_buffer = (t_spice_model_buffer*)my_calloc(1, sizeof(t_spice_model_buffer));
     ProcessSpiceModelBuffer(Node,spice_model->output_buffer);
     FreeNode(Node);
   } else if (SPICE_MODEL_INVBUF != spice_model->type) {
@@ -1066,7 +1077,7 @@ static void ProcessSpiceModel(ezxml_t Parent,
   Node = ezxml_child(Parent, "pass_gate_logic");
   spice_model->pass_gate_logic = NULL;
   if (Node) {
-    spice_model->pass_gate_logic = (t_spice_model_pass_gate_logic*)my_malloc(sizeof(t_spice_model_pass_gate_logic));
+    spice_model->pass_gate_logic = (t_spice_model_pass_gate_logic*)my_calloc(1, sizeof(t_spice_model_pass_gate_logic));
     /* Find spice_model_name */
     spice_model->pass_gate_logic->spice_model_name = my_strdup(FindProperty(Node, "circuit_model_name", TRUE));
 	ezxml_set_attr(Node, "circuit_model_name", NULL);
@@ -1082,7 +1093,7 @@ static void ProcessSpiceModel(ezxml_t Parent,
   /* Find All the ports*/
   spice_model->num_port = CountChildren(Parent, "port", 1);
   /*Alloc*/
-  spice_model->ports = (t_spice_model_port*)my_malloc(spice_model->num_port*sizeof(t_spice_model_port));
+  spice_model->ports = (t_spice_model_port*)my_calloc(spice_model->num_port, sizeof(t_spice_model_port));
   /* Assign each found spice model*/
   for (iport = 0; iport < spice_model->num_port; iport++) {
     Cur = FindFirstElement(Parent, "port", TRUE);
@@ -1091,8 +1102,9 @@ static void ProcessSpiceModel(ezxml_t Parent,
   }
 
   /* Read in wire parameters */
+  spice_model->wire_param = NULL;
   if ((SPICE_MODEL_CHAN_WIRE == spice_model->type)||(SPICE_MODEL_WIRE == spice_model->type)) {
-    spice_model->wire_param = (t_spice_model_wire_param*)my_malloc(sizeof(t_spice_model_wire_param));
+    spice_model->wire_param = (t_spice_model_wire_param*)my_calloc(1, sizeof(t_spice_model_wire_param));
     Node = ezxml_child(Parent, "wire_param");
     if (Node) {
       ProcessSpiceModelWireParam(Node,spice_model->wire_param);
@@ -1107,7 +1119,7 @@ static void ProcessSpiceModel(ezxml_t Parent,
   /* Find delay info */
   spice_model->num_delay_info = CountChildren(Parent, "delay_matrix", 0);
   /*Alloc*/
-  spice_model->delay_info = (t_spice_model_delay_info*) my_malloc(spice_model->num_delay_info * sizeof(t_spice_model_delay_info));
+  spice_model->delay_info = (t_spice_model_delay_info*) my_calloc(spice_model->num_delay_info, sizeof(t_spice_model_delay_info));
   /* Assign each found spice model*/
   for (i = 0; i < spice_model->num_delay_info; i++) {
     Cur = FindFirstElement(Parent, "delay_matrix", TRUE);
@@ -1508,6 +1520,232 @@ static void ProcessSpiceTechLibTransistors(ezxml_t Parent,
   return;
 }
 
+/* Build a circuit library based on the spice_models 
+ * This function does a quick conversion, so that we can proceed to update the downstream codes
+ * TODO: The circuit library should be incrementally built during XML parsing
+ * when the downstream is updated, the legacy spice_models will be removed 
+ */
+static 
+CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_models) {
+  CircuitLibrary circuit_lib;
+
+  /* Go spice_model by spice_model */
+  for (int imodel = 0; imodel < num_spice_model; ++imodel) {
+    /* Add a spice model to the circuit_lib */
+    CircuitModelId model_id = circuit_lib.add_circuit_model();
+    /* Fill fundamental attributes */
+    /* Basic information*/
+    circuit_lib.set_circuit_model_type(model_id, spice_models[imodel].type);
+
+    std::string name(spice_models[imodel].name); 
+    circuit_lib.set_circuit_model_name(model_id, name);
+
+    std::string prefix(spice_models[imodel].prefix); 
+    circuit_lib.set_circuit_model_prefix(model_id, prefix);
+
+    if (NULL != spice_models[imodel].verilog_netlist) {
+      std::string verilog_netlist(spice_models[imodel].verilog_netlist); 
+      circuit_lib.set_circuit_model_verilog_netlist(model_id, verilog_netlist);
+    }
+    
+    if (NULL != spice_models[imodel].model_netlist) {
+      std::string spice_netlist(spice_models[imodel].model_netlist); 
+      circuit_lib.set_circuit_model_spice_netlist(model_id, spice_netlist);
+    }
+
+    circuit_lib.set_circuit_model_is_default(model_id, 0 != spice_models[imodel].is_default);
+
+    /* Verilog generatioin options */
+    circuit_lib.set_circuit_model_dump_structural_verilog(model_id, TRUE == spice_models[imodel].dump_structural_verilog);
+
+    circuit_lib.set_circuit_model_dump_explicit_port_map(model_id, TRUE == spice_models[imodel].dump_explicit_port_map);
+
+    /* Design technology information */
+    circuit_lib.set_circuit_model_design_tech_type(model_id, spice_models[imodel].design_tech);
+
+    circuit_lib.set_circuit_model_is_power_gated(model_id, TRUE == spice_models[imodel].design_tech_info.power_gated);
+
+    /* Buffer linking information */
+    if (NULL != spice_models[imodel].input_buffer) {
+      std::string model_name;
+      if (NULL != spice_models[imodel].input_buffer->spice_model_name) {
+        model_name = spice_models[imodel].input_buffer->spice_model_name;
+      }
+      circuit_lib.set_circuit_model_input_buffer(model_id, 0 != spice_models[imodel].input_buffer->exist, model_name);
+    }
+    if (NULL != spice_models[imodel].output_buffer) {
+      std::string model_name;
+      if (NULL != spice_models[imodel].output_buffer->spice_model_name) {
+        model_name = spice_models[imodel].output_buffer->spice_model_name;
+      }
+      circuit_lib.set_circuit_model_output_buffer(model_id, 0 != spice_models[imodel].output_buffer->exist, model_name);
+    }
+    if (NULL != spice_models[imodel].lut_input_buffer) {
+      std::string model_name;
+      if (NULL != spice_models[imodel].lut_input_buffer->spice_model_name) {
+        model_name = spice_models[imodel].lut_input_buffer->spice_model_name;
+      }
+      circuit_lib.set_circuit_model_lut_input_buffer(model_id, 0 != spice_models[imodel].lut_input_buffer->exist, model_name);
+    }
+    if (NULL != spice_models[imodel].lut_input_inverter) {
+      std::string model_name;
+      if (NULL != spice_models[imodel].lut_input_inverter->spice_model_name) {
+        model_name = spice_models[imodel].lut_input_inverter->spice_model_name;
+      }
+      circuit_lib.set_circuit_model_lut_input_inverter(model_id, 0 != spice_models[imodel].lut_input_inverter->exist, model_name);
+    }
+    if (NULL != spice_models[imodel].lut_intermediate_buffer) {
+      std::string model_name;
+      if (NULL != spice_models[imodel].lut_intermediate_buffer->spice_model_name) {
+        model_name = spice_models[imodel].lut_intermediate_buffer->spice_model_name;
+      }
+      circuit_lib.set_circuit_model_lut_intermediate_buffer(model_id, 0 != spice_models[imodel].lut_intermediate_buffer->exist, model_name);
+
+      std::string model_location_map;
+      if (NULL != spice_models[imodel].lut_intermediate_buffer->location_map) {
+        model_location_map = spice_models[imodel].lut_intermediate_buffer->location_map;
+      }
+      circuit_lib.set_circuit_model_lut_intermediate_buffer_location_map(model_id, model_location_map);
+    }
+
+    /* Pass-gate-logic linking information */
+    if (NULL != spice_models[imodel].pass_gate_logic) {
+      std::string model_name(spice_models[imodel].pass_gate_logic->spice_model_name);
+      circuit_lib.set_circuit_model_pass_gate_logic(model_id, model_name); 
+    }
+
+    /* Buffer information */
+    if (NULL != spice_models[imodel].design_tech_info.buffer_info) {
+      circuit_lib.set_buffer_type(model_id, spice_models[imodel].design_tech_info.buffer_info->type);
+      circuit_lib.set_buffer_size(model_id, spice_models[imodel].design_tech_info.buffer_info->size);
+      if (TRUE == spice_models[imodel].design_tech_info.buffer_info->tapered_buf) {
+        circuit_lib.set_buffer_num_levels(model_id, spice_models[imodel].design_tech_info.buffer_info->tap_buf_level);
+        circuit_lib.set_buffer_f_per_stage(model_id, spice_models[imodel].design_tech_info.buffer_info->f_per_stage);
+      }
+    }
+
+    /* Pass-gate information */
+    if (NULL != spice_models[imodel].design_tech_info.pass_gate_info) {
+      circuit_lib.set_pass_gate_logic_type(model_id, spice_models[imodel].design_tech_info.pass_gate_info->type);
+      circuit_lib.set_pass_gate_logic_nmos_size(model_id, spice_models[imodel].design_tech_info.pass_gate_info->nmos_size);
+      circuit_lib.set_pass_gate_logic_pmos_size(model_id, spice_models[imodel].design_tech_info.pass_gate_info->pmos_size);
+    }
+
+    /* Multiplexer information */
+    if (NULL != spice_models[imodel].design_tech_info.mux_info) {
+      circuit_lib.set_mux_structure(model_id, spice_models[imodel].design_tech_info.mux_info->structure);
+      circuit_lib.set_mux_num_levels(model_id, spice_models[imodel].design_tech_info.mux_info->mux_num_level);
+      if (TRUE == spice_models[imodel].design_tech_info.mux_info->add_const_input) {
+        circuit_lib.set_mux_const_input_value(model_id, spice_models[imodel].design_tech_info.mux_info->const_input_val);
+      }
+      circuit_lib.set_mux_use_local_encoder(model_id, TRUE == spice_models[imodel].design_tech_info.mux_info->local_encoder);
+      circuit_lib.set_mux_use_advanced_rram_design(model_id, TRUE == spice_models[imodel].design_tech_info.mux_info->advanced_rram_design);
+    }
+
+    /* LUT information */
+    if (NULL != spice_models[imodel].design_tech_info.lut_info) {
+      circuit_lib.set_lut_is_fracturable(model_id, TRUE == spice_models[imodel].design_tech_info.lut_info->frac_lut);
+    }
+
+    /* Gate information */
+    if (NULL != spice_models[imodel].design_tech_info.gate_info) {
+      circuit_lib.set_gate_type(model_id, spice_models[imodel].design_tech_info.gate_info->type);
+    }
+
+    /* RRAM information */
+    if (NULL != spice_models[imodel].design_tech_info.rram_info) {
+      circuit_lib.set_rram_rlrs(model_id, spice_models[imodel].design_tech_info.rram_info->ron);
+      circuit_lib.set_rram_rhrs(model_id, spice_models[imodel].design_tech_info.rram_info->roff);
+      circuit_lib.set_rram_wprog_set_nmos(model_id, spice_models[imodel].design_tech_info.rram_info->wprog_set_nmos);
+      circuit_lib.set_rram_wprog_set_pmos(model_id, spice_models[imodel].design_tech_info.rram_info->wprog_set_pmos);
+      circuit_lib.set_rram_wprog_reset_nmos(model_id, spice_models[imodel].design_tech_info.rram_info->wprog_reset_nmos);
+      circuit_lib.set_rram_wprog_reset_pmos(model_id, spice_models[imodel].design_tech_info.rram_info->wprog_reset_pmos);
+    }
+
+    /* Delay information */
+    for (int idelay = 0; idelay < spice_models[imodel].num_delay_info; ++idelay) {
+      circuit_lib.add_delay_info(model_id, spice_models[imodel].delay_info[idelay].type);
+      
+      std::string in_port_names(spice_models[imodel].delay_info[idelay].in_port_name);
+      circuit_lib.set_delay_in_port_names(model_id, spice_models[imodel].delay_info[idelay].type, in_port_names);
+
+      std::string out_port_names(spice_models[imodel].delay_info[idelay].out_port_name);
+      circuit_lib.set_delay_out_port_names(model_id, spice_models[imodel].delay_info[idelay].type, out_port_names);
+      
+      std::string delay_values(spice_models[imodel].delay_info[idelay].value);
+      circuit_lib.set_delay_values(model_id, spice_models[imodel].delay_info[idelay].type, delay_values);
+    } 
+
+    /* Wire parameters */
+    if (NULL != spice_models[imodel].wire_param) {
+      circuit_lib.set_wire_type(model_id, spice_models[imodel].wire_param->type);
+      circuit_lib.set_wire_r(model_id, spice_models[imodel].wire_param->res_val);
+      circuit_lib.set_wire_c(model_id, spice_models[imodel].wire_param->cap_val);
+      circuit_lib.set_wire_num_levels(model_id, spice_models[imodel].wire_param->level);
+    }
+
+    /* Ports */
+    for (int iport = 0; iport < spice_models[imodel].num_port; ++iport) {
+      CircuitPortId port_id = circuit_lib.add_circuit_model_port(model_id);
+      /* Fill fundamental attributes */
+      circuit_lib.set_port_type(model_id, port_id, spice_models[imodel].ports[iport].type);
+
+      circuit_lib.set_port_size(model_id, port_id, spice_models[imodel].ports[iport].size);
+
+      std::string port_prefix(spice_models[imodel].ports[iport].prefix);
+      circuit_lib.set_port_prefix(model_id, port_id, port_prefix);
+
+      std::string port_lib_name(spice_models[imodel].ports[iport].lib_name);
+      circuit_lib.set_port_lib_name(model_id, port_id, port_lib_name);
+      
+      if (NULL != spice_models[imodel].ports[iport].inv_prefix) {
+        std::string port_inv_prefix(spice_models[imodel].ports[iport].inv_prefix);
+        circuit_lib.set_port_inv_prefix(model_id, port_id, port_inv_prefix);
+      }
+
+      circuit_lib.set_port_default_value(model_id, port_id, spice_models[imodel].ports[iport].default_val);
+
+      circuit_lib.set_port_is_mode_select(model_id, port_id, TRUE == spice_models[imodel].ports[iport].mode_select);
+      circuit_lib.set_port_is_global(model_id, port_id, TRUE == spice_models[imodel].ports[iport].is_global);
+      circuit_lib.set_port_is_reset(model_id, port_id, TRUE == spice_models[imodel].ports[iport].is_reset);
+      circuit_lib.set_port_is_set(model_id, port_id, TRUE == spice_models[imodel].ports[iport].is_set);
+      circuit_lib.set_port_is_config_enable(model_id, port_id, TRUE == spice_models[imodel].ports[iport].is_config_enable);
+      circuit_lib.set_port_is_prog(model_id, port_id, TRUE == spice_models[imodel].ports[iport].is_prog);
+
+      if (NULL != spice_models[imodel].ports[iport].spice_model_name) {
+        std::string port_model_name(spice_models[imodel].ports[iport].spice_model_name);
+        circuit_lib.set_port_circuit_model_name(model_id, port_id, port_model_name);
+      }
+
+      if (NULL != spice_models[imodel].ports[iport].inv_spice_model_name) {
+        std::string port_inv_model_name(spice_models[imodel].ports[iport].inv_spice_model_name);
+        circuit_lib.set_port_inv_circuit_model_name(model_id, port_id, port_inv_model_name);
+      }
+
+      if (NULL != spice_models[imodel].ports[iport].tri_state_map) {
+        std::string port_tri_state_map(spice_models[imodel].ports[iport].tri_state_map);
+        circuit_lib.set_port_tri_state_map(model_id, port_id, port_tri_state_map);
+      }
+
+      if (SPICE_MODEL_LUT == spice_models[imodel].type) {
+        circuit_lib.set_port_lut_frac_level(model_id, port_id, spice_models[imodel].ports[iport].lut_frac_level);
+
+        std::vector<size_t> port_lut_output_mask;
+        for (int ipin = 0; ipin < spice_models[imodel].ports[iport].size; ++ipin) {
+          port_lut_output_mask.push_back(spice_models[imodel].ports[iport].lut_output_mask[ipin]);
+        }
+        circuit_lib.set_port_lut_output_mask(model_id, port_id, port_lut_output_mask);
+      }
+
+      if (SPICE_MODEL_PORT_SRAM == spice_models[imodel].ports[iport].type) {
+        circuit_lib.set_port_sram_orgz(model_id, port_id, spice_models[imodel].ports[iport].organization);
+      }
+    } 
+  }
+
+  return circuit_lib;
+}
+
 /* Process the SPICE Settings*/
 void ProcessSpiceSettings(ezxml_t Parent,
                           t_spice* spice) {
@@ -1541,6 +1779,8 @@ void ProcessSpiceSettings(ezxml_t Parent,
     assert(imodel == spice->num_spice_model);
     FreeNode(Node);
   }
+  /* Build the CircuitLibrary here from spice_models */
+  spice->circuit_lib = build_circuit_library(spice->num_spice_model, spice->spice_models);
  
   /* Check codes*/
   check_tech_lib(spice->tech_lib, spice->num_spice_model, spice->spice_models);