From 1566a5558ac23074e5dc071773b38a8332bcae66 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 16 Apr 2021 16:10:31 -0600 Subject: [PATCH] [Test] Add task configuration file for iwls2005 --- .../benchmark_sweep/iwls2005/config/task.conf | 103 ++++++++++++++++++ 1 file changed, 103 insertions(+) create mode 100644 openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf diff --git a/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf new file mode 100644 index 000000000..60eaeec4a --- /dev/null +++ b/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf @@ -0,0 +1,103 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +# Yosys script parameters +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_cell_sim.v +yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt +yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v +yosys_dsp_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v +yosys_dsp_map_parameters=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_36x36 +# VPR parameters +# Use a fixed routing channel width to save runtime +vpr_route_chan_width=300 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml + +[BENCHMARKS] +# RTL netlists from IWLS 2005 benchmark release +# Comment out due to DFF synthesis problems +#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/*.v +#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/*.v +#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/*.v +#bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/simple_spi/rtl/*.v +# Comment out due to VHDL is not supported by Yosys without Verific +#bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/steppermotordrive/rtl/*.vhd +bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/tv80/rtl/*.v +# Comment out due to DFF synthesis problems +#bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/*.v +# AES core has two top modules that can be tested: encryption and decryption +# Synthesis is too long; skip it +#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/*.v +#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/*.v +#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/fpu/rtl/*.v +# Comment out due to DFF synthesis problems +#bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/pci/rtl/*.v +#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/spi/rtl/*.v +#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/*.v +bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/*.v +# Comment out due to DFF synthesis problems +#bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/*.v +## DES has two versions: area-optimized and performance optimized +bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/*.v +bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/*.v +# Comment out due to DFF synthesis problems +#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/i2c/rtl/*.v +# Comment out due to DFF synthesis problems +#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/sasc/rtl/*.v +bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ss_pcm/rtl/*.v +# Comment out due to DFF synthesis problems +#bench20=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/*.v +bench21=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/usb_phy/rtl/*.v +# Comment out due to DFF synthesis problems +#bench22=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/*.v + +[SYNTHESIS_PARAM] +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys +bench0_top = ac97_top +bench1_top = eth_top +bench2_top = mc_top +bench3_top = simple_spi_top +bench4_top = StepperMotorPorts +bench5_top = tv80s +bench6_top = vga_enh_top +bench7_top = aes_cipher_top +bench8_top = aes_inv_cipher_top +bench9_top = fpu +bench10_top = pci_bridge32 +bench11_top = spi_top +bench12_top = aes +bench13_top = usbf_top +bench14_top = wb_conmax_top +# Not sure either des or des3 is the top module. Need further investigation +bench15_top = des +bench16_top = des3 +bench17_top = i2c_master_top +bench18_top = sasc_top +bench19_top = pcm_slv_top +# May conflict with the top module name with other 'des' benchmark; This is a bug of openfpga flow scripts +bench20_top = des +bench21_top = usb_phy +bench22_top = wb_dma_top + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist=