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[OpoenFPGA Tool] Bug fix for smart fast configuration

This commit is contained in:
tangxifan 2020-09-23 21:38:42 -06:00
parent c2c37d7555
commit 154c9045f6
1 changed files with 4 additions and 1 deletions
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5
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
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@ -1536,10 +1536,13 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp,
std::vector<CircuitPortId> global_prog_reset_ports;
std::vector<CircuitPortId> global_prog_set_ports;
for (const CircuitPortId& global_port : global_ports) {
if (false == circuit_lib.port_is_reset(global_port)) {
continue;
}
VTR_ASSERT(true == circuit_lib.port_is_global(global_port));
VTR_ASSERT( (false == circuit_lib.port_is_reset(global_port))
|| (false == circuit_lib.port_is_reset(global_port)));
if (true == circuit_lib.port_is_reset(global_port)) {
if (true == circuit_lib.port_is_prog(global_port)) {
global_prog_reset_ports.push_back(global_port);
}
if (true == circuit_lib.port_is_set(global_port)) {