From 5cd7567e8fd119dcfc75553a8f3bca7b2b2ee793 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 23 Feb 2022 00:02:04 +0000 Subject: [PATCH 01/16] Updated Patch Count --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 17d852fa5..4da29560b 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -53,7 +53,7 @@ set_property(CACHE VPR_USE_EZGL PROPERTY STRINGS auto off on) # Version number set(OPENFPGA_VERSION_MAJOR 1) set(OPENFPGA_VERSION_MINOR 1) -set(OPENFPGA_VERSION_PATCH 2) +set(OPENFPGA_VERSION_PATCH 8) set(OPENFPGA_VERSION_PRERELEASE "dev") # Include user-defined functions From 086642d13474a2768a5ad312b2014a673be968d5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Feb 2022 15:33:24 -0800 Subject: [PATCH 02/16] [FPGA-Verilog] Now preconfigured wrapper can handle config_enable signals correctly --- openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index fba957963..7c6862380 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -235,6 +235,10 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp, } else { VTR_ASSERT_SAFE(std::string(PIN_CONSTRAINT_OPEN_NET) == constrained_net_name); std::vector default_values(module_global_pin.get_width(), fabric_global_ports.global_port_default_value(global_port_id)); + /* For configuration done signals, we should enable them in preconfigured wrapper */ + if (fabric_global_ports.global_port_is_config_enable(global_port_id)) { + default_values.resize(module_global_pin.get_width(), 1 - fabric_global_ports.global_port_default_value(global_port_id)); + } print_verilog_wire_constant_values(fp, module_global_pin, default_values); } } From 123bb70cb361ad4ce6dd761c571c2063cb14c672 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Feb 2022 15:53:58 -0800 Subject: [PATCH 03/16] [Doc] More explanantion on the use of config_enable attribute for circuit ports --- docs/source/manual/arch_lang/circuit_library.rst | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/docs/source/manual/arch_lang/circuit_library.rst b/docs/source/manual/arch_lang/circuit_library.rst index 726d29c56..4ec803f99 100644 --- a/docs/source/manual/arch_lang/circuit_library.rst +++ b/docs/source/manual/arch_lang/circuit_library.rst @@ -195,7 +195,17 @@ A circuit model may consist of a number of ports. The port list is mandatory in - ``is_reset="true|false"`` Specify if this port controls a reset signal. All the reset ports are connected to a global reset voltage stimuli in testbenches. - - ``is_config_enable="true|false"`` Specify if this port controls a configuration-enable signal. Only valid when ``is_global`` is ``true``. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the ``config_enable`` ports are connected to global configuration-enable voltage stimuli in testbenches. + - ``is_config_enable="true|false"`` Specify if this port controls a configuration-enable signal. Only valid when ``is_global`` is ``true``. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the ``config_enable`` ports are connected to global configuration-enable voltage stimuli in testbenches. + + .. note:: This attribute is used by testbench generators (see :ref:`fpga_verilog_testbench`) + + - In full testbench, + + - There is a ``config_done`` signal, which stay at logic ``0`` during bitstream loading phase, and is pulled up to logic ``1`` during operating phase + - When ``default_value="0"``, the port will be wired to a ``config_done`` signal. + - When ``default_value="1"``, the port will be wired to an inverted ``config_done`` signal. + + - In preconfigured wrapper, the port will be set to the inversion of ``default_value``, as the preconfigured testbenches consider operating phase only. .. note:: ``is_set``, ``is_reset`` and ``is_config_enable`` are only valid when ``is_global`` is ``true``. From 245c7b1e4508e6c0197b26e5b5123a6e359be4e2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Feb 2022 16:02:00 -0800 Subject: [PATCH 04/16] [Test] Add a new test case to validate config enable signal in preconfigured testbenches --- .../config/task.conf | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_enable_scff/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_enable_scff/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_enable_scff/config/task.conf new file mode 100644 index 000000000..6b55acd3e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_enable_scff/config/task.conf @@ -0,0 +1,44 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgscff_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From cf31879b2086f4659f2c7a6286cba533067b3ca2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Feb 2022 16:03:56 -0800 Subject: [PATCH 05/16] [Test] Deploy new test to basic regression tests --- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index bab6c6256..69e8cf4fb 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -23,6 +23,7 @@ run-task basic_tests/full_testbench/fast_configuration_chain_use_set --debug --s run-task basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs run-task basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs +run-task basic_tests/preconfig_testbench/configuration_chain_config_enable_scff --debug --show_thread_logs run-task basic_tests/preconfig_testbench/configuration_chain_no_time_stamp --debug --show_thread_logs echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; From b27a04eb24eac0bc71848216d5069846392b82fd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Feb 2022 22:07:11 -0800 Subject: [PATCH 06/16] [Test] Now test case has a config done CCFF --- .../k4_N4_40nm_cc_cfgdscff_openfpga.xml | 195 ++++++++++++++++++ .../openfpga_cell_library/verilog/dff.v | 44 ++++ .../regression_test_scripts/basic_reg_test.sh | 2 +- .../config/task.conf | 2 +- 4 files changed, 241 insertions(+), 2 deletions(-) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscff_openfpga.xml rename openfpga_flow/tasks/basic_tests/preconfig_testbench/{configuration_chain_config_enable_scff => configuration_chain_config_done_scff}/config/task.conf (97%) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscff_openfpga.xml new file mode 100644 index 000000000..6526bdd75 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscff_openfpga.xml @@ -0,0 +1,195 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_cell_library/verilog/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v index 07c22ea7c..9413ee2c7 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/dff.v +++ b/openfpga_flow/openfpga_cell_library/verilog/dff.v @@ -438,6 +438,50 @@ assign QN = !Q; endmodule //End Of Module +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +// - scan-chain input +// - a scan-chain enable +// - a configure enable, when enabled the registered output will +// be released to the CFGQ +// - a configure done, when enable, the regsitered output will be released to the Q +//----------------------------------------------------- +module CFGDSDFFR ( + input RST, // Reset input + input CK, // Clock Input + input SE, // Scan-chain Enable + input D, // Data Input + input SI, // Scan-chain input + input CFGE, // Configure enable + input CFG_DONE, // Configure done + output Q, // Regular Q output + output CFGQ, // Data Q output which is released when configure enable is activated + output CFGQN // Data Qb output which is released when configure enable is activated +); +//------------Internal Variables-------- +reg q_reg; +wire QN; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST) +if (RST) begin + q_reg <= 1'b0; +end else if (SE) begin + q_reg <= SI; +end else begin + q_reg <= D; +end + +assign CFGQ = CFGE ? Q : 1'b0; +assign CFGQN = CFGE ? QN : 1'b1; + +assign Q = CFG_DONE ? q_reg : 1'b0; +assign QN = CFG_DONE ? !Q : 1'b1; + +endmodule //End Of Module + + //----------------------------------------------------- // Function : D-type flip-flop with // - asynchronous active high reset diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 69e8cf4fb..ca6f9e1ab 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -23,7 +23,7 @@ run-task basic_tests/full_testbench/fast_configuration_chain_use_set --debug --s run-task basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs run-task basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs -run-task basic_tests/preconfig_testbench/configuration_chain_config_enable_scff --debug --show_thread_logs +run-task basic_tests/preconfig_testbench/configuration_chain_config_done_scff --debug --show_thread_logs run-task basic_tests/preconfig_testbench/configuration_chain_no_time_stamp --debug --show_thread_logs echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; diff --git a/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_enable_scff/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_done_scff/config/task.conf similarity index 97% rename from openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_enable_scff/config/task.conf rename to openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_done_scff/config/task.conf index 6b55acd3e..328d008fc 100644 --- a/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_enable_scff/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_done_scff/config/task.conf @@ -17,7 +17,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgscff_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscff_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] From e443a4567d4cef54cc62d5ea803eba70d0bc86f6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Feb 2022 22:09:26 -0800 Subject: [PATCH 07/16] [Arch] Typo --- .../openfpga_arch/k4_N4_40nm_cc_cfgdscff_openfpga.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscff_openfpga.xml index 6526bdd75..2d2bcb9ec 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscff_openfpga.xml @@ -157,13 +157,13 @@ - + - + From 235887e03a92072c44cbe5335682b14e06754767 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Feb 2022 22:35:23 -0800 Subject: [PATCH 08/16] [FPGA-Verilog] Fixed a bug on config-enable signals --- openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index 7c6862380..aaec1ceb7 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -237,6 +237,8 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp, std::vector default_values(module_global_pin.get_width(), fabric_global_ports.global_port_default_value(global_port_id)); /* For configuration done signals, we should enable them in preconfigured wrapper */ if (fabric_global_ports.global_port_is_config_enable(global_port_id)) { + VTR_LOG("Config-enable port '%s' is detected with default value '%ld'", module_global_pin.get_name().c_str(), fabric_global_ports.global_port_default_value(global_port_id)); + default_values.clear(); default_values.resize(module_global_pin.get_width(), 1 - fabric_global_ports.global_port_default_value(global_port_id)); } print_verilog_wire_constant_values(fp, module_global_pin, default_values); From d51557e0161db0a88a42025559998f385f94a24a Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Thu, 24 Feb 2022 07:22:59 +0000 Subject: [PATCH 09/16] Bump yosys-plugins from `57a3b87` to `61db11f` Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `57a3b87` to `61db11f`. - [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases) - [Commits](https://github.com/SymbiFlow/yosys-symbiflow-plugins/compare/57a3b87b7bf372611b2988f221c45f2ae16f1a9a...61db11f1b259f2b14574f142343830161a8df1b7) --- updated-dependencies: - dependency-name: yosys-plugins dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys-plugins | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys-plugins b/yosys-plugins index 57a3b87b7..61db11f1b 160000 --- a/yosys-plugins +++ b/yosys-plugins @@ -1 +1 @@ -Subproject commit 57a3b87b7bf372611b2988f221c45f2ae16f1a9a +Subproject commit 61db11f1b259f2b14574f142343830161a8df1b7 From a615c9d4e3aff4788c6cd7c0cdbf6b87e18a25ec Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Feb 2022 09:43:41 -0800 Subject: [PATCH 10/16] [Test] Rename test cases --- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 2 +- .../config/task.conf | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename openfpga_flow/tasks/basic_tests/preconfig_testbench/{configuration_chain_config_done_scff => configuration_chain_config_done_io}/config/task.conf (100%) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index ca6f9e1ab..2fa69fb87 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -23,7 +23,7 @@ run-task basic_tests/full_testbench/fast_configuration_chain_use_set --debug --s run-task basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs run-task basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs -run-task basic_tests/preconfig_testbench/configuration_chain_config_done_scff --debug --show_thread_logs +run-task basic_tests/preconfig_testbench/configuration_chain_config_done_io --debug --show_thread_logs run-task basic_tests/preconfig_testbench/configuration_chain_no_time_stamp --debug --show_thread_logs echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; diff --git a/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_done_scff/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_done_io/config/task.conf similarity index 100% rename from openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_done_scff/config/task.conf rename to openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_done_io/config/task.conf From fcaff28e24bd97309d0e9955adc0ee16bd851510 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Feb 2022 09:46:55 -0800 Subject: [PATCH 11/16] [HDL] Add a new IO cell with config_done support --- .../openfpga_cell_library/verilog/gpio.v | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/openfpga_flow/openfpga_cell_library/verilog/gpio.v b/openfpga_flow/openfpga_cell_library/verilog/gpio.v index 1b3618ab2..6c1b8158c 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/gpio.v +++ b/openfpga_flow/openfpga_cell_library/verilog/gpio.v @@ -19,6 +19,24 @@ module GPIO ( assign PAD = DIR ? 1'bz : A; endmodule +//----------------------------------------------------- +// Function : A minimum general purpose I/O with config_done signal +// which can block signals during configuration phase +//----------------------------------------------------- +module GPIO ( + input CONFIG_DONE, // Control signal to block signals + input A, // Data output + output Y, // Data input + inout PAD, // bi-directional pad + input DIR // direction control +); + //----- when direction enabled, the signal is propagated from PAD to data input + assign Y = CONFIG_DONE ? (DIR ? PAD : 1'bz) : 1'bz; + //----- when direction is disabled, the signal is propagated from data out to pad + assign PAD = CONFIG_DONE ? (DIR ? 1'bz : A) : 1'bz; +endmodule + + //----------------------------------------------------- // Function : A minimum input pad //----------------------------------------------------- From fdaf97e60dc0d9c7ce2cf75c61806bffc253627e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Feb 2022 09:49:34 -0800 Subject: [PATCH 12/16] [Test] Update test case by using GPIO with config_done signals --- ...ff_openfpga.xml => k4_N4_40nm_cc_cfgdscffio_openfpga.xml} | 5 +++-- openfpga_flow/openfpga_cell_library/verilog/gpio.v | 2 +- .../configuration_chain_config_done_io/config/task.conf | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) rename openfpga_flow/openfpga_arch/{k4_N4_40nm_cc_cfgdscff_openfpga.xml => k4_N4_40nm_cc_cfgdscffio_openfpga.xml} (95%) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscffio_openfpga.xml similarity index 95% rename from openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscff_openfpga.xml rename to openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscffio_openfpga.xml index 2d2bcb9ec..677f855c4 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscff_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscffio_openfpga.xml @@ -152,10 +152,11 @@ - + + @@ -177,7 +178,7 @@ - + diff --git a/openfpga_flow/openfpga_cell_library/verilog/gpio.v b/openfpga_flow/openfpga_cell_library/verilog/gpio.v index 6c1b8158c..383a5af96 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/gpio.v +++ b/openfpga_flow/openfpga_cell_library/verilog/gpio.v @@ -23,7 +23,7 @@ endmodule // Function : A minimum general purpose I/O with config_done signal // which can block signals during configuration phase //----------------------------------------------------- -module GPIO ( +module GPIO_CFGD ( input CONFIG_DONE, // Control signal to block signals input A, // Data output output Y, // Data input diff --git a/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_done_io/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_done_io/config/task.conf index 328d008fc..0a148ee3c 100644 --- a/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_done_io/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_done_io/config/task.conf @@ -17,7 +17,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscff_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscffio_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] From 9f7a182433bbed6884762998571fd6f2f26828df Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Feb 2022 09:51:26 -0800 Subject: [PATCH 13/16] [Arch] Typo --- .../openfpga_arch/k4_N4_40nm_cc_cfgdscffio_openfpga.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscffio_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscffio_openfpga.xml index 677f855c4..ce9403181 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscffio_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscffio_openfpga.xml @@ -156,7 +156,7 @@ - + From c4d8a69143a0926d1703d594937013ed0f2de288 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Fri, 25 Feb 2022 00:02:21 +0000 Subject: [PATCH 14/16] Updated Patch Count --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 4da29560b..c80805679 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -53,7 +53,7 @@ set_property(CACHE VPR_USE_EZGL PROPERTY STRINGS auto off on) # Version number set(OPENFPGA_VERSION_MAJOR 1) set(OPENFPGA_VERSION_MINOR 1) -set(OPENFPGA_VERSION_PATCH 8) +set(OPENFPGA_VERSION_PATCH 23) set(OPENFPGA_VERSION_PRERELEASE "dev") # Include user-defined functions From be05f08d1a45d29f868d7f55c1d3a552b48953ff Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Fri, 25 Feb 2022 07:27:35 +0000 Subject: [PATCH 15/16] Bump yosys-plugins from `61db11f` to `e40caae` Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `61db11f` to `e40caae`. - [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases) - [Commits](https://github.com/SymbiFlow/yosys-symbiflow-plugins/compare/61db11f1b259f2b14574f142343830161a8df1b7...e40caaecc5623f007b2033892f71630828274258) --- updated-dependencies: - dependency-name: yosys-plugins dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys-plugins | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys-plugins b/yosys-plugins index 61db11f1b..e40caaecc 160000 --- a/yosys-plugins +++ b/yosys-plugins @@ -1 +1 @@ -Subproject commit 61db11f1b259f2b14574f142343830161a8df1b7 +Subproject commit e40caaecc5623f007b2033892f71630828274258 From 87a8f0ddac47481bb79a55f03da57a9ef85dd79e Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sat, 26 Feb 2022 00:02:01 +0000 Subject: [PATCH 16/16] Updated Patch Count --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index c80805679..325269b24 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -53,7 +53,7 @@ set_property(CACHE VPR_USE_EZGL PROPERTY STRINGS auto off on) # Version number set(OPENFPGA_VERSION_MAJOR 1) set(OPENFPGA_VERSION_MINOR 1) -set(OPENFPGA_VERSION_PATCH 23) +set(OPENFPGA_VERSION_PATCH 35) set(OPENFPGA_VERSION_PRERELEASE "dev") # Include user-defined functions