From 148cc74d6a79335ae0a6a609e3162e3a989ab0cc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 12 Apr 2020 15:01:47 -0600 Subject: [PATCH] add io test cases to Travis CI --- .travis/script.sh | 6 ++++ ...er_chain_mem16K_multi_io_capacity_40nm.xml | 2 +- ...ble_adder_chain_mem16K_reduced_io_40nm.xml | 2 +- .../io/multi_io_capacity/config/task.conf | 34 +++++++++++++++++++ .../io/reduced_io/config/task.conf | 34 +++++++++++++++++++ 5 files changed, 76 insertions(+), 2 deletions(-) create mode 100644 openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf create mode 100644 openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf diff --git a/.travis/script.sh b/.travis/script.sh index 4c82f8128..59390a124 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -63,4 +63,10 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/bram/dpram16k --de echo -e "Testing Verilog generation with 16k block RAMs spanning two columns "; python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/bram/wide_dpram16k --debug --show_thread_logs +echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA "; +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/io/multi_io_capacity --debug --show_thread_logs + +echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA "; +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/io/reduced_io --debug --show_thread_logs + end_section "OpenFPGA.TaskTun" diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml index 8eb6f32bf..a3233edb3 100644 --- a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml +++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml @@ -226,7 +226,7 @@ - + diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml index 6f8c4cfae..2ed58d2f7 100644 --- a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml +++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml @@ -195,7 +195,7 @@ - + diff --git a/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf new file mode 100644 index 000000000..a3f9081d9 --- /dev/null +++ b/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif + +[SYNTHESIS_PARAM] +bench0_top = top +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf new file mode 100644 index 000000000..8ed4998db --- /dev/null +++ b/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif + +[SYNTHESIS_PARAM] +bench0_top = top +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist=