From 7020d9b4b67746d290aa3f6f99a732fe0adc3fb6 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Sun, 9 Dec 2018 15:48:59 -0700 Subject: [PATCH 1/2] Edit waveform generator + fix clock mapping in autochecked testbench --- vpr7_x2p/vpr/Circuits/pip_add_yosys.v | 805 ++++++++++++++++++ .../fpga_spice/verilog/verilog_autocheck_tb.c | 10 +- .../fpga_spice/verilog/verilog_top_netlist.c | 8 +- 3 files changed, 817 insertions(+), 6 deletions(-) create mode 100644 vpr7_x2p/vpr/Circuits/pip_add_yosys.v diff --git a/vpr7_x2p/vpr/Circuits/pip_add_yosys.v b/vpr7_x2p/vpr/Circuits/pip_add_yosys.v new file mode 100644 index 000000000..0302a988b --- /dev/null +++ b/vpr7_x2p/vpr/Circuits/pip_add_yosys.v @@ -0,0 +1,805 @@ +/* Generated by Yosys 0.7 (git sha1 UNKNOWN, gcc 4.8.5 -fPIC -Os) */ + +(* top = 1 *) +(* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:7" *) +module pip_add(rst, clk, a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7, b_0, b_1, b_2, b_3, b_4, b_5, b_6, b_7, cin, sumout_0, sumout_1, sumout_2, sumout_3, sumout_4, sumout_5, sumout_6, sumout_7, cout); + wire _000_; + wire _001_; + wire _002_; + wire _003_; + wire _004_; + wire _005_; + wire _006_; + wire _007_; + wire _008_; + wire _009_; + wire _010_; + wire _011_; + wire _012_; + wire _013_; + wire _014_; + wire _015_; + wire _016_; + wire _017_; + wire _018_; + wire _019_; + wire _020_; + wire _021_; + wire _022_; + wire _023_; + wire _024_; + wire _025_; + wire _026_; + wire _027_; + wire _028_; + wire _029_; + wire _030_; + wire _031_; + wire _032_; + wire _033_; + wire _034_; + wire _035_; + wire _036_; + wire _037_; + wire _038_; + wire _039_; + wire _040_; + wire _041_; + wire _042_; + wire _043_; + wire _044_; + wire _045_; + wire _046_; + wire _047_; + wire _048_; + wire _049_; + wire _050_; + wire _051_; + wire _052_; + wire _053_; + wire _054_; + wire _055_; + wire _056_; + wire _057_; + wire _058_; + wire _059_; + wire _060_; + wire _061_; + wire _062_; + wire _063_; + wire _064_; + wire _065_; + wire _066_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:39" *) + input a_0; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:40" *) + input a_1; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:41" *) + input a_2; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:42" *) + input a_3; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:43" *) + input a_4; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:44" *) + input a_5; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:45" *) + input a_6; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:46" *) + input a_7; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:47" *) + input b_0; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:48" *) + input b_1; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:49" *) + input b_2; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:50" *) + input b_3; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:51" *) + input b_4; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:52" *) + input b_5; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:53" *) + input b_6; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:54" *) + input b_7; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:55" *) + input cin; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:38" *) + input clk; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:64" *) + output cout; + reg cout; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:66" *) + reg [7:0] reg0_a; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:67" *) + reg [7:0] reg0_b; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:72" *) + reg reg0_cin; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:68" *) + reg [7:0] reg1_a; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:69" *) + reg [7:0] reg1_b; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:73" *) + reg reg1_cin; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:70" *) + reg [7:0] reg2_a; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:71" *) + reg [7:0] reg2_b; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:74" *) + reg reg2_cin; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:37" *) + input rst; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:56" *) + output sumout_0; + reg sumout_0; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:57" *) + output sumout_1; + reg sumout_1; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:58" *) + output sumout_2; + reg sumout_2; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:59" *) + output sumout_3; + reg sumout_3; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:60" *) + output sumout_4; + reg sumout_4; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:61" *) + output sumout_5; + reg sumout_5; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:62" *) + output sumout_6; + reg sumout_6; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:63" *) + output sumout_7; + reg sumout_7; + \$lut #( + .LUT(16'b0001010001000001), + .WIDTH(32'd4) + ) _067_ ( + .A({ reg2_a[6], reg2_b[6], _060_, rst }), + .Y(_021_) + ); + \$lut #( + .LUT(16'b0001000100010111), + .WIDTH(32'd4) + ) _068_ ( + .A({ _064_, _061_, reg2_a[5], reg2_b[5] }), + .Y(_060_) + ); + \$lut #( + .LUT(64'b1111110011010100110101001100000000000000000000000000000000000000), + .WIDTH(32'd6) + ) _069_ ( + .A({ _063_, reg2_a[2], reg2_b[2], reg2_a[3], reg2_b[3], _062_ }), + .Y(_061_) + ); + \$lut #( + .LUT(32'd18175871), + .WIDTH(32'd5) + ) _070_ ( + .A({ reg2_a[1], reg2_cin, reg2_a[0], reg2_b[0], reg2_b[1] }), + .Y(_062_) + ); + \$lut #( + .LUT(4'b0110), + .WIDTH(32'd2) + ) _071_ ( + .A({ reg2_a[4], reg2_b[4] }), + .Y(_063_) + ); + \$lut #( + .LUT(4'b1000), + .WIDTH(32'd2) + ) _072_ ( + .A({ reg2_a[4], reg2_b[4] }), + .Y(_064_) + ); + \$lut #( + .LUT(16'b0001010001000001), + .WIDTH(32'd4) + ) _073_ ( + .A({ reg2_a[7], reg2_b[7], _065_, rst }), + .Y(_032_) + ); + \$lut #( + .LUT(64'b0000000101010111000000010101011100000001010101110001010101111111), + .WIDTH(32'd6) + ) _074_ ( + .A({ _061_, _064_, reg2_a[6:5], reg2_b[5], reg2_b[6] }), + .Y(_065_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _075_ ( + .A({ a_0, rst }), + .Y(_043_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _076_ ( + .A({ a_1, rst }), + .Y(_054_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _077_ ( + .A({ a_2, rst }), + .Y(_005_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _078_ ( + .A({ a_3, rst }), + .Y(_012_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _079_ ( + .A({ a_4, rst }), + .Y(_013_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _080_ ( + .A({ a_5, rst }), + .Y(_014_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _081_ ( + .A({ a_6, rst }), + .Y(_015_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _082_ ( + .A({ a_7, rst }), + .Y(_016_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _083_ ( + .A({ reg0_a[0], rst }), + .Y(_017_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _084_ ( + .A({ reg0_a[1], rst }), + .Y(_018_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _085_ ( + .A({ reg0_a[2], rst }), + .Y(_019_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _086_ ( + .A({ reg0_a[3], rst }), + .Y(_020_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _087_ ( + .A({ reg0_a[4], rst }), + .Y(_022_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _088_ ( + .A({ reg0_a[5], rst }), + .Y(_023_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _089_ ( + .A({ reg0_a[6], rst }), + .Y(_024_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _090_ ( + .A({ reg0_a[7], rst }), + .Y(_025_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _091_ ( + .A({ reg1_a[0], rst }), + .Y(_026_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _092_ ( + .A({ reg1_a[1], rst }), + .Y(_027_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _093_ ( + .A({ reg1_a[2], rst }), + .Y(_028_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _094_ ( + .A({ reg1_a[3], rst }), + .Y(_029_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _095_ ( + .A({ reg1_a[4], rst }), + .Y(_030_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _096_ ( + .A({ reg1_a[5], rst }), + .Y(_031_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _097_ ( + .A({ reg1_a[6], rst }), + .Y(_033_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _098_ ( + .A({ reg1_a[7], rst }), + .Y(_034_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _099_ ( + .A({ b_0, rst }), + .Y(_035_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _100_ ( + .A({ b_1, rst }), + .Y(_036_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _101_ ( + .A({ b_2, rst }), + .Y(_037_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _102_ ( + .A({ b_3, rst }), + .Y(_038_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _103_ ( + .A({ b_4, rst }), + .Y(_039_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _104_ ( + .A({ b_5, rst }), + .Y(_040_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _105_ ( + .A({ b_6, rst }), + .Y(_041_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _106_ ( + .A({ b_7, rst }), + .Y(_042_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _107_ ( + .A({ reg0_b[0], rst }), + .Y(_044_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _108_ ( + .A({ reg0_b[1], rst }), + .Y(_045_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _109_ ( + .A({ reg0_b[2], rst }), + .Y(_046_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _110_ ( + .A({ reg0_b[3], rst }), + .Y(_047_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _111_ ( + .A({ reg0_b[4], rst }), + .Y(_048_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _112_ ( + .A({ reg0_b[5], rst }), + .Y(_049_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _113_ ( + .A({ reg0_b[6], rst }), + .Y(_050_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _114_ ( + .A({ reg0_b[7], rst }), + .Y(_051_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _115_ ( + .A({ reg1_b[0], rst }), + .Y(_052_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _116_ ( + .A({ reg1_b[1], rst }), + .Y(_053_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _117_ ( + .A({ reg1_b[2], rst }), + .Y(_055_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _118_ ( + .A({ reg1_b[3], rst }), + .Y(_056_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _119_ ( + .A({ reg1_b[4], rst }), + .Y(_057_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _120_ ( + .A({ reg1_b[5], rst }), + .Y(_058_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _121_ ( + .A({ reg1_b[6], rst }), + .Y(_059_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _122_ ( + .A({ reg1_b[7], rst }), + .Y(_000_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _123_ ( + .A({ cin, rst }), + .Y(_001_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _124_ ( + .A({ reg0_cin, rst }), + .Y(_002_) + ); + \$lut #( + .LUT(4'b0100), + .WIDTH(32'd2) + ) _125_ ( + .A({ reg1_cin, rst }), + .Y(_003_) + ); + \$lut #( + .LUT(16'b0000000011010100), + .WIDTH(32'd4) + ) _126_ ( + .A({ rst, reg2_a[7], reg2_b[7], _065_ }), + .Y(_004_) + ); + \$lut #( + .LUT(16'b0100000100010100), + .WIDTH(32'd4) + ) _127_ ( + .A({ reg2_cin, reg2_a[0], reg2_b[0], rst }), + .Y(_006_) + ); + \$lut #( + .LUT(64'b0000000011101000000000000001011100000000000101110000000011101000), + .WIDTH(32'd6) + ) _128_ ( + .A({ reg2_a[1], reg2_b[1], rst, reg2_cin, reg2_a[0], reg2_b[0] }), + .Y(_007_) + ); + \$lut #( + .LUT(16'b0001010001000001), + .WIDTH(32'd4) + ) _129_ ( + .A({ reg2_a[2], reg2_b[2], _062_, rst }), + .Y(_008_) + ); + \$lut #( + .LUT(16'b0001010001000001), + .WIDTH(32'd4) + ) _130_ ( + .A({ reg2_a[3], reg2_b[3], _066_, rst }), + .Y(_009_) + ); + \$lut #( + .LUT(8'b00101011), + .WIDTH(32'd3) + ) _131_ ( + .A({ reg2_a[2], reg2_b[2], _062_ }), + .Y(_066_) + ); + \$lut #( + .LUT(32'd234946830), + .WIDTH(32'd5) + ) _132_ ( + .A({ reg2_a[5], reg2_b[5], rst, _064_, _061_ }), + .Y(_011_) + ); + \$lut #( + .LUT(32'd2818260), + .WIDTH(32'd5) + ) _133_ ( + .A({ _063_, rst, reg2_a[3], reg2_b[3], _066_ }), + .Y(_010_) + ); + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:94|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg0_a[0] <= _043_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:94|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg0_a[1] <= _054_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:94|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg0_a[2] <= _005_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:94|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg0_a[3] <= _012_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:94|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg0_a[4] <= _013_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:94|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg0_a[5] <= _014_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:94|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg0_a[6] <= _015_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:94|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg0_a[7] <= _016_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:106|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg1_a[0] <= _017_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:106|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg1_a[1] <= _018_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:106|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg1_a[2] <= _019_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:106|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg1_a[3] <= _020_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:106|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg1_a[4] <= _022_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:106|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg1_a[5] <= _023_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:106|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg1_a[6] <= _024_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:106|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg1_a[7] <= _025_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:118|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg2_a[0] <= _026_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:118|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg2_a[1] <= _027_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:118|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg2_a[2] <= _028_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:118|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg2_a[3] <= _029_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:118|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg2_a[4] <= _030_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:118|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg2_a[5] <= _031_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:118|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg2_a[6] <= _033_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:118|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg2_a[7] <= _034_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:94|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg0_b[0] <= _035_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:94|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg0_b[1] <= _036_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:94|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg0_b[2] <= _037_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:94|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg0_b[3] <= _038_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:94|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg0_b[4] <= _039_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:94|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg0_b[5] <= _040_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:94|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg0_b[6] <= _041_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:94|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg0_b[7] <= _042_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:106|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg1_b[0] <= _044_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:106|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg1_b[1] <= _045_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:106|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg1_b[2] <= _046_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:106|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg1_b[3] <= _047_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:106|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg1_b[4] <= _048_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:106|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg1_b[5] <= _049_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:106|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg1_b[6] <= _050_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:106|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg1_b[7] <= _051_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:118|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg2_b[0] <= _052_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:118|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg2_b[1] <= _053_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:118|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg2_b[2] <= _055_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:118|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg2_b[3] <= _056_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:118|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg2_b[4] <= _057_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:118|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg2_b[5] <= _058_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:118|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg2_b[6] <= _059_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:118|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg2_b[7] <= _000_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:94|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg0_cin <= _001_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:106|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg1_cin <= _002_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:118|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + reg2_cin <= _003_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:131|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + cout <= _004_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:131|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + sumout_0 <= _006_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:131|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + sumout_1 <= _007_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:131|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + sumout_2 <= _008_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:131|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + sumout_3 <= _009_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:131|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + sumout_4 <= _010_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:131|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + sumout_5 <= _011_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:131|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + sumout_6 <= _021_; + (* src = "/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/Circuits/pip_add.v:131|/usr/local/stow/yosys/0.7/bin/../share/yosys/adff2dff.v:22" *) + always @(posedge clk) + sumout_7 <= _032_; +endmodule diff --git a/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_autocheck_tb.c b/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_autocheck_tb.c index aa0567583..9b83c76c9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_autocheck_tb.c +++ b/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_autocheck_tb.c @@ -568,10 +568,16 @@ void dump_verilog_top_auto_testbench_call_benchmark(FILE* fp, char* blif_circuit fprintf(fp, ",\n"); } if(VPACK_INPAD == logical_block[iblock].type){ - fprintf(fp, " %s_%s_%d_", logical_block[iblock].name, gio_inout_prefix, iopad_idx); + /* See if this is a clock net */ + if (TRUE == vpack_net[logical_block[iblock].output_nets[0][0]].is_global) { + fprintf(fp, " %s", top_tb_op_clock_port_name); + } + else{ + fprintf(fp, " %s_%s_%d_", logical_block[iblock].name, gio_inout_prefix, iopad_idx); + } } else if(VPACK_OUTPAD == logical_block[iblock].type){ - fprintf(fp, " %s_benchmark", logical_block[iblock].name); + fprintf(fp, " %s_benchmark", logical_block[iblock].name); } } } diff --git a/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_top_netlist.c b/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_top_netlist.c index 797735cf2..2fee0786e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_top_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_top_netlist.c @@ -2437,14 +2437,14 @@ void dump_verilog_top_testbench_stimuli_serial_version(FILE* fp, fprintf(fp, "end\n"); fprintf(fp, "always wait (~%s)\n", top_tb_reset_port_name); fprintf(fp, " begin \n"); - fprintf(fp, " %s%s%s[%d] = ~%s%s%s[%d];\n #%2f\n", + fprintf(fp, " %s%s%s[%d] = ~%s%s%s[%d];\n #%.2f\n", gio_inout_prefix, iopad_verilog_model->prefix, top_tb_inout_reg_postfix, iopad_idx, gio_inout_prefix, iopad_verilog_model->prefix, top_tb_inout_reg_postfix, iopad_idx, - (op_clock_period * cur_spice_net_info->probability * 2. / cur_spice_net_info->density) / verilog_sim_timescale); - fprintf(fp, " %s%s%s[%d] = ~%s%s%s[%d];\n #%2f;\n", + (op_clock_period * 2 * ((int)(cur_spice_net_info->probability / cur_spice_net_info->density)+ iblock) / verilog_sim_timescale)); + fprintf(fp, " %s%s%s[%d] = ~%s%s%s[%d];\n #%.2f;\n", gio_inout_prefix, iopad_verilog_model->prefix, top_tb_inout_reg_postfix, iopad_idx, gio_inout_prefix, iopad_verilog_model->prefix, top_tb_inout_reg_postfix, iopad_idx, - (op_clock_period * cur_spice_net_info->density * 6. / cur_spice_net_info->probability) / verilog_sim_timescale); + (op_clock_period * 2 * ((int)((cur_spice_net_info->density / cur_spice_net_info->probability) * 2.5 + iblock)) / verilog_sim_timescale)); fprintf(fp, " end \n"); fprintf(fp, "\n"); found_mapped_inpad++; From a69c2e188255fbd1175e543324e4d721a93f4686 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Mon, 10 Dec 2018 09:46:16 -0700 Subject: [PATCH 2/2] Add security in checking to avoid simulation glitch error --- vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_autocheck_tb.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_autocheck_tb.c b/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_autocheck_tb.c index 9b83c76c9..91c4cd40c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_autocheck_tb.c +++ b/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_autocheck_tb.c @@ -609,8 +609,10 @@ void dump_verilog_top_auto_testbench_check(FILE* fp){ assert((VPACK_INPAD == logical_block[iblock].type)||(VPACK_OUTPAD == logical_block[iblock].type)); if(VPACK_OUTPAD == logical_block[iblock].type){ fprintf(fp, " always@(posedge %s_verification) begin\n", logical_block[iblock].name); - fprintf(fp, " $display(\"Mismatch on %s_verification\");\n", logical_block[iblock].name); - fprintf(fp, " $finish;\n"); + fprintf(fp, " if(%s_verification) begin\n", logical_block[iblock].name); + fprintf(fp, " $display(\"Mismatch on %s_verification\");\n", logical_block[iblock].name); + fprintf(fp, " $finish;\n"); + fprintf(fp, " end\n"); fprintf(fp, " end\n\n"); } }