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Fix Explicit verilog

This commit is contained in:
Baudouin Chauviere 2019-07-11 22:09:34 -06:00
parent c9b84f61c9
commit 1431ee2f82
2 changed files with 7 additions and 7 deletions
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12
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
View File

@ -373,7 +373,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp,
fprintf(fp, ".%s(", fprintf(fp, ".%s(",
pb_type_port->spice_model_port->lib_name); pb_type_port->spice_model_port->lib_name);
} }
if (1 < pb_type_port_num_pins) { if (1 < pb_type_port->num_pins) {
fprintf(fp, "{"); fprintf(fp, "{");
} }
for (int ipin = 0; ipin < pb_type_port->num_pins; ++ipin) { for (int ipin = 0; ipin < pb_type_port->num_pins; ++ipin) {
@ -383,7 +383,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp,
fprintf(fp, "%s", fprintf(fp, "%s",
gen_verilog_one_pb_type_pin_name(port_prefix, pb_type_port, ipin)); gen_verilog_one_pb_type_pin_name(port_prefix, pb_type_port, ipin));
} }
if (1 < pb_type_port_num_pins) { if (1 < pb_type_port->num_pins) {
fprintf(fp, "}"); fprintf(fp, "}");
} }
if (TRUE == dump_explicit_port_map) { if (TRUE == dump_explicit_port_map) {
@ -445,7 +445,7 @@ void dump_verilog_pb_type_bus_ports(FILE* fp,
} }
} }
dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "inout", dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "inout",
pb_type_inout_ports[iport], dump_port_type, dump_explicit_port_map); pb_type_inout_ports[iport], dump_port_type, TRUE);
/* Update the counter */ /* Update the counter */
num_dumped_port++; num_dumped_port++;
@ -464,7 +464,7 @@ void dump_verilog_pb_type_bus_ports(FILE* fp,
} }
} }
dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "input", dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "input",
pb_type_input_ports[iport], dump_port_type, dump_explicit_port_map); pb_type_input_ports[iport], dump_port_type, TRUE);
/* Update the counter */ /* Update the counter */
num_dumped_port++; num_dumped_port++;
} }
@ -482,7 +482,7 @@ void dump_verilog_pb_type_bus_ports(FILE* fp,
} }
} }
dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "output", dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "output",
pb_type_output_ports[iport], dump_port_type, dump_explicit_port_map); pb_type_output_ports[iport], dump_port_type, TRUE);
/* Update the counter */ /* Update the counter */
num_dumped_port++; num_dumped_port++;
} }
@ -501,7 +501,7 @@ void dump_verilog_pb_type_bus_ports(FILE* fp,
} }
} }
dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "input", dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "input",
pb_type_clk_ports[iport], dump_port_type, dump_explicit_port_map); pb_type_clk_ports[iport], dump_port_type, TRUE);
/* Update the counter */ /* Update the counter */
num_dumped_port++; num_dumped_port++;
} }

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c
View File

@ -134,7 +134,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl); get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl);
/* print ports --> input ports */ /* print ports --> input ports */
dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, TRUE, FALSE, FALSE, false); dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, TRUE, FALSE, FALSE, true);
/* IOPADs requires a specical port to output */ /* IOPADs requires a specical port to output */
if (SPICE_MODEL_IOPAD == verilog_model->type) { if (SPICE_MODEL_IOPAD == verilog_model->type) {
fprintf(fp, ",\n"); fprintf(fp, ",\n");