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add support on packable/unpackable modes in VPR architecture

This commit is contained in:
tangxifan 2020-04-06 16:07:49 -06:00
parent 7e89c2c65f
commit 13cd48c119
17 changed files with 61 additions and 23 deletions
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3
libs/libarchfpga/src/physical_types.h
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@ -822,6 +822,9 @@ struct t_mode {
t_pb_type* parent_pb_type = nullptr; t_pb_type* parent_pb_type = nullptr;
int index = 0; int index = 0;
/* Xifan Tang: Specify if the mode is packable or not */
bool packable = true;
/* Power related members */ /* Power related members */
t_mode_power* mode_power = nullptr; t_mode_power* mode_power = nullptr;

14
libs/libarchfpga/src/read_xml_arch_file.cpp
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@ -1956,6 +1956,20 @@ static void ProcessMode(pugi::xml_node Parent, t_mode* mode, const bool timing_e
mode->name = vtr::strdup(Prop); mode->name = vtr::strdup(Prop);
} }
/* Xifan Tang: parse XML about if this mode is packable or not */
mode->packable = true;
/* If the parent mode is not packable, all the child mode should be unpackable as well */
if (nullptr != mode->parent_pb_type->parent_mode) {
mode->packable = mode->parent_pb_type->parent_mode->packable;
}
/* Override if user specify */
mode->packable = get_attribute(Parent, "packable", loc_data, ReqOpt::OPTIONAL).as_bool(mode->packable);
if (false == mode->packable) {
VTR_LOG("mode '%s[%s]' is defined by user to be not packable\n",
mode->parent_pb_type->name,
mode->name);
}
mode->num_pb_type_children = count_children(Parent, "pb_type", loc_data, ReqOpt::OPTIONAL); mode->num_pb_type_children = count_children(Parent, "pb_type", loc_data, ReqOpt::OPTIONAL);
if (mode->num_pb_type_children > 0) { if (mode->num_pb_type_children > 0) {
mode->pb_type_children = new t_pb_type[mode->num_pb_type_children]; mode->pb_type_children = new t_pb_type[mode->num_pb_type_children];

2
openfpga/test_vpr_arch/k6_N10_40nm.xml
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@ -139,7 +139,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>

2
openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml
View File

@ -139,7 +139,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>

4
openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
View File

@ -158,7 +158,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -230,7 +230,7 @@
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>

4
openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
View File

@ -245,7 +245,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -321,7 +321,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
View File

@ -282,7 +282,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -358,7 +358,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml
View File

@ -158,7 +158,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -230,7 +230,7 @@
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>

4
openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
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@ -245,7 +245,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -321,7 +321,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
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@ -282,7 +282,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -358,7 +358,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
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@ -348,7 +348,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -424,7 +424,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
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@ -316,7 +316,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -392,7 +392,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
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@ -285,7 +285,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -361,7 +361,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
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@ -282,7 +282,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -358,7 +358,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" packable="false">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

5
vpr/src/pack/cluster.cpp
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@ -1458,6 +1458,11 @@ static enum e_block_pack_status try_place_atom_block_rec(const t_pb_graph_node*
} }
pb_type = pb_graph_node->pb_type; pb_type = pb_graph_node->pb_type;
/* Xifan Tang: bypass unpackable modes */
if (false == pb_type->parent_mode->packable) {
return BLK_FAILED_FEASIBLE;
}
is_primitive = (pb_type->num_modes == 0); is_primitive = (pb_type->num_modes == 0);
if (is_primitive) { if (is_primitive) {

4
vpr/src/pack/cluster_router.cpp
View File

@ -1173,6 +1173,10 @@ static void expand_node_all_modes(t_lb_router_data* router_data, t_expansion_nod
if (cur_mode != -1 && mode != cur_mode) { if (cur_mode != -1 && mode != cur_mode) {
continue; continue;
} }
/* Xifan Tang: Do not expand in unpackable modes */
if (false == pin->parent_node->pb_type->parent_mode->packable) {
continue;
}
/* Check whether a mode is illegal. If it is then the node will not be expanded */ /* Check whether a mode is illegal. If it is then the node will not be expanded */
bool is_illegal = false; bool is_illegal = false;

14
vpr/src/pack/prepack.cpp
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@ -791,6 +791,13 @@ t_pack_molecule* alloc_and_load_pack_molecules(t_pack_patterns* list_of_pack_pat
* TODO: Need to investigate better mapping strategies than first-fit * TODO: Need to investigate better mapping strategies than first-fit
*/ */
for (i = 0; i < num_packing_patterns; i++) { for (i = 0; i < num_packing_patterns; i++) {
/* Xifan Tang: skip patterns that belong to unpackable modes */
if ( (nullptr != list_of_pack_patterns[i].root_block->pb_type->parent_mode)
&& (false == list_of_pack_patterns[i].root_block->pb_type->parent_mode->packable) ) {
continue;
}
best_pattern = 0; best_pattern = 0;
for (j = 1; j < num_packing_patterns; j++) { for (j = 1; j < num_packing_patterns; j++) {
if (is_used[best_pattern]) { if (is_used[best_pattern]) {
@ -799,7 +806,7 @@ t_pack_molecule* alloc_and_load_pack_molecules(t_pack_patterns* list_of_pack_pat
best_pattern = j; best_pattern = j;
} }
} }
VTR_ASSERT(is_used[best_pattern] == false); VTR_ASSERT(is_used[best_pattern] == false);
is_used[best_pattern] = true; is_used[best_pattern] = true;
auto blocks = atom_ctx.nlist.blocks(); auto blocks = atom_ctx.nlist.blocks();
@ -1213,6 +1220,11 @@ static t_pb_graph_node* get_expected_lowest_cost_primitive_for_atom_block_in_pb_
} }
} else { } else {
for (i = 0; i < curr_pb_graph_node->pb_type->num_modes; i++) { for (i = 0; i < curr_pb_graph_node->pb_type->num_modes; i++) {
/* Xifan Tang: early fail if this primitive in a unpackable mode */
if (false == curr_pb_graph_node->pb_type->modes[i].packable) {
continue;
}
for (j = 0; j < curr_pb_graph_node->pb_type->modes[i].num_pb_type_children; j++) { for (j = 0; j < curr_pb_graph_node->pb_type->modes[i].num_pb_type_children; j++) {
*cost = UNDEFINED; *cost = UNDEFINED;
cur = get_expected_lowest_cost_primitive_for_atom_block_in_pb_graph_node(blk_id, &curr_pb_graph_node->child_pb_graph_nodes[i][j][0], cost); cur = get_expected_lowest_cost_primitive_for_atom_block_in_pb_graph_node(blk_id, &curr_pb_graph_node->child_pb_graph_nodes[i][j][0], cost);