From 1370be0817592648837b9083be0b686984189283 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 15 Feb 2022 16:44:51 -0800
Subject: [PATCH] [Script] Fixing bugs

---
 .../implicit_verilog_example_script.openfpga                  | 4 ++--
 .../implicit_verilog/config/pin_constraints_reset.xml         | 2 +-
 .../verilog_netlist_formats/implicit_verilog/config/task.conf | 2 +-
 .../implicit_verilog_default_nettype_wire/config/task.conf    | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga
index 9ad59198b..f7ab0e145 100644
--- a/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga
@@ -56,8 +56,8 @@ write_fabric_verilog --file ./SRC --include_timing --print_user_defined_template
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
-write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH}  --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH}  --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE}
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/pin_constraints_reset.xml b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/pin_constraints_reset.xml
index c9f8f8242..5b4f76fe3 100644
--- a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/pin_constraints_reset.xml
+++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/pin_constraints_reset.xml
@@ -2,6 +2,6 @@
   <!-- For a given .blif file, we want to assign 
        - the reset signal to the op_reset[0] port of the FPGA fabric
     -->
-  <set_io pin="reset[0]" net="reset"/>
+  <set_io pin="reset[0]" net="rst_counter"/>
 </pin_constraints>
 
diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf
index f58ccdfdc..df489b240 100644
--- a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf
@@ -19,7 +19,7 @@ fpga_flow=yosys_vpr
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
-openfpga_verilog_default_net_type=none
+openfpga_default_net_type=none
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf
index e298e0cc2..591be6245 100644
--- a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf
@@ -19,7 +19,7 @@ fpga_flow=yosys_vpr
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
-openfpga_verilog_default_net_type=wire
+openfpga_default_net_type=wire
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml