From 1353577351d0bc61b81ddc87d240b304c97fcf77 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 13 Jan 2023 16:45:30 -0800
Subject: [PATCH] [test] added a new test to validate locally generated clocks

---
 .../config/pin_constraints_reset.xml          |  4 ++
 .../config/repack_design_constraints.xml      |  4 ++
 .../k4_series/k4n4_clk_gen/config/task.conf   | 43 +++++++++++++++++++
 3 files changed, 51 insertions(+)
 create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints_reset.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/repack_design_constraints.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf

diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints_reset.xml
new file mode 100644
index 000000000..20a21d2cf
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/pin_constraints_reset.xml
@@ -0,0 +1,4 @@
+<pin_constraints>
+  <!-- Intended to be dummy -->
+</pin_constraints>
+
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/repack_design_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/repack_design_constraints.xml
new file mode 100644
index 000000000..06a125111
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/repack_design_constraints.xml
@@ -0,0 +1,4 @@
+<repack_design_constraints>
+  <!-- Intended to be dummy -->
+</repack_design_constraints>
+
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
new file mode 100644
index 000000000..1cf981d22
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
@@ -0,0 +1,43 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 3*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_divider/clk_divider.v
+
+[SYNTHESIS_PARAM]
+# Yosys script parameters
+bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
+bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
+bench_read_verilog_options_common = -nolatches
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
+
+bench0_top = clk_divider
+bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=