riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[core] code format

This commit is contained in:
tangxifan 2024-09-20 17:42:53 -07:00
parent 965ee2190e
commit 1332d426c7
5 changed files with 60 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
libs/libclkarchopenfpga/src/base/clock_network.cpp
View File

@ -274,7 +274,8 @@ std::vector<ClockInternalDriverId> ClockNetwork::spine_intermediate_drivers(
const ClockSpineId& spine_id, const vtr::Point<int>& coord) const { const ClockSpineId& spine_id, const vtr::Point<int>& coord) const {
VTR_ASSERT(valid_spine_id(spine_id)); VTR_ASSERT(valid_spine_id(spine_id));
/* Convert coord to a unique string */ /* Convert coord to a unique string */
std::string coord_str = std::to_string(coord.x()) + std::string(",") + std::to_string(coord.y()); std::string coord_str =
std::to_string(coord.x()) + std::string(",") + std::to_string(coord.y());
auto result = spine_intermediate_drivers_[spine_id].find(coord_str); auto result = spine_intermediate_drivers_[spine_id].find(coord_str);
if (result == spine_intermediate_drivers_[spine_id].end()) { if (result == spine_intermediate_drivers_[spine_id].end()) {
return std::vector<ClockInternalDriverId>(); return std::vector<ClockInternalDriverId>();
@ -837,11 +838,13 @@ ClockInternalDriverId ClockNetwork::add_spine_intermediate_driver(
const std::string& int_driver_to_port) { const std::string& int_driver_to_port) {
VTR_ASSERT(valid_spine_id(spine_id)); VTR_ASSERT(valid_spine_id(spine_id));
/* Convert coord to a unique string */ /* Convert coord to a unique string */
std::string coord_str = std::to_string(coord.x()) + std::string(",") + std::to_string(coord.y()); std::string coord_str =
std::to_string(coord.x()) + std::string(",") + std::to_string(coord.y());
/* Parse ports */ /* Parse ports */
PortParser to_pin_parser(int_driver_to_port); PortParser to_pin_parser(int_driver_to_port);
/* Find any existing id for the driver port */ /* Find any existing id for the driver port */
ClockInternalDriverId int_driver_id_to_add = ClockInternalDriverId(internal_driver_ids_.size()); ClockInternalDriverId int_driver_id_to_add =
ClockInternalDriverId(internal_driver_ids_.size());
for (ClockInternalDriverId int_driver_id : internal_driver_ids_) { for (ClockInternalDriverId int_driver_id : internal_driver_ids_) {
if (internal_driver_from_pins_[int_driver_id] == int_driver_from_port && if (internal_driver_from_pins_[int_driver_id] == int_driver_from_port &&
internal_driver_to_pins_[int_driver_id] == to_pin_parser.port()) { internal_driver_to_pins_[int_driver_id] == to_pin_parser.port()) {
@ -850,7 +853,8 @@ ClockInternalDriverId ClockNetwork::add_spine_intermediate_driver(
} }
} }
/* Reaching here, no existing id can be reused, create a new one */ /* Reaching here, no existing id can be reused, create a new one */
if (int_driver_id_to_add == ClockInternalDriverId(internal_driver_ids_.size())) { if (int_driver_id_to_add ==
ClockInternalDriverId(internal_driver_ids_.size())) {
internal_driver_ids_.push_back(int_driver_id_to_add); internal_driver_ids_.push_back(int_driver_id_to_add);
internal_driver_from_pins_.push_back(int_driver_from_port); internal_driver_from_pins_.push_back(int_driver_from_port);
internal_driver_to_pins_.push_back(to_pin_parser.port()); internal_driver_to_pins_.push_back(to_pin_parser.port());
@ -858,13 +862,18 @@ ClockInternalDriverId ClockNetwork::add_spine_intermediate_driver(
/* Add it to existing map, avoid duplicated id */ /* Add it to existing map, avoid duplicated id */
auto result = spine_intermediate_drivers_[spine_id].find(coord_str); auto result = spine_intermediate_drivers_[spine_id].find(coord_str);
if (result == spine_intermediate_drivers_[spine_id].end()) { if (result == spine_intermediate_drivers_[spine_id].end()) {
spine_intermediate_drivers_[spine_id][coord_str].push_back(int_driver_id_to_add); spine_intermediate_drivers_[spine_id][coord_str].push_back(
int_driver_id_to_add);
} else { } else {
if (std::find(result->second.begin(), result->second.end(), int_driver_id_to_add) == result->second.end()) { if (std::find(result->second.begin(), result->second.end(),
int_driver_id_to_add) == result->second.end()) {
result->second.push_back(int_driver_id_to_add); result->second.push_back(int_driver_id_to_add);
} else { } else {
VTR_LOG_WARN("Skip intermediate driver (from_port='%s', to_port='%s') at (%s) as it is duplicated in the clock architecture description file!\n", VTR_LOG_WARN(
int_driver_from_port.c_str(), int_driver_to_port.c_str(), coord_str.c_str()); "Skip intermediate driver (from_port='%s', to_port='%s') at (%s) as it "
"is duplicated in the clock architecture description file!\n",
int_driver_from_port.c_str(), int_driver_to_port.c_str(),
coord_str.c_str());
} }
} }
return int_driver_id_to_add; return int_driver_id_to_add;

7
libs/libclkarchopenfpga/src/base/clock_network.h
View File

@ -97,7 +97,8 @@ class ClockNetwork {
std::string spine_name(const ClockSpineId& spine_id) const; std::string spine_name(const ClockSpineId& spine_id) const;
vtr::Point<int> spine_start_point(const ClockSpineId& spine_id) const; vtr::Point<int> spine_start_point(const ClockSpineId& spine_id) const;
vtr::Point<int> spine_end_point(const ClockSpineId& spine_id) const; vtr::Point<int> spine_end_point(const ClockSpineId& spine_id) const;
std::vector<ClockInternalDriverId> spine_intermediate_drivers(const ClockSpineId& spine_id, const vtr::Point<int>& coord) const; std::vector<ClockInternalDriverId> spine_intermediate_drivers(
const ClockSpineId& spine_id, const vtr::Point<int>& coord) const;
/* Return the level where the spine locates in the multi-layer clock tree /* Return the level where the spine locates in the multi-layer clock tree
* structure */ * structure */
@ -320,7 +321,9 @@ class ClockNetwork {
vtr::vector<ClockSpineId, std::vector<vtr::Point<int>>> spine_switch_coords_; vtr::vector<ClockSpineId, std::vector<vtr::Point<int>>> spine_switch_coords_;
vtr::vector<ClockSpineId, std::vector<std::vector<ClockInternalDriverId>>> vtr::vector<ClockSpineId, std::vector<std::vector<ClockInternalDriverId>>>
spine_switch_internal_drivers_; spine_switch_internal_drivers_;
vtr::vector<ClockSpineId, std::map<std::string, std::vector<ClockInternalDriverId>>> spine_intermediate_drivers_; vtr::vector<ClockSpineId,
std::map<std::string, std::vector<ClockInternalDriverId>>>
spine_intermediate_drivers_;
vtr::vector<ClockSpineId, ClockSpineId> spine_parents_; vtr::vector<ClockSpineId, ClockSpineId> spine_parents_;
vtr::vector<ClockSpineId, std::vector<ClockSpineId>> spine_children_; vtr::vector<ClockSpineId, std::vector<ClockSpineId>> spine_children_;
vtr::vector<ClockSpineId, ClockTreeId> spine_parent_trees_; vtr::vector<ClockSpineId, ClockTreeId> spine_parent_trees_;

9
libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h
View File

@ -21,12 +21,15 @@ constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_END_X = "end_x";
constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_END_Y = "end_y"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_END_Y = "end_y";
constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_TYPE = "type"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_TYPE = "type";
constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_DIRECTION = "direction"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_DIRECTION = "direction";
constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME = "intermediate_driver"; constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME =
"intermediate_driver";
constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_TAP_NODE_NAME = "tap"; constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_TAP_NODE_NAME = "tap";
constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_X = "x"; constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_X = "x";
constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_Y = "y"; constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_Y = "y";
constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_FROM_PIN = "from_pin"; constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_FROM_PIN =
constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_TO_PIN = "to_pin"; "from_pin";
constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_TO_PIN =
"to_pin";
constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME = "switch_point"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME = "switch_point";
constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME = constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME =
"internal_driver"; "internal_driver";

30
libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp
View File

@ -191,17 +191,17 @@ static void read_xml_clock_spine_intermediate_driver_tap(
} }
std::string int_driver_from_port_name = std::string int_driver_from_port_name =
get_attribute( get_attribute(xml_int_driver,
xml_int_driver, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_FROM_PIN,
XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_FROM_PIN, loc_data) loc_data)
.as_string(); .as_string();
std::string int_driver_to_port_name = std::string int_driver_to_port_name =
get_attribute(xml_int_driver, get_attribute(xml_int_driver,
XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_TO_PIN, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_TO_PIN,
loc_data) loc_data)
.as_string(); .as_string();
clk_ntwk.add_spine_intermediate_driver(spine_id, spine_coord, int_driver_from_port_name, clk_ntwk.add_spine_intermediate_driver(
int_driver_to_port_name); spine_id, spine_coord, int_driver_from_port_name, int_driver_to_port_name);
} }
/******************************************************************** /********************************************************************
@ -266,11 +266,13 @@ static void read_xml_clock_spine_intermediate_driver(
"Invalid id of a clock spine!\n"); "Invalid id of a clock spine!\n");
} }
int tap_x = get_attribute(xml_driver, int tap_x =
XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_X, loc_data) get_attribute(xml_driver, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_X,
loc_data)
.as_int(); .as_int();
int tap_y = get_attribute(xml_driver, int tap_y =
XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_Y, loc_data) get_attribute(xml_driver, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_Y,
loc_data)
.as_int(); .as_int();
/* Add internal drivers if possible */ /* Add internal drivers if possible */
@ -279,7 +281,8 @@ static void read_xml_clock_spine_intermediate_driver(
if (xml_int_driver.name() == if (xml_int_driver.name() ==
std::string(XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_TAP_NODE_NAME)) { std::string(XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_TAP_NODE_NAME)) {
read_xml_clock_spine_intermediate_driver_tap( read_xml_clock_spine_intermediate_driver_tap(
xml_int_driver, loc_data, clk_ntwk, spine_id, vtr::Point<int>(tap_x, tap_y)); xml_int_driver, loc_data, clk_ntwk, spine_id,
vtr::Point<int>(tap_x, tap_y));
} else { } else {
bad_tag(xml_int_driver, loc_data, xml_driver, bad_tag(xml_int_driver, loc_data, xml_driver,
{XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_TAP_NODE_NAME}); {XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_TAP_NODE_NAME});
@ -393,12 +396,13 @@ static void read_xml_clock_spine(pugi::xml_node& xml_spine,
spine_id); spine_id);
} else if (xml_switch_point.name() == } else if (xml_switch_point.name() ==
std::string(XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME)) { std::string(XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME)) {
read_xml_clock_spine_intermediate_driver(xml_switch_point, loc_data, clk_ntwk, read_xml_clock_spine_intermediate_driver(xml_switch_point, loc_data,
spine_id); clk_ntwk, spine_id);
} else { } else {
bad_tag(xml_switch_point, loc_data, xml_spine, bad_tag(xml_switch_point, loc_data, xml_spine,
{XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME}); {XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME,
XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME});
} }
} }
} }

14
libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp
View File

@ -145,15 +145,18 @@ static int write_xml_clock_spine_switch_point(
static int write_xml_clock_spine_intermediate_drivers( static int write_xml_clock_spine_intermediate_drivers(
std::fstream& fp, const ClockNetwork& clk_ntwk, const ClockSpineId& spine_id, std::fstream& fp, const ClockNetwork& clk_ntwk, const ClockSpineId& spine_id,
const vtr::Point<int>& coord) { const vtr::Point<int>& coord) {
std::vector<ClockInternalDriverId> int_drivers = clk_ntwk.spine_intermediate_drivers(spine_id, coord); std::vector<ClockInternalDriverId> int_drivers =
clk_ntwk.spine_intermediate_drivers(spine_id, coord);
if (int_drivers.empty()) { if (int_drivers.empty()) {
return 0; return 0;
} }
openfpga::write_tab_to_file(fp, 3); openfpga::write_tab_to_file(fp, 3);
fp << "<" << XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME << ""; fp << "<" << XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME << "";
write_xml_attribute(fp, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_X, coord.x()); write_xml_attribute(fp, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_X,
write_xml_attribute(fp, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_Y, coord.y()); coord.x());
write_xml_attribute(fp, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_Y,
coord.y());
for (ClockInternalDriverId int_driver_id : int_drivers) { for (ClockInternalDriverId int_driver_id : int_drivers) {
openfpga::write_tab_to_file(fp, 4); openfpga::write_tab_to_file(fp, 4);
@ -161,8 +164,8 @@ static int write_xml_clock_spine_intermediate_drivers(
write_xml_attribute( write_xml_attribute(
fp, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_FROM_PIN, fp, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_FROM_PIN,
clk_ntwk.internal_driver_from_pin(int_driver_id).c_str()); clk_ntwk.internal_driver_from_pin(int_driver_id).c_str());
write_xml_attribute( write_xml_attribute(fp,
fp, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_TO_PIN, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_TO_PIN,
clk_ntwk.internal_driver_to_pin(int_driver_id) clk_ntwk.internal_driver_to_pin(int_driver_id)
.to_verilog_string() .to_verilog_string()
.c_str()); .c_str());
@ -174,7 +177,6 @@ static int write_xml_clock_spine_intermediate_drivers(
return 0; return 0;
} }
static int write_xml_clock_spine(std::fstream& fp, const ClockNetwork& clk_ntwk, static int write_xml_clock_spine(std::fstream& fp, const ClockNetwork& clk_ntwk,
const ClockSpineId& spine_id) { const ClockSpineId& spine_id) {
openfpga::write_tab_to_file(fp, 2); openfpga::write_tab_to_file(fp, 2);