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update tileable rr_graph generator to improve routability and also enable assoicated testing

This commit is contained in:
tangxifan 2019-06-27 17:52:25 -06:00
parent 15c536e9b4
commit 1332ba62e8
3 changed files with 14 additions and 6 deletions
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2
fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
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@ -150,7 +150,7 @@
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout auto="1.0" tileable_routing="off"/> <layout auto="1.0" tileable_routing="on"/>
<spice_settings> <spice_settings>
<parameters> <parameters>
<options sim_temp="25" post="off" captab="off" fast="on"/> <options sim_temp="25" post="off" captab="off" fast="on"/>

16
vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp
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@ -1087,15 +1087,17 @@ void build_gsb_one_ipin_track2pin_map(const t_rr_graph* rr_graph,
(*track2ipin_map)[chan_side_index][track_index].push_back(ipin_index); (*track2ipin_map)[chan_side_index][track_index].push_back(ipin_index);
track_cnt += 2; track_cnt += 2;
/* Stop when we have enough Fc */ /* Stop when we have enough Fc: this may lead to some tracks have zero drivers.
* So I comment it. And we just make sure its track_cnt >= actual_Fc
if (actual_Fc == track_cnt) { if (actual_Fc == track_cnt) {
break; break;
} }
*/
} }
/* Ensure the number of tracks is similar to Fc */ /* Ensure the number of tracks is similar to Fc */
//printf("Fc_in=%d, track_cnt=%d\n", actual_Fc, track_cnt); //printf("Fc_in=%d, track_cnt=%d\n", actual_Fc, track_cnt);
assert (actual_Fc == track_cnt); assert (actual_Fc <= track_cnt);
} }
return; return;
@ -1180,15 +1182,17 @@ void build_gsb_one_opin_pin2track_map(const t_rr_graph* rr_graph,
(*opin2track_map)[opin_side_index][opin_node_id].push_back(track_rr_node_index); (*opin2track_map)[opin_side_index][opin_node_id].push_back(track_rr_node_index);
/* update track counter */ /* update track counter */
track_cnt++; track_cnt++;
/* Stop when we have enough Fc */ /* Stop when we have enough Fc: this may lead to some tracks have zero drivers.
* So I comment it. And we just make sure its track_cnt >= actual_Fc
if (actual_Fc == track_cnt) { if (actual_Fc == track_cnt) {
break; break;
} }
*/
} }
/* Ensure the number of tracks is similar to Fc */ /* Ensure the number of tracks is similar to Fc */
//printf("Fc_out=%lu, scaled_Fc_out=%d, track_cnt=%d, actual_track_cnt=%lu/%lu\n", Fc, actual_Fc, track_cnt, actual_track_list.size(), chan_width); //printf("Fc_out=%lu, scaled_Fc_out=%d, track_cnt=%d, actual_track_cnt=%lu/%lu\n", Fc, actual_Fc, track_cnt, actual_track_list.size(), chan_width);
assert (actual_Fc == track_cnt); assert (actual_Fc <= track_cnt);
} }
return; return;
@ -1330,6 +1334,10 @@ t_pin2track_map build_gsb_opin_to_track_map(t_rr_graph* rr_graph,
/* update offset: aim to rotate starting tracks by 1*/ /* update offset: aim to rotate starting tracks by 1*/
offset[side_manager.to_size_t()] += 1; offset[side_manager.to_size_t()] += 1;
} }
/* Check:
* 1. We want to ensure that each OPIN will drive at least one track
* 2. We want to ensure that each track will be driven by at least 1 OPIN */
} }
return opin2track_map; return opin2track_map;

2
vpr7_x2p/vpr/regression_verilog.sh
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@ -33,7 +33,7 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
cd - cd -
# Run VPR # Run VPR
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis #--fpga_x2p_compact_routing_hierarchy ./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy
cd $fpga_flow_scripts cd $fpga_flow_scripts
perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path