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[test] fixed some bugs on arch

This commit is contained in:
tangxifan 2024-06-29 17:38:34 -07:00
parent 1fd974d544
commit 12c9686c27
2 changed files with 1 additions and 2 deletions
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2
openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml
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@ -173,7 +173,7 @@
<segment name="L4" circuit_model_name="chan_segment"/> <segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment> </routing_segment>
<tile_annotations> <tile_annotations>
<global_port name="clk[0:1]" is_clock="true" clock_arch_tree_name="clk_tree_2lvl" default_val="0"> <global_port name="clk" is_clock="true" clock_arch_tree_name="clk_tree_2lvl" default_val="0">
<tile name="clb" port="clk[0:0]"/> <tile name="clb" port="clk[0:0]"/>
</global_port> </global_port>
</tile_annotations> </tile_annotations>

1
openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/repack_constraints.xml
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@ -1,5 +1,4 @@
<repack_design_constraints> <repack_design_constraints>
<pin_constraint pb_type="clb" pin="clk[0:0]" net="clk"/> <pin_constraint pb_type="clb" pin="clk[0:0]" net="clk"/>
<pin_constraint pb_type="clb" pin="clk[1:1]" net="OPEN"/>
</repack_design_constraints> </repack_design_constraints>