From 129caea38cb93afe977358a7a065cdb1ff87ec6f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 18:30:48 -0600 Subject: [PATCH] [Architecture] Patch configurable latch Verilog HDL with resetb --- openfpga_flow/VerilogNetlists/config_latch_neg_rst.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v b/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v index 836012259..cb24769d5 100644 --- a/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v +++ b/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v @@ -17,7 +17,7 @@ module config_latch ( reg q_reg; //-------------Code Starts Here--------- -always @ ( posedge resetb) begin +always @ (resetb or wl or bl) begin if (~resetb) begin q_reg <= 1'b0; end else if (1'b1 == wl) begin