diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py
index 23a655e02..2e72fb7fe 100644
--- a/openfpga_flow/scripts/run_fpga_flow.py
+++ b/openfpga_flow/scripts/run_fpga_flow.py
@@ -867,8 +867,8 @@ def collect_files_for_vpr():
 
     # Sanitize provided Benchmark option
     if not os.path.isfile(args.base_verilog or ""):
-        logger.error("Base Verilog File - %s" % args.base_verilog)
-        clean_up_and_exit("Provided base_verilog file not found")
+        logger.warning("Base Verilog File - %s", args.base_verilog)
+        return
     shutil.copy(args.base_verilog, args.top_module + "_output_verilog.v")
 
 
diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py
index e215a3f50..8278331f6 100644
--- a/openfpga_flow/scripts/run_fpga_task.py
+++ b/openfpga_flow/scripts/run_fpga_task.py
@@ -352,13 +352,6 @@ def generate_each_task_actions(taskname):
                 else:
                     CurrBenchPara["activity_file"] = SynthSection.get(bech_name + "_act")
 
-            # Check if base verilog file exists
-            if not SynthSection.get(bech_name + "_verilog"):
-                clean_up_and_exit(
-                    "Missing argument %s for vpr_blif flow" % (bech_name + "_verilog")
-                )
-            CurrBenchPara["verilog_file"] = SynthSection.get(bech_name + "_verilog")
-
         # Add script parameter list in current benchmark
         ScriptSections = [x for x in TaskFileSections if "SCRIPT_PARAM" in x]
         script_para_list = {}
@@ -367,10 +360,23 @@ def generate_each_task_actions(taskname):
             for key, values in task_conf[eachset].items():
                 command += ["--" + key, values] if values else ["--" + key]
 
+
+            if "end_flow_with_test" in command:
+                # Verilog script is only required when end_flow_with_test defined
+                # Check if base verilog file exists
+                if not SynthSection.get(bech_name + "_verilog"):
+                    clean_up_and_exit(
+                        "Missing argument %s for vpr_blif flow" % (bech_name + "_verilog")
+                )
+
             # Set label for Sript Parameters
             set_lbl = eachset.replace("SCRIPT_PARAM", "")
             set_lbl = set_lbl[1:] if set_lbl else "Common"
             script_para_list[set_lbl] = command
+
+
+            CurrBenchPara["verilog_file"] = SynthSection.get(bech_name + "_verilog")
+
         CurrBenchPara["script_params"] = script_para_list
 
         benchmark_list.append(CurrBenchPara)