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[Test] Add full VTR benchmark (with most commented); ready for massive testing

This commit is contained in:
tangxifan 2021-03-20 21:01:18 -06:00
parent 2bd8ef2af9
commit 125e94a6b3
1 changed files with 47 additions and 4 deletions
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51
openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf
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@ -30,14 +30,57 @@ yosys_dsp_map_parameters=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINW
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml
[BENCHMARKS] [BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v # Official benchmarks from VTR benchmark release
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/diffeq1.v bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/bgm.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/blob_merge.v
# Failed due to an unknown error in VPR netlist parser
#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/boundtop.v
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v
bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/diffeq1.v
bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/diffeq2.v
#bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/LU8PEEng.v
#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/LU32PEEng.v
#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mcml.v
#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mkDelayWorker32B.v
#bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mkPktMerge.v
#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mkSMAdapter4B.v
#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/or1200.v
#bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/raygentop.v
#bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/sha.v
#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision0.v
#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision1.v
#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision2.v
#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision3.v
# Additional benchmarks after VTR benchmark release
#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/arm_core.v
#bench20=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/spree.v
#bench21=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/LU64PEEng.v
[SYNTHESIS_PARAM] [SYNTHESIS_PARAM]
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys
# Benchmark ch_intrinsics # Benchmark ch_intrinsics
bench0_top = memset bench0_top = bgm
bench1_top = diffeq_paj_convert bench1_top = RLE_BlobMerging
bench2_top = paj_boundtop_hierarchy_no_mem
bench3_top = memset
bench4_top = diffeq_paj_convert
bench5_top = diffeq_f_systemC
bench6_top = LU8PEEng
bench7_top = LU32PEEng
bench8_top = mcml
bench9_top = mkDelayWorker32B
bench10_top = mkPktMerge
bench11_top = mkSMAdapter4B
bench12_top = or1200_flat
bench13_top = paj_raygentop_hierarchy_no_mem
bench14_top = sha1
bench15_top = sv_chip0_hierarchy_no_mem
bench16_top = sv_chip1_hierarchy_no_mem
bench17_top = sv_chip2_hierarchy_no_mem
bench18_top = sv_chip3_hierarchy_no_mem
bench19_top = arm_core
bench20_top = system
bench21_top = LU64PEEng
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test= #end_flow_with_test=