diff --git a/openfpga/src/base/openfpga_verilog_command_template.h b/openfpga/src/base/openfpga_verilog_command_template.h
index e2e1fabd1..4e2efe0e8 100644
--- a/openfpga/src/base/openfpga_verilog_command_template.h
+++ b/openfpga/src/base/openfpga_verilog_command_template.h
@@ -33,9 +33,11 @@ ShellCommandId add_write_fabric_verilog_command_template(
   /* Add an option '--constant_undriven_inputs' */
   CommandOptionId const_undriven_inputs_opt = shell_cmd.add_option(
     "constant_undriven_inputs", true,
-    "Can be [none|bus0|bus1|bit0|bit1]. Use constant vdd/gnd for undriven wires in Verilog netlists. Recommand to "
+    "Can be [none|bus0|bus1|bit0|bit1]. Use constant vdd/gnd for undriven "
+    "wires in Verilog netlists. Recommand to "
     "enable when there are boundary routing tracks in FPGA fabric");
-  shell_cmd.set_option_require_value(const_undriven_inputs_opt, openfpga::OPT_STRING);
+  shell_cmd.set_option_require_value(const_undriven_inputs_opt,
+                                     openfpga::OPT_STRING);
 
   /* Add an option '--explicit_port_mapping' */
   shell_cmd.add_option("explicit_port_mapping", false,
diff --git a/openfpga/src/base/openfpga_verilog_template.h b/openfpga/src/base/openfpga_verilog_template.h
index c9b4ff849..dd024c72c 100644
--- a/openfpga/src/base/openfpga_verilog_template.h
+++ b/openfpga/src/base/openfpga_verilog_template.h
@@ -58,14 +58,17 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd,
   }
   options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
   options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing());
-  /* For perimeter cb, enable the constant-zero undriven inputs, unless it is defined by
-   * user. Throw error if the constant inputs are not selected! */
+  /* For perimeter cb, enable the constant-zero undriven inputs, unless it is
+   * defined by user. Throw error if the constant inputs are not selected! */
   if (cmd_context.option_enable(cmd, opt_constant_undriven_inputs)) {
-    options.set_constant_undriven_inputs(cmd_context.option_value(cmd, opt_constant_undriven_inputs));
+    options.set_constant_undriven_inputs(
+      cmd_context.option_value(cmd, opt_constant_undriven_inputs));
   }
   if (g_vpr_ctx.device().arch->perimeter_cb) {
-    if (FabricVerilogOption::e_undriven_input_type::NONE == options.constant_undriven_inputs()) {
-      options.set_constant_undriven_inputs(FabricVerilogOption::e_undriven_input_type::BUS0);
+    if (FabricVerilogOption::e_undriven_input_type::NONE ==
+        options.constant_undriven_inputs()) {
+      options.set_constant_undriven_inputs(
+        FabricVerilogOption::e_undriven_input_type::BUS0);
       VTR_LOG(
         "Automatically enable the constant_undriven_input option as perimeter "
         "connection blocks are seen in FPGA fabric\n");
diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp
index 571cca4df..0dafb4414 100644
--- a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp
+++ b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp
@@ -22,7 +22,8 @@ FabricVerilogOption::FabricVerilogOption() {
   time_stamp_ = true;
   use_relative_path_ = false;
   constant_undriven_inputs_ = FabricVerilogOption::e_undriven_input_type::NONE;
-  CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_ = {"none", "bus0", "bus1", "bit0", "bit1"};
+  CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_ = {"none", "bus0", "bus1", "bit0",
+                                          "bit1"};
   verbose_output_ = false;
 }
 
@@ -55,18 +56,23 @@ e_verilog_default_net_type FabricVerilogOption::default_net_type() const {
   return default_net_type_;
 }
 
-FabricVerilogOption::e_undriven_input_type FabricVerilogOption::constant_undriven_inputs() const {
+FabricVerilogOption::e_undriven_input_type
+FabricVerilogOption::constant_undriven_inputs() const {
   return constant_undriven_inputs_;
 }
 
 bool FabricVerilogOption::constant_undriven_inputs_use_bus() const {
-  return constant_undriven_inputs_ == FabricVerilogOption::e_undriven_input_type::BUS0
-       || constant_undriven_inputs_ == FabricVerilogOption::e_undriven_input_type::BUS1;
+  return constant_undriven_inputs_ ==
+           FabricVerilogOption::e_undriven_input_type::BUS0 ||
+         constant_undriven_inputs_ ==
+           FabricVerilogOption::e_undriven_input_type::BUS1;
 }
 
 size_t FabricVerilogOption::constant_undriven_inputs_value() const {
-  if (constant_undriven_inputs_ == FabricVerilogOption::e_undriven_input_type::BUS1
-       || constant_undriven_inputs_ == FabricVerilogOption::e_undriven_input_type::BIT1) {
+  if (constant_undriven_inputs_ ==
+        FabricVerilogOption::e_undriven_input_type::BUS1 ||
+      constant_undriven_inputs_ ==
+        FabricVerilogOption::e_undriven_input_type::BIT1) {
     return 1;
   }
   return 0;
@@ -74,8 +80,11 @@ size_t FabricVerilogOption::constant_undriven_inputs_value() const {
 
 std::string FabricVerilogOption::full_constant_undriven_input_type_str() const {
   std::string full_type_str("[");
-  for (size_t itype = 0; itype < size_t(FabricVerilogOption::e_undriven_input_type::NUM_TYPES); ++itype) {
-    full_type_str += std::string(CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_[itype]) + std::string("|");
+  for (size_t itype = 0;
+       itype < size_t(FabricVerilogOption::e_undriven_input_type::NUM_TYPES);
+       ++itype) {
+    full_type_str += std::string(CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_[itype]) +
+                     std::string("|");
   }
   full_type_str.pop_back();
   full_type_str += std::string("]");
@@ -135,22 +144,29 @@ void FabricVerilogOption::set_default_net_type(
   }
 }
 
-bool FabricVerilogOption::set_constant_undriven_inputs(const std::string& type_str) {
+bool FabricVerilogOption::set_constant_undriven_inputs(
+  const std::string& type_str) {
   bool valid_type = false;
-  for (size_t itype = 0; itype < size_t(FabricVerilogOption::e_undriven_input_type::NUM_TYPES); ++itype) {
+  for (size_t itype = 0;
+       itype < size_t(FabricVerilogOption::e_undriven_input_type::NUM_TYPES);
+       ++itype) {
     if (std::string(CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_[itype]) == type_str) {
-      constant_undriven_inputs_ = static_cast<FabricVerilogOption::e_undriven_input_type>(itype);
+      constant_undriven_inputs_ =
+        static_cast<FabricVerilogOption::e_undriven_input_type>(itype);
       valid_type = true;
       break;
     }
   }
   if (!valid_type) {
-    VTR_LOG_ERROR("Invalid types for undriven inputs: %s. Expect %s\n", type_str.c_str(), full_constant_undriven_input_type_str().c_str());
+    VTR_LOG_ERROR("Invalid types for undriven inputs: %s. Expect %s\n",
+                  type_str.c_str(),
+                  full_constant_undriven_input_type_str().c_str());
   }
   return valid_type;
 }
 
-bool FabricVerilogOption::set_constant_undriven_inputs(const FabricVerilogOption::e_undriven_input_type& type) {
+bool FabricVerilogOption::set_constant_undriven_inputs(
+  const FabricVerilogOption::e_undriven_input_type& type) {
   constant_undriven_inputs_ = type;
   return type != FabricVerilogOption::e_undriven_input_type::NUM_TYPES;
 }
diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.h b/openfpga/src/fpga_verilog/fabric_verilog_options.h
index 9e29a9585..83483112a 100644
--- a/openfpga/src/fpga_verilog/fabric_verilog_options.h
+++ b/openfpga/src/fpga_verilog/fabric_verilog_options.h
@@ -16,14 +16,15 @@ namespace openfpga {
  *******************************************************************/
 class FabricVerilogOption {
  public: /* Types */
-   enum class e_undriven_input_type {
-     NONE = 0, /* Leave undriven input to be dangling */
-     BUS0, /* Wire to a bus format of constant 0 */
-     BUS1, /* Wire to a bus format of constant 1 */
-     BIT0, /* Wire to a blast-bit format of constant 0 */
-     BIT1, /* Wire to a blast-bit format of constant 1 */
-     NUM_TYPES
-   };
+  enum class e_undriven_input_type {
+    NONE = 0, /* Leave undriven input to be dangling */
+    BUS0,     /* Wire to a bus format of constant 0 */
+    BUS1,     /* Wire to a bus format of constant 1 */
+    BIT0,     /* Wire to a blast-bit format of constant 0 */
+    BIT1,     /* Wire to a blast-bit format of constant 1 */
+    NUM_TYPES
+  };
+
  public: /* Public constructor */
   /* Set default options */
   FabricVerilogOption();
@@ -38,9 +39,11 @@ class FabricVerilogOption {
   e_verilog_default_net_type default_net_type() const;
   bool print_user_defined_template() const;
   e_undriven_input_type constant_undriven_inputs() const;
-  /* Identify if a bus format should be applied when wiring undriven inputs to constants */
+  /* Identify if a bus format should be applied when wiring undriven inputs to
+   * constants */
   bool constant_undriven_inputs_use_bus() const;
-  /* Identify the logic value should be applied when wiring undriven inputs to constants */
+  /* Identify the logic value should be applied when wiring undriven inputs to
+   * constants */
   size_t constant_undriven_inputs_value() const;
   std::string full_constant_undriven_input_type_str() const;
   bool verbose_output() const;
@@ -54,9 +57,9 @@ class FabricVerilogOption {
   void set_compress_routing(const bool& enabled);
   void set_print_user_defined_template(const bool& enabled);
   void set_default_net_type(const std::string& default_net_type);
-  /** Decode the type from string to enumeration 
-   * "none" -> NONE, "bus0" -> BUS0, "bus1" -> BUS1, "bit0" -> BIT0, "bit1" -> BIT1
-   * For invalid types, error out
+  /** Decode the type from string to enumeration
+   * "none" -> NONE, "bus0" -> BUS0, "bus1" -> BUS1, "bit0" -> BIT0, "bit1" ->
+   * BIT1 For invalid types, error out
    */
   bool set_constant_undriven_inputs(const std::string& type_str);
   /** For invalid types, error out */
@@ -73,7 +76,10 @@ class FabricVerilogOption {
   bool time_stamp_;
   bool use_relative_path_;
   e_undriven_input_type constant_undriven_inputs_;
-  std::array<const char*, size_t(FabricVerilogOption::e_undriven_input_type::NUM_TYPES)> CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_; //String versions of constant undriven input types
+  std::array<const char*,
+             size_t(FabricVerilogOption::e_undriven_input_type::NUM_TYPES)>
+    CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_;  // String versions of constant
+                                           // undriven input types
   bool verbose_output_;
 };
 
diff --git a/openfpga/src/fpga_verilog/verilog_grid.cpp b/openfpga/src/fpga_verilog/verilog_grid.cpp
index 37b1bb526..f5cc2acf4 100644
--- a/openfpga/src/fpga_verilog/verilog_grid.cpp
+++ b/openfpga/src/fpga_verilog/verilog_grid.cpp
@@ -115,7 +115,8 @@ static void print_verilog_primitive_block(
   /* Write the verilog module */
   FabricVerilogOption curr_options = options;
   curr_options.set_explicit_port_mapping(true);
-  write_verilog_module_to_file(fp, module_manager, primitive_module, curr_options);
+  write_verilog_module_to_file(fp, module_manager, primitive_module,
+                               curr_options);
 
   /* Close file handler */
   fp.close();
@@ -233,8 +234,7 @@ static void rec_print_verilog_logical_tile(
           std::string(physical_pb_type->name) + " -----"));
 
   /* Write the verilog module */
-  write_verilog_module_to_file(
-    fp, module_manager, pb_module, options);
+  write_verilog_module_to_file(fp, module_manager, pb_module, options);
 
   print_verilog_comment(
     fp,
@@ -346,8 +346,7 @@ static void print_verilog_physical_tile_netlist(
   print_verilog_comment(
     fp, std::string("----- BEGIN Grid Verilog module: " +
                     module_manager.module_name(grid_module) + " -----"));
-  write_verilog_module_to_file(
-    fp, module_manager, grid_module, options);
+  write_verilog_module_to_file(fp, module_manager, grid_module, options);
 
   print_verilog_comment(
     fp, std::string("----- END Grid Verilog module: " +
diff --git a/openfpga/src/fpga_verilog/verilog_lut.cpp b/openfpga/src/fpga_verilog/verilog_lut.cpp
index fb5a143a1..267ff8f15 100644
--- a/openfpga/src/fpga_verilog/verilog_lut.cpp
+++ b/openfpga/src/fpga_verilog/verilog_lut.cpp
@@ -62,9 +62,8 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager,
     FabricVerilogOption curr_options = options;
     curr_options.set_explicit_port_mapping(
       options.explicit_port_mapping() ||
-        circuit_lib.dump_explicit_port_map(lut_model));
-    write_verilog_module_to_file(
-      fp, module_manager, lut_module, curr_options);
+      circuit_lib.dump_explicit_port_map(lut_model));
+    write_verilog_module_to_file(fp, module_manager, lut_module, curr_options);
   }
 
   /* Close the file handler */
diff --git a/openfpga/src/fpga_verilog/verilog_memory.cpp b/openfpga/src/fpga_verilog/verilog_memory.cpp
index 39ed7ea83..d3799264a 100644
--- a/openfpga/src/fpga_verilog/verilog_memory.cpp
+++ b/openfpga/src/fpga_verilog/verilog_memory.cpp
@@ -60,9 +60,9 @@ static void print_verilog_mux_memory_module(
       FabricVerilogOption curr_options = options;
       curr_options.set_explicit_port_mapping(
         options.explicit_port_mapping() ||
-          circuit_lib.dump_explicit_port_map(mux_model));
-      write_verilog_module_to_file(
-        fp, module_manager, mem_module, curr_options);
+        circuit_lib.dump_explicit_port_map(mux_model));
+      write_verilog_module_to_file(fp, module_manager, mem_module,
+                                   curr_options);
 
       /* Add an empty line as a splitter */
       fp << std::endl;
@@ -81,8 +81,8 @@ static void print_verilog_mux_memory_module(
       if (module_manager.valid_module_id(feedthru_mem_module)) {
         VTR_ASSERT(true == module_manager.valid_module_id(feedthru_mem_module));
         /* Write the module content in Verilog format */
-        write_verilog_module_to_file(
-          fp, module_manager, feedthru_mem_module, curr_options);
+        write_verilog_module_to_file(fp, module_manager, feedthru_mem_module,
+                                     curr_options);
 
         /* Add an empty line as a splitter */
         fp << std::endl;
@@ -206,7 +206,7 @@ void print_verilog_submodule_memories(
     FabricVerilogOption curr_options = options;
     curr_options.set_explicit_port_mapping(
       options.explicit_port_mapping() ||
-        circuit_lib.dump_explicit_port_map(model));
+      circuit_lib.dump_explicit_port_map(model));
     write_verilog_module_to_file(fp, module_manager, mem_module, curr_options);
 
     /* Add an empty line as a splitter */
@@ -236,8 +236,7 @@ void print_verilog_submodule_memories(
   for (ModuleId mem_group_module : module_manager.modules_by_usage(
          ModuleManager::e_module_usage_type::MODULE_CONFIG_GROUP)) {
     /* Write the module content in Verilog format */
-    write_verilog_module_to_file(
-      fp, module_manager, mem_group_module, options);
+    write_verilog_module_to_file(fp, module_manager, mem_group_module, options);
 
     /* Add an empty line as a splitter */
     fp << std::endl;
diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
index 11f063f46..72599e4bc 100644
--- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp
+++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
@@ -570,10 +570,10 @@ static void write_verilog_instance_to_file(std::fstream& fp,
  * This is a key function, maybe most frequently called in our Verilog writer
  * Note that file stream must be valid
  *******************************************************************/
-void write_verilog_module_to_file(
-  std::fstream& fp, const ModuleManager& module_manager,
-  const ModuleId& module_id,
-  const FabricVerilogOption& options) {
+void write_verilog_module_to_file(std::fstream& fp,
+                                  const ModuleManager& module_manager,
+                                  const ModuleId& module_id,
+                                  const FabricVerilogOption& options) {
   VTR_ASSERT(true == valid_file_stream(fp));
 
   /* Ensure we have a valid module_id */
@@ -604,7 +604,8 @@ void write_verilog_module_to_file(
   }
 
   /* Use constant to drive undriven local wires */
-  if (options.constant_undriven_inputs() != FabricVerilogOption::e_undriven_input_type::NONE) {
+  if (options.constant_undriven_inputs() !=
+      FabricVerilogOption::e_undriven_input_type::NONE) {
     std::vector<ModuleManager::e_module_port_type> blacklist = {
       ModuleManager::e_module_port_type::MODULE_GLOBAL_PORT,
       ModuleManager::e_module_port_type::MODULE_GPIN_PORT,
@@ -622,11 +623,13 @@ void write_verilog_module_to_file(
         if (options.constant_undriven_inputs_use_bus()) {
           print_verilog_wire_constant_values(
             fp, local_undriven_wire,
-            std::vector<size_t>(local_undriven_wire.get_width(), options.constant_undriven_inputs_value()));
+            std::vector<size_t>(local_undriven_wire.get_width(),
+                                options.constant_undriven_inputs_value()));
         } else {
           print_verilog_wire_constant_values_bit_blast(
             fp, local_undriven_wire,
-            std::vector<size_t>(local_undriven_wire.get_width(), options.constant_undriven_inputs_value()));
+            std::vector<size_t>(local_undriven_wire.get_width(),
+                                options.constant_undriven_inputs_value()));
         }
       }
     }
diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.h b/openfpga/src/fpga_verilog/verilog_module_writer.h
index c24b05d1c..3c4c024e5 100644
--- a/openfpga/src/fpga_verilog/verilog_module_writer.h
+++ b/openfpga/src/fpga_verilog/verilog_module_writer.h
@@ -6,9 +6,9 @@
  *******************************************************************/
 #include <fstream>
 
+#include "fabric_verilog_options.h"
 #include "module_manager.h"
 #include "verilog_port_types.h"
-#include "fabric_verilog_options.h"
 
 /********************************************************************
  * Function declaration
@@ -17,10 +17,10 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void write_verilog_module_to_file(
-  std::fstream& fp, const ModuleManager& module_manager,
-  const ModuleId& module_id, 
-  const FabricVerilogOption& options);
+void write_verilog_module_to_file(std::fstream& fp,
+                                  const ModuleManager& module_manager,
+                                  const ModuleId& module_id,
+                                  const FabricVerilogOption& options);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/fpga_verilog/verilog_mux.cpp b/openfpga/src/fpga_verilog/verilog_mux.cpp
index 2fca08df4..d4844b080 100644
--- a/openfpga/src/fpga_verilog/verilog_mux.cpp
+++ b/openfpga/src/fpga_verilog/verilog_mux.cpp
@@ -677,11 +677,11 @@ static void generate_verilog_mux_branch_module(
         FabricVerilogOption curr_options = options;
         curr_options.set_explicit_port_mapping(
           curr_options.explicit_port_mapping() ||
-            circuit_lib.dump_explicit_port_map(mux_model));
-        curr_options.set_constant_undriven_inputs(FabricVerilogOption::e_undriven_input_type::NONE);
-        write_verilog_module_to_file(
-          fp, module_manager, mux_module,
-          curr_options);
+          circuit_lib.dump_explicit_port_map(mux_model));
+        curr_options.set_constant_undriven_inputs(
+          FabricVerilogOption::e_undriven_input_type::NONE);
+        write_verilog_module_to_file(fp, module_manager, mux_module,
+                                     curr_options);
         /* Add an empty line as a splitter */
         fp << std::endl;
       } else {
@@ -694,7 +694,8 @@ static void generate_verilog_mux_branch_module(
     case CIRCUIT_MODEL_DESIGN_RRAM:
       generate_verilog_rram_mux_branch_module(
         module_manager, circuit_lib, fp, mux_model, module_name, mux_graph,
-        options.default_net_type(), circuit_lib.dump_structural_verilog(mux_model));
+        options.default_net_type(),
+        circuit_lib.dump_structural_verilog(mux_model));
       break;
     default:
       VTR_LOGF_ERROR(__FILE__, __LINE__,
@@ -1403,8 +1404,7 @@ static void generate_verilog_rram_mux_module(
 static void generate_verilog_mux_module(
   ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
   std::fstream& fp, const CircuitModelId& mux_model, const MuxGraph& mux_graph,
-  const ModuleNameMap& module_name_map,
-  const FabricVerilogOption& options) {
+  const ModuleNameMap& module_name_map, const FabricVerilogOption& options) {
   std::string module_name =
     generate_mux_subckt_name(circuit_lib, mux_model,
                              find_mux_num_datapath_inputs(
@@ -1424,12 +1424,11 @@ static void generate_verilog_mux_module(
         (curr_options.explicit_port_mapping() ||
          circuit_lib.dump_explicit_port_map(mux_model) ||
          circuit_lib.dump_explicit_port_map(
-           circuit_lib.pass_gate_logic_model(mux_model)))
-      );
-      curr_options.set_constant_undriven_inputs(FabricVerilogOption::e_undriven_input_type::NONE);
-      write_verilog_module_to_file(
-        fp, module_manager, mux_module,
-        curr_options);
+           circuit_lib.pass_gate_logic_model(mux_model))));
+      curr_options.set_constant_undriven_inputs(
+        FabricVerilogOption::e_undriven_input_type::NONE);
+      write_verilog_module_to_file(fp, module_manager, mux_module,
+                                   curr_options);
       /* Add an empty line as a splitter */
       fp << std::endl;
       break;
diff --git a/openfpga/src/fpga_verilog/verilog_routing.cpp b/openfpga/src/fpga_verilog/verilog_routing.cpp
index aed1cacf8..f346b7087 100644
--- a/openfpga/src/fpga_verilog/verilog_routing.cpp
+++ b/openfpga/src/fpga_verilog/verilog_routing.cpp
@@ -115,8 +115,7 @@ static void print_verilog_routing_connection_box_unique_module(
   VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
 
   /* Write the verilog module */
-  write_verilog_module_to_file(
-    fp, module_manager, cb_module, options);
+  write_verilog_module_to_file(fp, module_manager, cb_module, options);
 
   /* Add an empty line as a splitter */
   fp << std::endl;
@@ -235,8 +234,7 @@ static void print_verilog_routing_switch_box_unique_module(
   VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
 
   /* Write the verilog module */
-  write_verilog_module_to_file(
-    fp, module_manager, sb_module, options);
+  write_verilog_module_to_file(fp, module_manager, sb_module, options);
 
   /* Close file handler */
   fp.close();
diff --git a/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp b/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp
index 2ce5687c3..67ccdb4af 100644
--- a/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp
+++ b/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp
@@ -56,8 +56,7 @@ void print_verilog_submodule_shift_register_banks(
   for (const ModuleId& sr_module : blwl_sr_banks.bl_bank_unique_modules()) {
     VTR_ASSERT(true == module_manager.valid_module_id(sr_module));
     /* Write the module content in Verilog format */
-    write_verilog_module_to_file(
-      fp, module_manager, sr_module, options);
+    write_verilog_module_to_file(fp, module_manager, sr_module, options);
 
     /* Add an empty line as a splitter */
     fp << std::endl;
@@ -66,8 +65,7 @@ void print_verilog_submodule_shift_register_banks(
   for (const ModuleId& sr_module : blwl_sr_banks.wl_bank_unique_modules()) {
     VTR_ASSERT(true == module_manager.valid_module_id(sr_module));
     /* Write the module content in Verilog format */
-    write_verilog_module_to_file(
-      fp, module_manager, sr_module, options);
+    write_verilog_module_to_file(fp, module_manager, sr_module, options);
 
     /* Add an empty line as a splitter */
     fp << std::endl;
diff --git a/openfpga/src/fpga_verilog/verilog_tile.cpp b/openfpga/src/fpga_verilog/verilog_tile.cpp
index 85ba9385a..9de47fe16 100644
--- a/openfpga/src/fpga_verilog/verilog_tile.cpp
+++ b/openfpga/src/fpga_verilog/verilog_tile.cpp
@@ -58,8 +58,7 @@ static int print_verilog_tile_module_netlist(
                             options.time_stamp());
 
   /* Write the module content in Verilog format */
-  write_verilog_module_to_file(
-    fp, module_manager, tile_module, options);
+  write_verilog_module_to_file(fp, module_manager, tile_module, options);
 
   /* Add an empty line as a splitter */
   fp << std::endl;
diff --git a/openfpga/src/fpga_verilog/verilog_top_module.cpp b/openfpga/src/fpga_verilog/verilog_top_module.cpp
index f7eb7db5f..9812e9db5 100644
--- a/openfpga/src/fpga_verilog/verilog_top_module.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_module.cpp
@@ -61,8 +61,7 @@ void print_verilog_core_module(NetlistManager& netlist_manager,
                             options.time_stamp());
 
   /* Write the module content in Verilog format */
-  write_verilog_module_to_file(
-    fp, module_manager, core_module, options);
+  write_verilog_module_to_file(fp, module_manager, core_module, options);
 
   /* Add an empty line as a splitter */
   fp << std::endl;
@@ -126,8 +125,7 @@ void print_verilog_top_module(NetlistManager& netlist_manager,
     fp, std::string("Top-level Verilog module for FPGA"), options.time_stamp());
 
   /* Write the module content in Verilog format */
-  write_verilog_module_to_file(
-    fp, module_manager, top_module, options);
+  write_verilog_module_to_file(fp, module_manager, top_module, options);
 
   /* Add an empty line as a splitter */
   fp << std::endl;
diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
index aef6cf5fa..2dab191cd 100644
--- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
@@ -843,7 +843,9 @@ void print_verilog_wire_constant_values_bit_blast(
 
   for (size_t ipin : output_port.pins()) {
     BasicPort curr_pin(output_port.get_name(), ipin, ipin);
-    print_verilog_wire_constant_values(fp, curr_pin, std::vector<size_t>(curr_pin.get_width(), const_values[ipin]));
+    print_verilog_wire_constant_values(
+      fp, curr_pin,
+      std::vector<size_t>(curr_pin.get_width(), const_values[ipin]));
   }
 }