From 12134f4106771bfb75632ac2ce4b05598349aead Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 6 Jan 2023 17:48:00 -0800 Subject: [PATCH] [core] now openfpga verilog commands follow templates --- openfpga/src/base/openfpga_verilog.h | 38 -- .../src/base/openfpga_verilog_command.cpp | 437 +---------------- .../base/openfpga_verilog_command_template.h | 460 ++++++++++++++++++ ...erilog.cpp => openfpga_verilog_template.h} | 38 +- 4 files changed, 481 insertions(+), 492 deletions(-) delete mode 100644 openfpga/src/base/openfpga_verilog.h create mode 100644 openfpga/src/base/openfpga_verilog_command_template.h rename openfpga/src/base/{openfpga_verilog.cpp => openfpga_verilog_template.h} (95%) diff --git a/openfpga/src/base/openfpga_verilog.h b/openfpga/src/base/openfpga_verilog.h deleted file mode 100644 index 34b967d0a..000000000 --- a/openfpga/src/base/openfpga_verilog.h +++ /dev/null @@ -1,38 +0,0 @@ -#ifndef OPENFPGA_VERILOG_H -#define OPENFPGA_VERILOG_H - -/******************************************************************** - * Include header files that are required by function declaration - *******************************************************************/ -#include "command.h" -#include "command_context.h" -#include "openfpga_context.h" - -/******************************************************************** - * Function declaration - *******************************************************************/ - -/* begin namespace openfpga */ -namespace openfpga { - -int write_fabric_verilog(OpenfpgaContext& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context); - -int write_full_testbench(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, const CommandContext& cmd_context); - -int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, - const CommandContext& cmd_context); - -int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, - const CommandContext& cmd_context); - -int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, - const CommandContext& cmd_context); - -} /* end namespace openfpga */ - -#endif diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp index 6ce1ea193..5af5e000a 100644 --- a/openfpga/src/base/openfpga_verilog_command.cpp +++ b/openfpga/src/base/openfpga_verilog_command.cpp @@ -5,447 +5,14 @@ * - generate_fabric_verilog : generate Verilog netlists about FPGA fabric * - generate_fabric_verilog_testbench : TODO: generate Verilog testbenches *******************************************************************/ +#include "openfpga_verilog_command_template.h" #include "openfpga_verilog_command.h" -#include "openfpga_verilog.h" - /* begin namespace openfpga */ namespace openfpga { -/******************************************************************** - * - Add a command to Shell environment: generate fabric Verilog - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_fabric_verilog_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_fabric_verilog"); - - /* Add an option '--file' in short '-f'*/ - CommandOptionId output_opt = shell_cmd.add_option( - "file", true, "Specify the output directory for Verilog netlists"); - shell_cmd.set_option_short_name(output_opt, "f"); - shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); - - /* Add an option '--explicit_port_mapping' */ - shell_cmd.add_option("explicit_port_mapping", false, - "Use explicit port mapping in Verilog netlists"); - - /* Add an option '--include_timing' */ - shell_cmd.add_option("include_timing", false, - "Enable timing annotation in Verilog netlists"); - - /* Add an option '--print_user_defined_template' */ - shell_cmd.add_option( - "print_user_defined_template", false, - "Generate a template Verilog files for user-defined circuit models"); - - /* Add an option '--default_net_type' */ - CommandOptionId default_net_type_opt = shell_cmd.add_option( - "default_net_type", false, - "Set the default net type for Verilog netlists. Default value is 'none'"); - shell_cmd.set_option_require_value(default_net_type_opt, - openfpga::OPT_STRING); - - /* Add an option '--no_time_stamp' */ - shell_cmd.add_option("no_time_stamp", false, - "Do not print a time stamp in the output files"); - - /* Add an option '--use_relative_path' */ - shell_cmd.add_option( - "use_relative_path", false, - "Force to use relative path in netlists when including other netlists"); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Enable verbose output"); - - /* Add command 'write_fabric_verilog' to the Shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, "generate Verilog netlists modeling full FPGA fabric"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, write_fabric_verilog); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - add a command to shell environment: write full testbench - * - add associated options - * - add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_full_testbench_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_full_testbench"); - - /* add an option '--file' in short '-f'*/ - CommandOptionId output_opt = shell_cmd.add_option( - "file", true, "specify the output directory for hdl netlists"); - shell_cmd.set_option_short_name(output_opt, "f"); - shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); - - /* add an option '--bitstream'*/ - CommandOptionId bitstream_opt = shell_cmd.add_option( - "bitstream", true, "specify the bitstream to be loaded in the testbench"); - shell_cmd.set_option_require_value(bitstream_opt, openfpga::OPT_STRING); - - /* add an option '--fabric_netlist_file_path'*/ - CommandOptionId fabric_netlist_opt = - shell_cmd.add_option("fabric_netlist_file_path", false, - "specify the file path to the fabric hdl netlist"); - shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING); - - /* add an option '--pin_constraints_file in short '-pcf' */ - CommandOptionId pcf_opt = - shell_cmd.add_option("pin_constraints_file", false, - "specify the file path to the pin constraints"); - shell_cmd.set_option_short_name(pcf_opt, "pcf"); - shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING); - - /* add an option '--bus_group_file in short '-bgf' */ - CommandOptionId bgf_opt = shell_cmd.add_option( - "bus_group_file", false, "specify the file path to the group pins to bus"); - shell_cmd.set_option_short_name(bgf_opt, "bgf"); - shell_cmd.set_option_require_value(bgf_opt, openfpga::OPT_STRING); - - /* add an option '--reference_benchmark_file_path'*/ - CommandOptionId ref_bm_opt = shell_cmd.add_option( - "reference_benchmark_file_path", false, - "specify the file path to the reference verilog netlist. If specified, the " - "testbench will include self-checking codes"); - shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING); - - /* add an option '--fast_configuration' */ - shell_cmd.add_option( - "fast_configuration", false, - "reduce the period of configuration by skip certain data points"); - - /* add an option '--explicit_port_mapping' */ - shell_cmd.add_option("explicit_port_mapping", false, - "use explicit port mapping in verilog netlists"); - - /* Add an option '--default_net_type' */ - CommandOptionId default_net_type_opt = shell_cmd.add_option( - "default_net_type", false, - "Set the default net type for Verilog netlists. Default value is 'none'"); - shell_cmd.set_option_require_value(default_net_type_opt, - openfpga::OPT_STRING); - - /* Add an option '--no_self_checking' */ - shell_cmd.add_option( - "no_self_checking", false, - "Do not generate self-checking codes for Verilog testbenches."); - - /* add an option '--include_signal_init' */ - shell_cmd.add_option("include_signal_init", false, - "initialize all the signals in verilog testbenches"); - - /* Add an option '--no_time_stamp' */ - shell_cmd.add_option("no_time_stamp", false, - "Do not print a time stamp in the output files"); - - /* Add an option '--use_relative_path' */ - shell_cmd.add_option( - "use_relative_path", false, - "Force to use relative path in netlists when including other netlists"); - - /* add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "enable verbose output"); - - /* add command to the shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, "generate full testbenches for an fpga fabric"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, write_full_testbench); - - /* add command dependency to the shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - add a command to shell environment: write preconfigured fabric wrapper - * - add associated options - * - add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_preconfigured_fabric_wrapper_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_preconfigured_fabric_wrapper"); - - /* add an option '--file' in short '-f'*/ - CommandOptionId output_opt = shell_cmd.add_option( - "file", true, "specify the output directory for hdl netlists"); - shell_cmd.set_option_short_name(output_opt, "f"); - shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); - - /* add an option '--fabric_netlist_file_path'*/ - CommandOptionId fabric_netlist_opt = - shell_cmd.add_option("fabric_netlist_file_path", false, - "specify the file path to the fabric hdl netlist"); - shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING); - - /* add an option '--pin_constraints_file in short '-pcf' */ - CommandOptionId pcf_opt = - shell_cmd.add_option("pin_constraints_file", false, - "specify the file path to the pin constraints"); - shell_cmd.set_option_short_name(pcf_opt, "pcf"); - shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING); - - /* add an option '--bus_group_file in short '-bgf' */ - CommandOptionId bgf_opt = shell_cmd.add_option( - "bus_group_file", false, "specify the file path to the group pins to bus"); - shell_cmd.set_option_short_name(bgf_opt, "bgf"); - shell_cmd.set_option_require_value(bgf_opt, openfpga::OPT_STRING); - - /* add an option '--explicit_port_mapping' */ - shell_cmd.add_option("explicit_port_mapping", false, - "use explicit port mapping in verilog netlists"); - - /* Add an option '--default_net_type' */ - CommandOptionId default_net_type_opt = shell_cmd.add_option( - "default_net_type", false, - "Set the default net type for Verilog netlists. Default value is 'none'"); - shell_cmd.set_option_require_value(default_net_type_opt, - openfpga::OPT_STRING); - - /* Add an option '--embed_bitstream' */ - CommandOptionId embed_bitstream_opt = - shell_cmd.add_option("embed_bitstream", false, - "Embed bitstream to the Verilog wrapper netlist; This " - "may cause a large netlist file size"); - shell_cmd.set_option_require_value(embed_bitstream_opt, openfpga::OPT_STRING); - - /* add an option '--include_signal_init' */ - shell_cmd.add_option("include_signal_init", false, - "initialize all the signals in verilog testbenches"); - - /* Add an option '--no_time_stamp' */ - shell_cmd.add_option("no_time_stamp", false, - "Do not print a time stamp in the output files"); - - /* add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "enable verbose output"); - - /* add command to the shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, "generate a wrapper for a pre-configured fpga fabric"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, - write_preconfigured_fabric_wrapper); - - /* add command dependency to the shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: write preconfigured testbench - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_preconfigured_testbench_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_preconfigured_testbench"); - - /* Add an option '--file' in short '-f'*/ - CommandOptionId output_opt = shell_cmd.add_option( - "file", true, "Specify the output directory for HDL netlists"); - shell_cmd.set_option_short_name(output_opt, "f"); - shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); - - /* add an option '--fabric_netlist_file_path'*/ - CommandOptionId fabric_netlist_opt = - shell_cmd.add_option("fabric_netlist_file_path", false, - "specify the file path to the fabric hdl netlist"); - shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING); - - /* Add an option '--pin_constraints_file in short '-pcf' */ - CommandOptionId pcf_opt = - shell_cmd.add_option("pin_constraints_file", false, - "Specify the file path to the pin constraints"); - shell_cmd.set_option_short_name(pcf_opt, "pcf"); - shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING); - - /* add an option '--bus_group_file in short '-bgf' */ - CommandOptionId bgf_opt = shell_cmd.add_option( - "bus_group_file", false, "specify the file path to the group pins to bus"); - shell_cmd.set_option_short_name(bgf_opt, "bgf"); - shell_cmd.set_option_require_value(bgf_opt, openfpga::OPT_STRING); - - /* Add an option '--reference_benchmark_file_path'*/ - CommandOptionId ref_bm_opt = shell_cmd.add_option( - "reference_benchmark_file_path", false, - "Specify the file path to the reference Verilog netlist. If specified, the " - "testbench will include self-checking codes"); - shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING); - - /* Add an option '--explicit_port_mapping' */ - shell_cmd.add_option("explicit_port_mapping", false, - "Use explicit port mapping in Verilog netlists"); - - /* Add an option '--default_net_type' */ - CommandOptionId default_net_type_opt = shell_cmd.add_option( - "default_net_type", false, - "Set the default net type for Verilog netlists. Default value is 'none'"); - shell_cmd.set_option_require_value(default_net_type_opt, - openfpga::OPT_STRING); - - /* Add an option '--no_time_stamp' */ - shell_cmd.add_option("no_time_stamp", false, - "Do not print a time stamp in the output files"); - - /* Add an option '--use_relative_path' */ - shell_cmd.add_option( - "use_relative_path", false, - "Force to use relative path in netlists when including other netlists"); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Enable verbose output"); - - /* Add command to the Shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, "generate testbenches for a preconfigured FPGA fabric"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, - write_preconfigured_testbench); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - -/******************************************************************** - * - Add a command to Shell environment: write simulation task info - * - Add associated options - * - Add command dependency - *******************************************************************/ -static ShellCommandId add_openfpga_write_simulation_task_info_command( - openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_simulation_task_info"); - - /* Add an option '--file' in short '-f'*/ - CommandOptionId output_opt = shell_cmd.add_option( - "file", true, - "Specify the file path to output simulation-related information"); - shell_cmd.set_option_short_name(output_opt, "f"); - shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); - - /* Add an option '--hdl_dir'*/ - CommandOptionId hdl_dir_opt = shell_cmd.add_option( - "hdl_dir", true, - "Specify the directory path where HDL netlists are created"); - shell_cmd.set_option_require_value(hdl_dir_opt, openfpga::OPT_STRING); - - /* Add an option '--reference_benchmark_file_path'*/ - CommandOptionId ref_bm_opt = shell_cmd.add_option( - "reference_benchmark_file_path", false, - "Specify the file path to the reference Verilog netlist. If specified, the " - "testbench will include self-checking codes"); - shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING); - - /* Add an option '--testbench_type'*/ - CommandOptionId tb_type_opt = shell_cmd.add_option( - "testbench_type", false, - "Specify the type of testbenches to be considered. Different testbenches " - "have different simulation parameters."); - shell_cmd.set_option_require_value(tb_type_opt, openfpga::OPT_STRING); - - /* Add an option '--time_unit' */ - CommandOptionId time_unit_opt = - shell_cmd.add_option("time_unit", false, - "Specify the time unit to be used in HDL simulation. " - "Acceptable is [a|f|p|n|u|m|k|M]s"); - shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING); - - /* Add an option '--verbose' */ - shell_cmd.add_option("verbose", false, "Enable verbose output"); - - /* Add command to the Shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, "generate an interchangable simulation task configuration file"); - shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, write_simulation_task_info); - - /* Add command dependency to the Shell */ - shell.set_command_dependency(shell_cmd_id, dependent_cmds); - - return shell_cmd_id; -} - void add_openfpga_verilog_commands(openfpga::Shell& shell) { - /* Get the unique id of 'build_fabric' command which is to be used in creating - * the dependency graph */ - const ShellCommandId& build_fabric_cmd_id = - shell.command(std::string("build_fabric")); - - /* Add a new class of commands */ - ShellCommandClassId openfpga_verilog_cmd_class = - shell.add_command_class("FPGA-Verilog"); - - /******************************** - * Command 'write_fabric_verilog' - */ - /* The 'write_fabric_verilog' command should NOT be executed before - * 'build_fabric' */ - std::vector fabric_verilog_dependent_cmds; - fabric_verilog_dependent_cmds.push_back(build_fabric_cmd_id); - add_openfpga_write_fabric_verilog_command(shell, openfpga_verilog_cmd_class, - fabric_verilog_dependent_cmds); - - /******************************** - * Command 'write_full_testbench' - */ - /* The command 'write_full_testbench' should NOT be executed before - * 'build_fabric' */ - std::vector full_testbench_dependent_cmds; - full_testbench_dependent_cmds.push_back(build_fabric_cmd_id); - add_openfpga_write_full_testbench_command(shell, openfpga_verilog_cmd_class, - full_testbench_dependent_cmds); - - /******************************** - * Command 'write_preconfigured_fabric_wrapper' - */ - /* The command 'write_preconfigured_fabric_wrapper' should NOT be executed - * before 'build_fabric' */ - std::vector preconfig_wrapper_dependent_cmds; - preconfig_wrapper_dependent_cmds.push_back(build_fabric_cmd_id); - add_openfpga_write_preconfigured_fabric_wrapper_command( - shell, openfpga_verilog_cmd_class, preconfig_wrapper_dependent_cmds); - - /******************************** - * Command 'write_preconfigured_testbench' - */ - /* The command 'write_preconfigured_testbench' should NOT be executed before - * 'build_fabric' */ - std::vector preconfig_testbench_dependent_cmds; - preconfig_testbench_dependent_cmds.push_back(build_fabric_cmd_id); - add_openfpga_write_preconfigured_testbench_command( - shell, openfpga_verilog_cmd_class, preconfig_testbench_dependent_cmds); - - /******************************** - * Command 'write_simulation_task_info' - */ - /* The command 'write_simulation_task_info' should NOT be executed before - * 'build_fabric' */ - std::vector sim_task_info_dependent_cmds; - sim_task_info_dependent_cmds.push_back(build_fabric_cmd_id); - add_openfpga_write_simulation_task_info_command( - shell, openfpga_verilog_cmd_class, sim_task_info_dependent_cmds); + add_verilog_command_templates(shell); } } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_verilog_command_template.h b/openfpga/src/base/openfpga_verilog_command_template.h new file mode 100644 index 000000000..60ccfa425 --- /dev/null +++ b/openfpga/src/base/openfpga_verilog_command_template.h @@ -0,0 +1,460 @@ +#ifndef OPENFPGA_VERILOG_COMMAND_TEMPLATE_H +#define OPENFPGA_VERILOG_COMMAND_TEMPLATE_H +/******************************************************************** + * Add commands to the OpenFPGA shell interface, + * in purpose of generate Verilog netlists modeling the full FPGA fabric + * This is one of the core engine of openfpga, including: + * - generate_fabric_verilog : generate Verilog netlists about FPGA fabric + * - generate_fabric_verilog_testbench : TODO: generate Verilog testbenches + *******************************************************************/ +#include "openfpga_verilog_template.h" +#include "shell.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * - Add a command to Shell environment: generate fabric Verilog + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_fabric_verilog_command_template( + openfpga::Shell& shell, + const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds) { + Command shell_cmd("write_fabric_verilog"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId output_opt = shell_cmd.add_option( + "file", true, "Specify the output directory for Verilog netlists"); + shell_cmd.set_option_short_name(output_opt, "f"); + shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + + /* Add an option '--explicit_port_mapping' */ + shell_cmd.add_option("explicit_port_mapping", false, + "Use explicit port mapping in Verilog netlists"); + + /* Add an option '--include_timing' */ + shell_cmd.add_option("include_timing", false, + "Enable timing annotation in Verilog netlists"); + + /* Add an option '--print_user_defined_template' */ + shell_cmd.add_option( + "print_user_defined_template", false, + "Generate a template Verilog files for user-defined circuit models"); + + /* Add an option '--default_net_type' */ + CommandOptionId default_net_type_opt = shell_cmd.add_option( + "default_net_type", false, + "Set the default net type for Verilog netlists. Default value is 'none'"); + shell_cmd.set_option_require_value(default_net_type_opt, + openfpga::OPT_STRING); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print a time stamp in the output files"); + + /* Add an option '--use_relative_path' */ + shell_cmd.add_option( + "use_relative_path", false, + "Force to use relative path in netlists when including other netlists"); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add command 'write_fabric_verilog' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "generate Verilog netlists modeling full FPGA fabric"); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, write_fabric_verilog_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - add a command to shell environment: write full testbench + * - add associated options + * - add command dependency + *******************************************************************/ +template +ShellCommandId add_write_full_testbench_command_template( + openfpga::Shell& shell, + const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds) { + Command shell_cmd("write_full_testbench"); + + /* add an option '--file' in short '-f'*/ + CommandOptionId output_opt = shell_cmd.add_option( + "file", true, "specify the output directory for hdl netlists"); + shell_cmd.set_option_short_name(output_opt, "f"); + shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + + /* add an option '--bitstream'*/ + CommandOptionId bitstream_opt = shell_cmd.add_option( + "bitstream", true, "specify the bitstream to be loaded in the testbench"); + shell_cmd.set_option_require_value(bitstream_opt, openfpga::OPT_STRING); + + /* add an option '--fabric_netlist_file_path'*/ + CommandOptionId fabric_netlist_opt = + shell_cmd.add_option("fabric_netlist_file_path", false, + "specify the file path to the fabric hdl netlist"); + shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING); + + /* add an option '--pin_constraints_file in short '-pcf' */ + CommandOptionId pcf_opt = + shell_cmd.add_option("pin_constraints_file", false, + "specify the file path to the pin constraints"); + shell_cmd.set_option_short_name(pcf_opt, "pcf"); + shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING); + + /* add an option '--bus_group_file in short '-bgf' */ + CommandOptionId bgf_opt = shell_cmd.add_option( + "bus_group_file", false, "specify the file path to the group pins to bus"); + shell_cmd.set_option_short_name(bgf_opt, "bgf"); + shell_cmd.set_option_require_value(bgf_opt, openfpga::OPT_STRING); + + /* add an option '--reference_benchmark_file_path'*/ + CommandOptionId ref_bm_opt = shell_cmd.add_option( + "reference_benchmark_file_path", false, + "specify the file path to the reference verilog netlist. If specified, the " + "testbench will include self-checking codes"); + shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING); + + /* add an option '--fast_configuration' */ + shell_cmd.add_option( + "fast_configuration", false, + "reduce the period of configuration by skip certain data points"); + + /* add an option '--explicit_port_mapping' */ + shell_cmd.add_option("explicit_port_mapping", false, + "use explicit port mapping in verilog netlists"); + + /* Add an option '--default_net_type' */ + CommandOptionId default_net_type_opt = shell_cmd.add_option( + "default_net_type", false, + "Set the default net type for Verilog netlists. Default value is 'none'"); + shell_cmd.set_option_require_value(default_net_type_opt, + openfpga::OPT_STRING); + + /* Add an option '--no_self_checking' */ + shell_cmd.add_option( + "no_self_checking", false, + "Do not generate self-checking codes for Verilog testbenches."); + + /* add an option '--include_signal_init' */ + shell_cmd.add_option("include_signal_init", false, + "initialize all the signals in verilog testbenches"); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print a time stamp in the output files"); + + /* Add an option '--use_relative_path' */ + shell_cmd.add_option( + "use_relative_path", false, + "Force to use relative path in netlists when including other netlists"); + + /* add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "enable verbose output"); + + /* add command to the shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "generate full testbenches for an fpga fabric"); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, write_full_testbench_template); + + /* add command dependency to the shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - add a command to shell environment: write preconfigured fabric wrapper + * - add associated options + * - add command dependency + *******************************************************************/ +template +ShellCommandId add_write_preconfigured_fabric_wrapper_command_template( + openfpga::Shell& shell, + const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds) { + Command shell_cmd("write_preconfigured_fabric_wrapper"); + + /* add an option '--file' in short '-f'*/ + CommandOptionId output_opt = shell_cmd.add_option( + "file", true, "specify the output directory for hdl netlists"); + shell_cmd.set_option_short_name(output_opt, "f"); + shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + + /* add an option '--fabric_netlist_file_path'*/ + CommandOptionId fabric_netlist_opt = + shell_cmd.add_option("fabric_netlist_file_path", false, + "specify the file path to the fabric hdl netlist"); + shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING); + + /* add an option '--pin_constraints_file in short '-pcf' */ + CommandOptionId pcf_opt = + shell_cmd.add_option("pin_constraints_file", false, + "specify the file path to the pin constraints"); + shell_cmd.set_option_short_name(pcf_opt, "pcf"); + shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING); + + /* add an option '--bus_group_file in short '-bgf' */ + CommandOptionId bgf_opt = shell_cmd.add_option( + "bus_group_file", false, "specify the file path to the group pins to bus"); + shell_cmd.set_option_short_name(bgf_opt, "bgf"); + shell_cmd.set_option_require_value(bgf_opt, openfpga::OPT_STRING); + + /* add an option '--explicit_port_mapping' */ + shell_cmd.add_option("explicit_port_mapping", false, + "use explicit port mapping in verilog netlists"); + + /* Add an option '--default_net_type' */ + CommandOptionId default_net_type_opt = shell_cmd.add_option( + "default_net_type", false, + "Set the default net type for Verilog netlists. Default value is 'none'"); + shell_cmd.set_option_require_value(default_net_type_opt, + openfpga::OPT_STRING); + + /* Add an option '--embed_bitstream' */ + CommandOptionId embed_bitstream_opt = + shell_cmd.add_option("embed_bitstream", false, + "Embed bitstream to the Verilog wrapper netlist; This " + "may cause a large netlist file size"); + shell_cmd.set_option_require_value(embed_bitstream_opt, openfpga::OPT_STRING); + + /* add an option '--include_signal_init' */ + shell_cmd.add_option("include_signal_init", false, + "initialize all the signals in verilog testbenches"); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print a time stamp in the output files"); + + /* add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "enable verbose output"); + + /* add command to the shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "generate a wrapper for a pre-configured fpga fabric"); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, + write_preconfigured_fabric_wrapper_template); + + /* add command dependency to the shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: write preconfigured testbench + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_preconfigured_testbench_command_template( + openfpga::Shell& shell, + const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds) { + Command shell_cmd("write_preconfigured_testbench"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId output_opt = shell_cmd.add_option( + "file", true, "Specify the output directory for HDL netlists"); + shell_cmd.set_option_short_name(output_opt, "f"); + shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + + /* add an option '--fabric_netlist_file_path'*/ + CommandOptionId fabric_netlist_opt = + shell_cmd.add_option("fabric_netlist_file_path", false, + "specify the file path to the fabric hdl netlist"); + shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING); + + /* Add an option '--pin_constraints_file in short '-pcf' */ + CommandOptionId pcf_opt = + shell_cmd.add_option("pin_constraints_file", false, + "Specify the file path to the pin constraints"); + shell_cmd.set_option_short_name(pcf_opt, "pcf"); + shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING); + + /* add an option '--bus_group_file in short '-bgf' */ + CommandOptionId bgf_opt = shell_cmd.add_option( + "bus_group_file", false, "specify the file path to the group pins to bus"); + shell_cmd.set_option_short_name(bgf_opt, "bgf"); + shell_cmd.set_option_require_value(bgf_opt, openfpga::OPT_STRING); + + /* Add an option '--reference_benchmark_file_path'*/ + CommandOptionId ref_bm_opt = shell_cmd.add_option( + "reference_benchmark_file_path", false, + "Specify the file path to the reference Verilog netlist. If specified, the " + "testbench will include self-checking codes"); + shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING); + + /* Add an option '--explicit_port_mapping' */ + shell_cmd.add_option("explicit_port_mapping", false, + "Use explicit port mapping in Verilog netlists"); + + /* Add an option '--default_net_type' */ + CommandOptionId default_net_type_opt = shell_cmd.add_option( + "default_net_type", false, + "Set the default net type for Verilog netlists. Default value is 'none'"); + shell_cmd.set_option_require_value(default_net_type_opt, + openfpga::OPT_STRING); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print a time stamp in the output files"); + + /* Add an option '--use_relative_path' */ + shell_cmd.add_option( + "use_relative_path", false, + "Force to use relative path in netlists when including other netlists"); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add command to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "generate testbenches for a preconfigured FPGA fabric"); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, + write_preconfigured_testbench_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: write simulation task info + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_simulation_task_info_command_template( + openfpga::Shell& shell, + const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds) { + Command shell_cmd("write_simulation_task_info"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId output_opt = shell_cmd.add_option( + "file", true, + "Specify the file path to output simulation-related information"); + shell_cmd.set_option_short_name(output_opt, "f"); + shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + + /* Add an option '--hdl_dir'*/ + CommandOptionId hdl_dir_opt = shell_cmd.add_option( + "hdl_dir", true, + "Specify the directory path where HDL netlists are created"); + shell_cmd.set_option_require_value(hdl_dir_opt, openfpga::OPT_STRING); + + /* Add an option '--reference_benchmark_file_path'*/ + CommandOptionId ref_bm_opt = shell_cmd.add_option( + "reference_benchmark_file_path", false, + "Specify the file path to the reference Verilog netlist. If specified, the " + "testbench will include self-checking codes"); + shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING); + + /* Add an option '--testbench_type'*/ + CommandOptionId tb_type_opt = shell_cmd.add_option( + "testbench_type", false, + "Specify the type of testbenches to be considered. Different testbenches " + "have different simulation parameters."); + shell_cmd.set_option_require_value(tb_type_opt, openfpga::OPT_STRING); + + /* Add an option '--time_unit' */ + CommandOptionId time_unit_opt = + shell_cmd.add_option("time_unit", false, + "Specify the time unit to be used in HDL simulation. " + "Acceptable is [a|f|p|n|u|m|k|M]s"); + shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add command to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "generate an interchangable simulation task configuration file"); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, write_simulation_task_info_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +template +void add_verilog_command_templates(openfpga::Shell& shell) { + /* Get the unique id of 'build_fabric' command which is to be used in creating + * the dependency graph */ + const ShellCommandId& build_fabric_cmd_id = + shell.command(std::string("build_fabric")); + + /* Add a new class of commands */ + ShellCommandClassId openfpga_verilog_cmd_class = + shell.add_command_class("FPGA-Verilog"); + + /******************************** + * Command 'write_fabric_verilog' + */ + /* The 'write_fabric_verilog' command should NOT be executed before + * 'build_fabric' */ + std::vector fabric_verilog_dependent_cmds; + fabric_verilog_dependent_cmds.push_back(build_fabric_cmd_id); + add_write_fabric_verilog_command_template(shell, openfpga_verilog_cmd_class, + fabric_verilog_dependent_cmds); + + /******************************** + * Command 'write_full_testbench' + */ + /* The command 'write_full_testbench' should NOT be executed before + * 'build_fabric' */ + std::vector full_testbench_dependent_cmds; + full_testbench_dependent_cmds.push_back(build_fabric_cmd_id); + add_write_full_testbench_command_template(shell, openfpga_verilog_cmd_class, + full_testbench_dependent_cmds); + + /******************************** + * Command 'write_preconfigured_fabric_wrapper' + */ + /* The command 'write_preconfigured_fabric_wrapper' should NOT be executed + * before 'build_fabric' */ + std::vector preconfig_wrapper_dependent_cmds; + preconfig_wrapper_dependent_cmds.push_back(build_fabric_cmd_id); + add_write_preconfigured_fabric_wrapper_command_template( + shell, openfpga_verilog_cmd_class, preconfig_wrapper_dependent_cmds); + + /******************************** + * Command 'write_preconfigured_testbench' + */ + /* The command 'write_preconfigured_testbench' should NOT be executed before + * 'build_fabric' */ + std::vector preconfig_testbench_dependent_cmds; + preconfig_testbench_dependent_cmds.push_back(build_fabric_cmd_id); + add_write_preconfigured_testbench_command_template( + shell, openfpga_verilog_cmd_class, preconfig_testbench_dependent_cmds); + + /******************************** + * Command 'write_simulation_task_info' + */ + /* The command 'write_simulation_task_info' should NOT be executed before + * 'build_fabric' */ + std::vector sim_task_info_dependent_cmds; + sim_task_info_dependent_cmds.push_back(build_fabric_cmd_id); + add_write_simulation_task_info_command_template( + shell, openfpga_verilog_cmd_class, sim_task_info_dependent_cmds); +} + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog_template.h similarity index 95% rename from openfpga/src/base/openfpga_verilog.cpp rename to openfpga/src/base/openfpga_verilog_template.h index 90bd48eb1..8454e2786 100644 --- a/openfpga/src/base/openfpga_verilog.cpp +++ b/openfpga/src/base/openfpga_verilog_template.h @@ -1,25 +1,18 @@ +#ifndef OPENFPGA_VERILOG_TEMPLATE_H +#define OPENFPGA_VERILOG_TEMPLATE_H + /******************************************************************** * This file includes functions to compress the hierachy of routing architecture *******************************************************************/ -/* Headers from vtrutil library */ #include "vtr_log.h" #include "vtr_time.h" - -/* Headers from openfpgashell library */ #include "command_exit_codes.h" - -/* Headers from openfpgautil library */ #include "openfpga_scale.h" -#include "openfpga_verilog.h" +#include "command.h" +#include "command_context.h" #include "verilog_api.h" - -/* Headers from pcf library */ #include "read_xml_pin_constraints.h" - -/* Headers from bgf library */ #include "read_xml_bus_group.h" - -/* Include global variables of VPR */ #include "globals.h" /* begin namespace openfpga */ @@ -28,7 +21,8 @@ namespace openfpga { /******************************************************************** * A wrapper function to call the fabric Verilog generator of FPGA-Verilog *******************************************************************/ -int write_fabric_verilog(OpenfpgaContext& openfpga_ctx, const Command& cmd, +template +int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { CommandOptionId opt_output_dir = cmd.option("file"); CommandOptionId opt_explicit_port_mapping = @@ -77,7 +71,8 @@ int write_fabric_verilog(OpenfpgaContext& openfpga_ctx, const Command& cmd, /******************************************************************** * A wrapper function to call the full testbench generator of FPGA-Verilog *******************************************************************/ -int write_full_testbench(const OpenfpgaContext& openfpga_ctx, +template +int write_full_testbench_template(const T& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { CommandOptionId opt_output_dir = cmd.option("file"); @@ -150,9 +145,10 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx, * A wrapper function to call the preconfigured wrapper generator of *FPGA-Verilog *******************************************************************/ -int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx, - const Command& cmd, - const CommandContext& cmd_context) { +template +int write_preconfigured_fabric_wrapper_template(const T& openfpga_ctx, + const Command& cmd, + const CommandContext& cmd_context) { CommandOptionId opt_output_dir = cmd.option("file"); CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path"); CommandOptionId opt_pcf = cmd.option("pin_constraints_file"); @@ -216,7 +212,8 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx, * A wrapper function to call the preconfigured testbench generator of *FPGA-Verilog *******************************************************************/ -int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx, +template +int write_preconfigured_testbench_template(const T& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { CommandOptionId opt_output_dir = cmd.option("file"); @@ -278,7 +275,8 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx, * A wrapper function to call the simulation task information generator of *FPGA-Verilog *******************************************************************/ -int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx, +template +int write_simulation_task_info_template(const T& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { CommandOptionId opt_file = cmd.option("file"); @@ -337,3 +335,5 @@ int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx, } } /* end namespace openfpga */ + +#endif