[engine] now consider vtr submodule when compilation, remove out-of-date directories
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@ -184,12 +184,9 @@ endif()
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# Sub-projects
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#
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#add_subdirectory(iverilog)
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add_subdirectory(libs)
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add_subdirectory(libopenfpga)
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#add_subdirectory(yosys)
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add_subdirectory(abc)
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add_subdirectory(ace2)
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add_subdirectory(vpr)
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add_subdirectory(verilog-to-routing)
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add_subdirectory(openfpga)
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# yosys compilation starts
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@ -267,37 +264,6 @@ endif()
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# Note that target_compile_options() *appends* to the current compilation options of
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# the specified target
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#Since ABC is an externally developed tool, we suppress all compiler warnings
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CHECK_CXX_COMPILER_FLAG("-w" CXX_COMPILER_SUPPORTS_-w)
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if(CXX_COMPILER_SUPPORTS_-w)
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target_compile_options(libabc PRIVATE "-w")
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target_compile_options(abc PRIVATE "-w")
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endif()
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#Some ABC headers generate warnings, treat them as system headers to suppress warnings
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get_property(ABC_INCLUDE_DIRS TARGET libabc PROPERTY INCLUDE_DIRECTORIES)
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target_include_directories(libabc SYSTEM INTERFACE ${ABC_INCLUDE_DIRS})
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# We use Yosys and abc Makefile now, TODO: create CMakeLists.txt as well
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set_target_properties(libabc abc
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PROPERTIES
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ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/abc"
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LIBRARY_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/abc"
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RUNTIME_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/abc")
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# Set output locations to be in the main source tree under the relevant folder
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set_target_properties(libace ace
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PROPERTIES
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ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/ace2"
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LIBRARY_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/ace2"
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RUNTIME_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/ace2")
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set_target_properties(libvpr vpr
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PROPERTIES
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ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr"
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LIBRARY_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr"
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RUNTIME_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr")
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set_target_properties(libopenfpga openfpga
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PROPERTIES
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ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/openfpga"
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