diff --git a/Dockerfile b/Dockerfile index 1a155fca4..22d150d40 100644 --- a/Dockerfile +++ b/Dockerfile @@ -7,7 +7,9 @@ RUN curl -fsSL https://code-server.dev/install.sh | sh RUN apt-get install -y nodejs RUN apt-get install tree RUN code-server --install-extension ms-python.python -RUN code-server --install-extension mechatroner +RUN code-server --install-extension mechatroner.rainbow-csv +RUN code-server --install-extension wavetrace.wavetrace +RUN code-server --install-extension dotjoshjohnson.xml RUN usermod -u 2000 openfpga_user RUN groupmod -g 2000 openfpga_user diff --git a/docs/source/conf.py b/docs/source/conf.py index 02a4256b8..821dcb4b2 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -185,7 +185,7 @@ texinfo_documents = [ ] -bibtex_bibfiles = ["z_reference.bib"] +bibtex_bibfiles = ["./appendix/z_reference.bib"] # -- Options for Epub output ------------------------------------------------- @@ -203,3 +203,22 @@ epub_title = project # A list of files that should not be packed into the epub file. epub_exclude_files = ['search.html'] + +# ======== +# Headings +# ======== +# +# Headings +# ======== +# +# Heading 3 +# --------- +# +# Heading 4 +# ^^^^^^^^^ +# +# Heading 5 +# ~~~~~~~~~ +# +# Heading 6 +# ********* diff --git a/docs/source/tutorials/getting_started/shell_shortcuts.rst b/docs/source/tutorials/getting_started/shell_shortcuts.rst index 0c32d3fa4..cb5d01bdc 100644 --- a/docs/source/tutorials/getting_started/shell_shortcuts.rst +++ b/docs/source/tutorials/getting_started/shell_shortcuts.rst @@ -1,17 +1,18 @@ -OpenFPGA shortcuts ------------------- +OpenFPGA Shell Commands +----------------------- -OpenFPGA provides `bash`/`zsh` shell-based shortcuts to perform all essential functions and navigate through the directories. Go to the OpenFPGA directory and source ``openfpga.sh`` +OpenFPGA provides `bash`/`zsh` shell-based shortcuts to perform all essential functions and navigate through the directories. Go to the OpenFPGA directory and source ``openfpga.sh``, .. code-block:: bash + export OPENFPGA_PATH= cd ${OPENFPGA_PATH} && source openfpga.sh .. note:: The OpenFPGA shortcut works with only a bash-like shell. e.g., `bash`/`zsh`/`fish,` etc. -Shortcut Commands -^^^^^^^^^^^^^^^^^ +Commands +^^^^^^^^ Once the ``openfpga.sh`` script is sourced, you can run any following commands directly in the terminal. @@ -38,13 +39,21 @@ Once the ``openfpga.sh`` script is sourced, you can run any following commands d for example ``create-task _my_task_copy basic_tests/generate_fabric`` create a copy of the ``basic_tests/generate_fabric`` task in the current directory with ``_my_task_copy`` name. -.. option:: run-modelsim +.. option:: goto_task + + This command navigate shell to specific run-directory of the given task. + For example `goto_task lab1 2` will change directory to `run002` runt directory of `lab2` + +.. option:: clear-task-run + + Clears all run diretories of the given task + +.. option:: run-modelsim This command runs the verification using ModelSim. The test benches are generated during the OpenFPGA run. **Note**: users need to have ``VSIM`` installed and configured - .. option:: run-regression-local This script runs the regression test locally using the current version of OpenFPGA. diff --git a/openfpga.sh b/openfpga.sh index 81a6279ad..787fe5c88 100755 --- a/openfpga.sh +++ b/openfpga.sh @@ -41,15 +41,15 @@ create-task () { return fi template="template_tasks/yosys_vpr_template" - if [ ${#2} -ge 1 ]; then + if [ ${#2} -ge 1 ]; then if [[ "$2" == "vpr_blif" ]]; then template="template_tasks/${2}_template/"; - elif [[ "$2" == "yosys_vpr" ]]; then template="template_tasks/${2}_template/"; - elif [[ "$2" == "vtr_benchmarks" ]]; then template="template_tasks/${2}_template/"; - else template="$2" + elif [[ "$2" == "yosys_vpr" ]]; then template="template_tasks/${2}_template/"; + elif [[ "$2" == "vtr_benchmarks" ]]; then template="template_tasks/${2}_template/"; + else template="$2" fi fi - if [ ! -f $OPENFPGA_PATH/openfpga_flow/tasks/${template}/config/task.conf ]; then - echo "Template project [${template}] does not exist" ; return; + if [ ! -f $OPENFPGA_PATH/openfpga_flow/tasks/${template}/config/task.conf ]; then + echo "Template project [${template}] does not exist" ; return; fi echo "Creating task $1" echo "Template project ${template}" @@ -57,6 +57,11 @@ create-task () { cp -r $OPENFPGA_PATH/openfpga_flow/tasks/${template}/* $1/ } +rerun-task () { + $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@" --remove_run_dir all + $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@" +} + run-task () { $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@" } @@ -66,7 +71,7 @@ clean-run () { } clear-task-run () { - $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@" --remove_run_dir all + $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@" --remove_run_dir all } run-modelsim () { diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 9fc356b49..a8f6c82aa 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -203,8 +203,9 @@ run-task basic_tests/io_constraints/empty_pcf $@ run-task basic_tests/io_constraints/pcf_ql_style $@ echo -e "Testing project templates"; -run-task template_tasks/vpr_blif_template $@ -run-task template_tasks/yosys_vpr_template $@ +run-task template_tasks/fabric_netlist_gen_template $@ +run-task template_tasks/fabric_verification_template $@ +run-task template_tasks/frac-lut-arch-explore_template $@ run-task template_tasks/vtr_benchmarks_template $@ echo -e "Testing create tsk from template and run task" diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/openfpga_arch.xml b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/arch/openfpga_arch.xml similarity index 92% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/openfpga_arch.xml rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/arch/openfpga_arch.xml index 0ff0edfd3..db45d6d42 100644 --- a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/openfpga_arch.xml +++ b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/arch/openfpga_arch.xml @@ -1,11 +1,3 @@ - @@ -157,21 +149,18 @@ - + + + + + + + + + - - - - - - - - - - - diff --git a/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/arch/vpr_arch.xml b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/arch/vpr_arch.xml new file mode 100644 index 000000000..c60b48336 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/arch/vpr_arch.xml @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/config/task.conf b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/config/task.conf similarity index 100% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/config/task.conf rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/config/task.conf diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/example_script.openfpga b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/example_script.openfpga similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/example_script.openfpga rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/example_script.openfpga diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.act b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2.act similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.act rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2.act diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.blif b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2.blif similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.blif rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.eblif b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2.eblif similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.eblif rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2.eblif diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.v b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2.v similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.v rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2.v diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2_verific.blif b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2_verific.blif similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2_verific.blif rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/and2/and2_verific.blif diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/blinking/blinking.v b/openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/blinking/blinking.v similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/blinking/blinking.v rename to openfpga_flow/tasks/template_tasks/fabric_netlist_gen_template/micro_benchmark/blinking/blinking.v diff --git a/openfpga_flow/tasks/template_tasks/fabric_verification_template/arch/openfpga_arch.xml b/openfpga_flow/tasks/template_tasks/fabric_verification_template/arch/openfpga_arch.xml new file mode 100644 index 000000000..0ffc95e49 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/fabric_verification_template/arch/openfpga_arch.xml @@ -0,0 +1,192 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/template_tasks/fabric_verification_template/arch/vpr_arch.xml b/openfpga_flow/tasks/template_tasks/fabric_verification_template/arch/vpr_arch.xml new file mode 100644 index 000000000..0fc9d794c --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/fabric_verification_template/arch/vpr_arch.xml @@ -0,0 +1,191 @@ + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/config/task.conf b/openfpga_flow/tasks/template_tasks/fabric_verification_template/config/task.conf similarity index 68% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/config/task.conf rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/config/task.conf index f3a65f25d..22f0358a3 100644 --- a/openfpga_flow/tasks/template_tasks/vpr_blif_template/config/task.conf +++ b/openfpga_flow/tasks/template_tasks/fabric_verification_template/config/task.conf @@ -13,25 +13,29 @@ power_analysis = false spice_output=false verilog_output=true timeout_each_job = 20*60 -# fpga_flow= vpr_blif If input in in .blif format -# fpga_flow= yosys_vpr If input in in .v format -fpga_flow=vpr_blif +fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:TASK_DIR}/example_script.openfpga openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml [BENCHMARKS] -bench0=${PATH:TASK_DIR}/micro_benchmark/and2/and2.blif +bench0=${PATH:TASK_DIR}/micro_benchmark/and2/and2.v +bench1=${PATH:TASK_DIR}/micro_benchmark/mult8/mult8.v [SYNTHESIS_PARAM] +# Yosys script parameters +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys + bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and2/and2.v +bench1_top = mult8 +bench1_verilog = ${PATH:TASK_DIR}/micro_benchmark/mult8/mult8.v [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/example_script.openfpga b/openfpga_flow/tasks/template_tasks/fabric_verification_template/example_script.openfpga similarity index 85% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/example_script.openfpga rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/example_script.openfpga index a31f81948..3fac06b3f 100644 --- a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/example_script.openfpga +++ b/openfpga_flow/tasks/template_tasks/fabric_verification_template/example_script.openfpga @@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options -link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges +link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml @@ -44,6 +44,7 @@ build_fabric_bitstream --verbose # Write fabric-dependent bitstream write_fabric_bitstream --file fabric_bitstream.bit --format plain_text +write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist @@ -55,19 +56,9 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping -write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file ./SDC - -# Write SDC to disable timing for configure ports -write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file ./SDC_analysis +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Finish and exit OpenFPGA exit diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.act b/openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2.act similarity index 100% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.act rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2.act diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.blif b/openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2.blif similarity index 100% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.blif rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.eblif b/openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2.eblif similarity index 100% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.eblif rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2.eblif diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.v b/openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2.v similarity index 100% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.v rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2.v diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif b/openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif similarity index 100% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2_verific.blif b/openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2_verific.blif similarity index 100% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2_verific.blif rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/and2/and2_verific.blif diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/blinking/blinking.v b/openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/blinking/blinking.v similarity index 100% rename from openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/blinking/blinking.v rename to openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/blinking/blinking.v diff --git a/openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/mult8/mult8.v b/openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/mult8/mult8.v new file mode 100644 index 000000000..1ad0c1f19 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/fabric_verification_template/micro_benchmark/mult8/mult8.v @@ -0,0 +1,22 @@ +//------------------------------------------------------- +// Functionality: A 8-bit combinational multiply circuit +//------------------------------------------------------- + +module mult8(a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7, + b_0, b_1, b_2, b_3, b_4, b_5, b_6, b_7, + out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7, + out_8, out_9, out_10, out_11, out_12, out_13, out_14, out_15); +input a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7; +input b_0, b_1, b_2, b_3, b_4, b_5, b_6, b_7; +output out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7; +output out_8, out_9, out_10, out_11, out_12, out_13, out_14, out_15; + + assign a = {a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7}; + assign b = {b_0, b_1, b_2, b_3, b_4, b_5, b_6, b_7}; + assign out = {out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7, out_8, out_9, out_10, out_11, out_12, out_13, out_14, out_15}; + + assign out = a*b; + +endmodule + + diff --git a/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/config/task.conf b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/config/task.conf new file mode 100644 index 000000000..0d4e82645 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/config/task.conf @@ -0,0 +1,49 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:TASK_DIR}/vtr_benchmark_template_script.openfpga +openfpga_arch_file=${PATH:TASK_DIR}/openfpga_arch.xml +vpr_route_chan_width=300 + +[ARCHITECTURES] +arch0=${PATH:TASK_DIR}/k6_N10_tileable.xml +arch1=${PATH:TASK_DIR}/k6_frac_N10_tileable.xml + +[BENCHMARKS] +bench1=${PATH:BENCH_PATH}/vtr_benchmark/ch_intrinsics.v +bench2=${PATH:BENCH_PATH}/vtr_benchmark/diffeq1.v +bench3=${PATH:BENCH_PATH}/vtr_benchmark/diffeq2.v +bench4=${PATH:BENCH_PATH}/vtr_benchmark/sha.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys + +# Benchmark top_module name +bench1_top = memset +bench2_top = diffeq_paj_convert +bench3_top = diffeq_f_systemC +bench4_top = sha1 + +[SCRIPT_PARAM_] +# + +[DEFAULT_PARSE_RESULT_VPR] +01_lut6_use = "lut6 : ([0-9]+)", int +02_lut5_use = "lut5 : ([0-9]+)", int \ No newline at end of file diff --git a/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_N10_tileable.xml b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_N10_tileable.xml new file mode 100644 index 000000000..2b8b06cb3 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_N10_tileable.xml @@ -0,0 +1,198 @@ + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + clb.clk + clb.cin + clb.O[9:0] clb.I[19:0] + clb.cout clb.O[19:10] clb.I[39:20] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_frac_N10_tileable.xml b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_frac_N10_tileable.xml new file mode 100644 index 000000000..27084cccf --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_frac_N10_tileable.xml @@ -0,0 +1,245 @@ + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + clb.clk + clb.cin + clb.O[9:0] clb.I[19:0] + clb.cout clb.O[19:10] clb.I[39:20] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/openfpga_arch.xml b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/openfpga_arch.xml similarity index 100% rename from openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/openfpga_arch.xml rename to openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/openfpga_arch.xml diff --git a/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/vtr_benchmark_template_script.openfpga b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/vtr_benchmark_template_script.openfpga new file mode 100644 index 000000000..ebe778df6 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/vtr_benchmark_template_script.openfpga @@ -0,0 +1,7 @@ +# Execute VPR for architecture exploration + +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} \ + --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} \ + --constant_net_method route + +exit \ No newline at end of file diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/vpr_arch.xml b/openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/vpr_arch.xml deleted file mode 100644 index 5af28d265..000000000 --- a/openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/vpr_arch.xml +++ /dev/null @@ -1,287 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/vpr_arch.xml b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/vpr_arch.xml deleted file mode 100644 index 6d875aa50..000000000 --- a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/vpr_arch.xml +++ /dev/null @@ -1,199 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file