[core] syntax

libs/libarchopenfpga/src/bitstream_setting.cpp

@@ -24,6 +24,13 @@ BitstreamSetting::default_mode_settings() const {
                          default_mode_setting_ids_.end());
 }
 
+BitstreamSetting::bitstream_clock_routing_setting_range
+BitstreamSetting::clock_routing_settings() const {
+  return vtr::make_range(clock_routing_setting_ids_.begin(),
+                         clock_routing_setting_ids_.end());
+}
+
+
 BitstreamSetting::bitstream_interconnect_setting_range
 BitstreamSetting::interconnect_settings() const {
   return vtr::make_range(interconnect_setting_ids_.begin(),

libs/libarchopenfpga/src/bitstream_setting.h

@@ -11,6 +11,7 @@
 #include "bitstream_setting_fwd.h"
 #include "vtr_geometry.h"
 #include "vtr_vector.h"
+#include "openfpga_port.h"
 
 /* namespace openfpga begins */
 namespace openfpga {
@@ -177,7 +178,6 @@ class BitstreamSetting {
     const std::string& default_path);
 
   /* Non-fabric bitstream setting */
-  std::vector<NonFabricBitstreamSetting> non_fabric() const;
   void add_non_fabric(const std::string& name, const std::string& file);
   void add_non_fabric_pb(const std::string& pb, const std::string& content);
 

libs/libarchopenfpga/src/read_xml_bitstream_setting.cpp

@@ -14,6 +14,7 @@
 
 /* Headers from openfpga util library */
 #include "openfpga_pb_parser.h"
+#include "openfpga_port_parser.h"
 
 /* Headers from libarchfpga */
 #include "arch_error.h"
@@ -95,7 +96,7 @@ static void read_xml_bitstream_clock_routing_setting(
     get_attribute(xml_clk_routing, XML_CLOCK_ROUTING_ATTRIBUTE_PIN, loc_data).as_string();
   /* Parse the port and apply sanity checks */
   openfpga::PortParser port_parser(pin_attr);
-  BasicPort pin = port_parser.port();
+  openfpga::BasicPort pin = port_parser.port();
   if (!pin.is_valid()) {
     archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_clk_routing),
                    "Invalid pin '%s' which should be valid port. For example, clk[1:1]\n", pin_attr.c_str());
@@ -198,7 +199,11 @@ openfpga::BitstreamSetting read_xml_bitstream_setting(
       }
     }
     if (!valid_node) {
-      bad_tag(xml_child, loc_data, Node, XML_VALID_NODE_NAMES);
+      std::vector<std::string> vec_valid_node_names;
+      for (auto valid_node_name : XML_VALID_NODE_NAMES) {
+        vec_valid_node_names.push_back(std::string(valid_node_name));
+      }
+      bad_tag(xml_child, loc_data, Node, vec_valid_node_names);
     }
 
     if (xml_child.name() == std::string(XML_PB_TYPE_NODE_NAME)) {

libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp

@@ -6,7 +6,7 @@
 # Input file: /home/xifan/github/OpenFPGA/libs/libopenfpgacapnproto/gen/unique_blocks.xsd
 # md5sum of input file: 1db9d740309076fa51f61413bae1e072
 
-@0xe572df7b6c5621b7;
+@0xfa145057f56804f2;
 using Cxx = import "/capnp/c++.capnp";
 $Cxx.namespace("ucap");
 

openfpga/src/annotation/annotate_bitstream_setting.cpp

@@ -247,11 +247,11 @@ static int annotate_bitstream_clock_routing_setting(
       return CMD_EXEC_FATAL_ERROR;
     }
     if (!tree_port.mergeable(wanted_pin)) {
-      VTR_LOG_ERROR("Invalid clock pin definition '%s' from bitstream setting for clock network name '%s', which does not match the name of pin '%s' in the clock network description!\n", wanted_pin.to_verilog_string().c_str(), ntwk_name.c_str(), tree_port.to_verilog_string.c_str());
+      VTR_LOG_ERROR("Invalid clock pin definition '%s' from bitstream setting for clock network name '%s', which does not match the name of pin '%s' in the clock network description!\n", wanted_pin.to_verilog_string().c_str(), ntwk_name.c_str(), tree_port.to_verilog_string().c_str());
       return CMD_EXEC_FATAL_ERROR;
     }
-    if (!tree_port.contained(wanted_pin) {
+    if (!tree_port.contained(wanted_pin)) {
-      VTR_LOG_ERROR("Invalid clock pin definition '%s' from bitstream setting for clock network name '%s', which is out of the pin '%s' in the clock network description!\n", wanted_pin.to_verilog_string().c_str(), ntwk_name.c_str(), tree_port.to_verilog_string.c_str());
+      VTR_LOG_ERROR("Invalid clock pin definition '%s' from bitstream setting for clock network name '%s', which is out of the pin '%s' in the clock network description!\n", wanted_pin.to_verilog_string().c_str(), ntwk_name.c_str(), tree_port.to_verilog_string().c_str());
       return CMD_EXEC_FATAL_ERROR;
     }
     /* All sanity check passed. Record the bitstream requirements */
@@ -392,6 +392,7 @@ static int annotate_bitstream_interconnect_setting(
 int annotate_bitstream_setting(
   const BitstreamSetting& bitstream_setting,
   const DeviceContext& vpr_device_ctx,
+  const ClockNetwork& clk_ntwk,
   VprDeviceAnnotation& vpr_device_annotation,
   VprBitstreamAnnotation& vpr_bitstream_annotation) {
   int status = CMD_EXEC_SUCCESS;
@@ -402,7 +403,7 @@ int annotate_bitstream_setting(
     return status;
   }
 
-  status = annotate_bitstream_clock_routing_setting(bitstream_setting, vpr_device_ctx,
+  status = annotate_bitstream_clock_routing_setting(bitstream_setting, clk_ntwk,
                                                     vpr_bitstream_annotation);
   if (status == CMD_EXEC_FATAL_ERROR) {
     return status;

openfpga/src/annotation/annotate_bitstream_setting.h

@@ -6,6 +6,7 @@
  *******************************************************************/
 #include "openfpga_context.h"
 #include "vpr_context.h"
+#include "clock_network.h"
 
 /********************************************************************
  * Function declaration
@@ -17,6 +18,7 @@ namespace openfpga {
 int annotate_bitstream_setting(
   const BitstreamSetting& bitstream_setting,
   const DeviceContext& vpr_device_ctx,
+  const ClockNetwork& clk_ntwk,
   VprDeviceAnnotation& vpr_device_annotation,
   VprBitstreamAnnotation& vpr_bitstream_annotation);
 

openfpga/src/base/openfpga_link_arch_template.h

@@ -177,6 +177,7 @@ int link_arch_template(T& openfpga_ctx, const Command& cmd,
   if (CMD_EXEC_FATAL_ERROR ==
       annotate_bitstream_setting(
         openfpga_ctx.bitstream_setting(), g_vpr_ctx.device(),
+        openfpga_ctx.clock_arch(),
         openfpga_ctx.mutable_vpr_device_annotation(),
         openfpga_ctx.mutable_vpr_bitstream_annotation())) {
     return CMD_EXEC_FATAL_ERROR;
@@ -233,6 +234,7 @@ int route_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd,
     openfpga_ctx.mutable_vpr_routing_annotation(),
     openfpga_ctx.vpr_clustering_annotation(), g_vpr_ctx.device(),
     g_vpr_ctx.clustering().clb_nlist, g_vpr_ctx.placement(),
+    openfpga_ctx.vpr_bitstream_annotation(),
     openfpga_ctx.clock_rr_lookup(), openfpga_ctx.clock_arch(), pin_constraints,
     cmd_context.option_enable(cmd, opt_disable_unused_trees),
     cmd_context.option_enable(cmd, opt_disable_unused_spines),