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[engine] fixing bugs on using subtile index

This commit is contained in:
tangxifan 2022-08-23 11:00:23 -07:00
parent fa790d50d4
commit 10cefebca8
1 changed files with 3 additions and 2 deletions
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5
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
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@ -708,8 +708,9 @@ void build_physical_block_bitstream(BitstreamManager& bitstream_manager,
* it as a mode under a <pb_type> * it as a mode under a <pb_type>
*/ */
for (size_t z = 0; z < place_annotation.grid_blocks(grid_coord).size(); ++z) { for (size_t z = 0; z < place_annotation.grid_blocks(grid_coord).size(); ++z) {
VTR_ASSERT(1 == grid_type->sub_tiles[z].equivalent_sites.size()); int sub_tile_index = device_annotation.physical_tile_z_to_subtile_index(grid_type, z);
for (t_logical_block_type_ptr lb_type : grid_type->sub_tiles[z].equivalent_sites) { VTR_ASSERT(1 == grid_type->sub_tiles[sub_tile_index].equivalent_sites.size());
for (t_logical_block_type_ptr lb_type : grid_type->sub_tiles[sub_tile_index].equivalent_sites) {
/* Bypass empty pb_graph */ /* Bypass empty pb_graph */
if (nullptr == lb_type->pb_graph_head) { if (nullptr == lb_type->pb_graph_head) {
continue; continue;