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bring single mode test case online with bug fixing

This commit is contained in:
tangxifan 2019-10-28 17:04:10 -06:00
parent 5cb3717433
commit 10491c4291
3 changed files with 30 additions and 13 deletions
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2
.travis/script.sh
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@ -18,5 +18,5 @@ end_section "OpenFPGA.build"
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
cd - cd -
python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing explicit_verilog --maxthreads 3 python3 openfpga_flow/scripts/run_fpga_task.py single_mode blif_vpr_flow tileable_routing explicit_verilog --maxthreads 3
end_section "OpenFPGA.TaskTun" end_section "OpenFPGA.TaskTun"

4
openfpga_flow/tasks/single_mode/config/task.conf
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@ -53,6 +53,6 @@ vpr_fpga_verilog_print_user_defined_template=
vpr_fpga_verilog_print_report_timing_tcl= vpr_fpga_verilog_print_report_timing_tcl=
vpr_fpga_verilog_print_sdc_pnr= vpr_fpga_verilog_print_sdc_pnr=
vpr_fpga_verilog_print_sdc_analysis= vpr_fpga_verilog_print_sdc_analysis=
#vpr_fpga_verilog_explicit_mapping= vpr_fpga_verilog_explicit_mapping=
#vpr_fpga_x2p_compact_routing_hierarchy= vpr_fpga_x2p_compact_routing_hierarchy=
end_flow_with_test= end_flow_with_test=

37
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp
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@ -426,6 +426,20 @@ void print_verilog_top_random_stimuli(std::fstream& fp,
print_verilog_comment(fp, std::string("----- Initialization -------")); print_verilog_comment(fp, std::string("----- Initialization -------"));
fp << "\tinitial begin" << std::endl; fp << "\tinitial begin" << std::endl;
/* Create clock stimuli */
BasicPort clock_port = generate_verilog_top_clock_port(clock_port_names);
fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << " <= 1'b0;" << std::endl;
fp << "\t\twhile(1) begin" << std::endl;
fp << "\t\t\t#" << std::setprecision(2) << ((0.5/simulation_parameters.stimulate_params.op_clock_freq)/verilog_sim_timescale) << std::endl;
fp << "\t\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port);
fp << " <= !";
fp << generate_verilog_port(VERILOG_PORT_CONKT, clock_port);
fp << ";" << std::endl;
fp << "\t\tend" << std::endl;
/* Add an empty line as splitter */
fp << std::endl;
for (const t_logical_block& lb : L_logical_blocks) { for (const t_logical_block& lb : L_logical_blocks) {
/* Bypass non-I/O logical blocks ! */ /* Bypass non-I/O logical blocks ! */
if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) {
@ -441,17 +455,20 @@ void print_verilog_top_random_stimuli(std::fstream& fp,
/* Add an empty line as splitter */ /* Add an empty line as splitter */
fp << std::endl; fp << std::endl;
/* Creae clock stimuli */ /* Set 0 to registers for checking flags */
BasicPort clock_port = generate_verilog_top_clock_port(clock_port_names); for (const t_logical_block& lb : L_logical_blocks) {
fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << " <= 1'b0;" << std::endl; /* We care only those logic blocks which are input I/Os */
fp << "\t\twhile(1) begin" << std::endl; if (VPACK_OUTPAD != lb.type) {
fp << "\t\t\t#" << std::setprecision(2) << ((0.5/simulation_parameters.stimulate_params.op_clock_freq)/verilog_sim_timescale) << std::endl; continue;
fp << "\t\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port); }
fp << " <= !";
fp << generate_verilog_port(VERILOG_PORT_CONKT, clock_port); /* Each logical block assumes a single-width port */
fp << ";" << std::endl; BasicPort output_port(std::string(std::string(lb.name) + std::string(CHECKFLAG_PORT_POSTFIX)), 1);
fp << "\t\tend" << std::endl; fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << " <= 1'b0;" << std::endl;
}
fp << "\tend" << std::endl; fp << "\tend" << std::endl;
/* Finish initialization */
/* Add an empty line as splitter */ /* Add an empty line as splitter */
fp << std::endl; fp << std::endl;