From 10491c429145ee5391e66ad5aca3301066ab7e46 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 28 Oct 2019 17:04:10 -0600
Subject: [PATCH] bring single mode test case online with bug fixing

---
 .travis/script.sh                             |  2 +-
 .../tasks/single_mode/config/task.conf        |  4 +-
 .../verilog_formal_random_top_testbench.cpp   | 37 ++++++++++++++-----
 3 files changed, 30 insertions(+), 13 deletions(-)

diff --git a/.travis/script.sh b/.travis/script.sh
index 73e2a1ed2..599c35adf 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -18,5 +18,5 @@ end_section "OpenFPGA.build"
 
 start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
 cd -
-python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing explicit_verilog --maxthreads 3
+python3 openfpga_flow/scripts/run_fpga_task.py single_mode blif_vpr_flow tileable_routing explicit_verilog --maxthreads 3
 end_section "OpenFPGA.TaskTun"
diff --git a/openfpga_flow/tasks/single_mode/config/task.conf b/openfpga_flow/tasks/single_mode/config/task.conf
index f7086ab77..4d721002b 100644
--- a/openfpga_flow/tasks/single_mode/config/task.conf
+++ b/openfpga_flow/tasks/single_mode/config/task.conf
@@ -53,6 +53,6 @@ vpr_fpga_verilog_print_user_defined_template=
 vpr_fpga_verilog_print_report_timing_tcl=
 vpr_fpga_verilog_print_sdc_pnr=
 vpr_fpga_verilog_print_sdc_analysis=
-#vpr_fpga_verilog_explicit_mapping=
-#vpr_fpga_x2p_compact_routing_hierarchy=
+vpr_fpga_verilog_explicit_mapping=
+vpr_fpga_x2p_compact_routing_hierarchy=
 end_flow_with_test=
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp
index 6ba4c534c..8ac025eff 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp
@@ -426,6 +426,20 @@ void print_verilog_top_random_stimuli(std::fstream& fp,
   print_verilog_comment(fp, std::string("----- Initialization -------"));
 
   fp << "\tinitial begin" << std::endl;
+  /* Create clock stimuli */
+  BasicPort clock_port = generate_verilog_top_clock_port(clock_port_names);
+  fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << " <= 1'b0;" << std::endl;
+  fp << "\t\twhile(1) begin" << std::endl;
+  fp << "\t\t\t#" << std::setprecision(2) << ((0.5/simulation_parameters.stimulate_params.op_clock_freq)/verilog_sim_timescale) << std::endl;
+  fp << "\t\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port);
+  fp << " <= !";
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, clock_port);
+  fp << ";" << std::endl;
+  fp << "\t\tend" << std::endl;
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+
   for (const t_logical_block& lb : L_logical_blocks) {
     /* Bypass non-I/O logical blocks ! */
     if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) {
@@ -441,17 +455,20 @@ void print_verilog_top_random_stimuli(std::fstream& fp,
   /* Add an empty line as splitter */
   fp << std::endl;
   
-  /* Creae clock stimuli */
-  BasicPort clock_port = generate_verilog_top_clock_port(clock_port_names);
-  fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << " <= 1'b0;" << std::endl;
-  fp << "\t\twhile(1) begin" << std::endl;
-  fp << "\t\t\t#" << std::setprecision(2) << ((0.5/simulation_parameters.stimulate_params.op_clock_freq)/verilog_sim_timescale) << std::endl;
-  fp << "\t\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port);
-  fp << " <= !";
-  fp << generate_verilog_port(VERILOG_PORT_CONKT, clock_port);
-  fp << ";" << std::endl;
-  fp << "\t\tend" << std::endl;
+  /* Set 0 to registers for checking flags */
+  for (const t_logical_block& lb : L_logical_blocks) {
+    /* We care only those logic blocks which are input I/Os */
+    if (VPACK_OUTPAD != lb.type) { 
+      continue;
+    }
+
+    /* Each logical block assumes a single-width port */
+    BasicPort output_port(std::string(std::string(lb.name) + std::string(CHECKFLAG_PORT_POSTFIX)), 1); 
+    fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << " <= 1'b0;" << std::endl;
+  }
+
   fp << "\tend" << std::endl;
+  /* Finish initialization */
 
   /* Add an empty line as splitter */
   fp << std::endl;