[Doc] Update documentation on the minor changes on fabric bitstream file format

docs/source/manual/file_formats/fabric_bitstream.rst

@@ -63,7 +63,14 @@ The information depends on the type of configuration procotol.
 
 .. option:: frame_based 
 
-  Multiple lines will be included, each of which is organized as <address><space><bits>.
+  Multiple lines will be included, each of which is organized as ``<address><data_input_bits>``.
+  The size of address line and data input bits are shown as a comment in the bitstream file, which eases the development of bitstream downloader.
+  For example 
+  
+  .. code-block:: verilog
+
+    // Bitstream width (LSB -> MSB): <address 14 bits><data input 1 bits>
+
   Note that the address may include don't care bit which is denoted as ``x``.
 
   .. note:: OpenFPGA automatically convert don't care bit to logic ``0`` when generating testbenches.