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[Arch] Patch architecture using 16kbit dual port RAM

This commit is contained in:
tangxifan 2021-04-27 19:54:34 -06:00
parent 1d498bb296
commit 0f8aaae2bc
4 changed files with 156 additions and 129 deletions
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20
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
View File

@ -194,17 +194,17 @@
<port type="output" prefix="sumout" lib_name="SUM" size="1"/> <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
<port type="output" prefix="cout" lib_name="CO" size="1"/> <port type="output" prefix="cout" lib_name="CO" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="dpram_512x32" prefix="dpram_512x32" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dpram16k.v"> <circuit_model type="hard_logic" name="dpram_2048x8" prefix="dpram_2048x8" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dpram_2048x8.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="waddr" size="10"/> <port type="input" prefix="waddr" size="12"/>
<port type="input" prefix="raddr" size="10"/> <port type="input" prefix="raddr" size="12"/>
<port type="input" prefix="d_in" size="32"/> <port type="input" prefix="data_in" size="8"/>
<port type="input" prefix="wen" size="1"/> <port type="input" prefix="wen" size="1"/>
<port type="input" prefix="ren" size="1"/> <port type="input" prefix="ren" size="1"/>
<port type="output" prefix="d_out" size="32"/> <port type="output" prefix="data_out" size="8"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/> <port type="clock" prefix="clk" size="1"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
@ -222,6 +222,12 @@
<direct_connection> <direct_connection>
<direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/> <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
</direct_connection> </direct_connection>
<tile_annotations>
<global_port name="clk" is_clock="true" default_val="0">
<tile name="clb" port="clk"/>
<tile name="memory" port="clk"/>
</global_port>
</tile_annotations>
<pb_type_annotations> <pb_type_annotations>
<!-- physical pb_type binding in complex block IO --> <!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/> <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
@ -267,7 +273,7 @@
<!-- physical pb_type binding in complex block memory --> <!-- physical pb_type binding in complex block memory -->
<pb_type name="memory[mem_512x32_dp].mem_512x32_dp" circuit_model_name="dpram_512x32"/> <pb_type name="memory[mem_2048x8_dp].mem_2048x8_dp" circuit_model_name="dpram_2048x8"/>
<!-- END physical pb_type binding in complex block memory --> <!-- END physical pb_type binding in complex block memory -->
</pb_type_annotations> </pb_type_annotations>
</openfpga_architecture> </openfpga_architecture>

86
openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
View File

@ -118,14 +118,14 @@
<port name="lut6_out"/> <port name="lut6_out"/>
</output_ports> </output_ports>
</model> </model>
<model name="dual_port_ram"> <model name="dpram_2048x8">
<input_ports> <input_ports>
<!-- write address lines --> <!-- write address lines -->
<port name="waddr" clock="clk"/> <port name="waddr" clock="clk"/>
<!-- read address lines --> <!-- read address lines -->
<port name="raddr" clock="clk"/> <port name="raddr" clock="clk"/>
<!-- data lines can be broken down into smaller bit widths minimum size 1 --> <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
<port name="d_in" clock="clk"/> <port name="data_in" clock="clk"/>
<!-- write enable --> <!-- write enable -->
<port name="wen" clock="clk"/> <port name="wen" clock="clk"/>
<!-- read enable --> <!-- read enable -->
@ -135,7 +135,7 @@
</input_ports> </input_ports>
<output_ports> <output_ports>
<!-- output can be broken down into smaller bit widths minimum size 1 --> <!-- output can be broken down into smaller bit widths minimum size 1 -->
<port name="d_out" clock="clk"/> <port name="data_out" clock="clk"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
@ -180,15 +180,21 @@
<equivalent_sites> <equivalent_sites>
<site pb_type="memory"/> <site pb_type="memory"/>
</equivalent_sites> </equivalent_sites>
<input name="waddr" num_pins="10"/> <input name="waddr" num_pins="12"/>
<input name="raddr" num_pins="10"/> <input name="raddr" num_pins="12"/>
<input name="d_in" num_pins="32"/> <input name="data_in" num_pins="8"/>
<input name="wen" num_pins="1"/> <input name="wen" num_pins="1"/>
<input name="ren" num_pins="1"/> <input name="ren" num_pins="1"/>
<output name="d_out" num_pins="32"/> <output name="data_out" num_pins="8"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/> <pinlocations pattern="custom">
<loc side="left" yoffset="0">memory.clk</loc>
<loc side="top" yoffset="1"></loc>
<loc side="right" yoffset="0">memory.wen memory.waddr[0:3] memory.raddr[0:3] memory.data_in[0:2] memory.data_out[0:2]</loc>
<loc side="right" yoffset="1">memory.ren memory.waddr[4:7] memory.raddr[4:7] memory.data_in[3:5] memory.data_out[3:5]</loc>
<loc side="bottom" yoffset="0">memory.waddr[8:11] memory.raddr[8:11] memory.data_in[6:7] memory.data_out[6:7]</loc>
</pinlocations>
</tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
@ -682,57 +688,57 @@
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
<!-- Define single-mode dual-port memory begin --> <!-- Define single-mode dual-port memory begin -->
<pb_type name="memory"> <pb_type name="memory">
<input name="waddr" num_pins="10"/> <input name="waddr" num_pins="12"/>
<input name="raddr" num_pins="10"/> <input name="raddr" num_pins="12"/>
<input name="d_in" num_pins="32"/> <input name="data_in" num_pins="8"/>
<input name="wen" num_pins="1"/> <input name="wen" num_pins="1"/>
<input name="ren" num_pins="1"/> <input name="ren" num_pins="1"/>
<output name="d_out" num_pins="32"/> <output name="data_out" num_pins="8"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Specify the 512x32=16Kbit memory block <!-- Specify the 2048x8=16Kbit memory block
Note: the delay numbers are extracted from VPR flagship XML without modification Note: the delay numbers are extracted from VPR flagship XML without modification
Should align to the process technology we using to create the 16K dual-port RAM Should align to the process technology we using to create the 16K dual-port RAM
--> -->
<mode name="mem_512x32_dp"> <mode name="mem_2048x8_dp">
<pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> <pb_type name="mem_2048x8_dp" blif_model=".subckt dpram_2048x8" num_pb="1">
<input name="waddr" num_pins="10" port_class="address"/> <input name="waddr" num_pins="12" port_class="address1"/>
<input name="raddr" num_pins="10" port_class="address"/> <input name="raddr" num_pins="12" port_class="address2"/>
<input name="d_in" num_pins="32" port_class="data_in"/> <input name="data_in" num_pins="8" port_class="data_in1"/>
<input name="wen" num_pins="1" port_class="write_en"/> <input name="wen" num_pins="1" port_class="write_en1"/>
<input name="ren" num_pins="1" port_class="write_en"/> <input name="ren" num_pins="1" port_class="write_en2"/>
<output name="d_out" num_pins="32" port_class="data_out"/> <output name="data_out" num_pins="8" port_class="data_out1"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/> <T_setup value="509e-12" port="mem_2048x8_dp.waddr" clock="clk"/>
<T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/> <T_setup value="509e-12" port="mem_2048x8_dp.raddr" clock="clk"/>
<T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/> <T_setup value="509e-12" port="mem_2048x8_dp.data_in" clock="clk"/>
<T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/> <T_setup value="509e-12" port="mem_2048x8_dp.wen" clock="clk"/>
<T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/> <T_setup value="509e-12" port="mem_2048x8_dp.ren" clock="clk"/>
<T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/> <T_clock_to_Q max="1.234e-9" port="mem_2048x8_dp.data_out" clock="clk"/>
<power method="pin-toggle"> <power method="pin-toggle">
<port name="clk" energy_per_toggle="17.9e-12"/> <port name="clk" energy_per_toggle="17.9e-12"/>
<static_power power_per_instance="0.0"/> <static_power power_per_instance="0.0"/>
</power> </power>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr"> <direct name="waddress" input="memory.waddr" output="mem_2048x8_dp.waddr">
<delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/> <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_2048x8_dp.waddr"/>
</direct> </direct>
<direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr"> <direct name="raddress" input="memory.raddr" output="mem_2048x8_dp.raddr">
<delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/> <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_2048x8_dp.raddr"/>
</direct> </direct>
<direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in"> <direct name="data_input" input="memory.data_in" output="mem_2048x8_dp.data_in">
<delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/> <delay_constant max="132e-12" in_port="memory.data_in" out_port="mem_2048x8_dp.data_in"/>
</direct> </direct>
<direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen"> <direct name="writeen" input="memory.wen" output="mem_2048x8_dp.wen">
<delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/> <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_2048x8_dp.wen"/>
</direct> </direct>
<direct name="readen" input="memory.ren" output="mem_512x32_dp.ren"> <direct name="readen" input="memory.ren" output="mem_2048x8_dp.ren">
<delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/> <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_2048x8_dp.ren"/>
</direct> </direct>
<direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out"> <direct name="dataout" input="mem_2048x8_dp.data_out" output="memory.data_out">
<delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/> <delay_constant max="40e-12" in_port="mem_2048x8_dp.data_out" out_port="memory.data_out"/>
</direct> </direct>
<direct name="clk" input="memory.clk" output="mem_512x32_dp.clk"> <direct name="clk" input="memory.clk" output="mem_2048x8_dp.clk">
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>

86
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
View File

@ -118,14 +118,14 @@
<port name="lut6_out"/> <port name="lut6_out"/>
</output_ports> </output_ports>
</model> </model>
<model name="dual_port_ram"> <model name="dpram_2048x8">
<input_ports> <input_ports>
<!-- write address lines --> <!-- write address lines -->
<port name="waddr" clock="clk"/> <port name="waddr" clock="clk"/>
<!-- read address lines --> <!-- read address lines -->
<port name="raddr" clock="clk"/> <port name="raddr" clock="clk"/>
<!-- data lines can be broken down into smaller bit widths minimum size 1 --> <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
<port name="d_in" clock="clk"/> <port name="data_in" clock="clk"/>
<!-- write enable --> <!-- write enable -->
<port name="wen" clock="clk"/> <port name="wen" clock="clk"/>
<!-- read enable --> <!-- read enable -->
@ -135,7 +135,7 @@
</input_ports> </input_ports>
<output_ports> <output_ports>
<!-- output can be broken down into smaller bit widths minimum size 1 --> <!-- output can be broken down into smaller bit widths minimum size 1 -->
<port name="d_out" clock="clk"/> <port name="data_out" clock="clk"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
@ -180,15 +180,21 @@
<equivalent_sites> <equivalent_sites>
<site pb_type="memory"/> <site pb_type="memory"/>
</equivalent_sites> </equivalent_sites>
<input name="waddr" num_pins="10"/> <input name="waddr" num_pins="12"/>
<input name="raddr" num_pins="10"/> <input name="raddr" num_pins="12"/>
<input name="d_in" num_pins="32"/> <input name="data_in" num_pins="8"/>
<input name="wen" num_pins="1"/> <input name="wen" num_pins="1"/>
<input name="ren" num_pins="1"/> <input name="ren" num_pins="1"/>
<output name="d_out" num_pins="32"/> <output name="data_out" num_pins="8"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/> <pinlocations pattern="custom">
<loc side="left" yoffset="0">memory.clk</loc>
<loc side="top" yoffset="1"></loc>
<loc side="right" yoffset="0">memory.wen memory.waddr[0:3] memory.raddr[0:3] memory.data_in[0:2] memory.data_out[0:2]</loc>
<loc side="right" yoffset="1">memory.ren memory.waddr[4:7] memory.raddr[4:7] memory.data_in[3:5] memory.data_out[3:5]</loc>
<loc side="bottom" yoffset="0">memory.waddr[8:11] memory.raddr[8:11] memory.data_in[6:7] memory.data_out[6:7]</loc>
</pinlocations>
</tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
@ -682,57 +688,57 @@
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
<!-- Define single-mode dual-port memory begin --> <!-- Define single-mode dual-port memory begin -->
<pb_type name="memory"> <pb_type name="memory">
<input name="waddr" num_pins="10"/> <input name="waddr" num_pins="12"/>
<input name="raddr" num_pins="10"/> <input name="raddr" num_pins="12"/>
<input name="d_in" num_pins="32"/> <input name="data_in" num_pins="8"/>
<input name="wen" num_pins="1"/> <input name="wen" num_pins="1"/>
<input name="ren" num_pins="1"/> <input name="ren" num_pins="1"/>
<output name="d_out" num_pins="32"/> <output name="data_out" num_pins="8"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Specify the 512x32=16Kbit memory block <!-- Specify the 2048x8=16Kbit memory block
Note: the delay numbers are extracted from VPR flagship XML without modification Note: the delay numbers are extracted from VPR flagship XML without modification
Should align to the process technology we using to create the 16K dual-port RAM Should align to the process technology we using to create the 16K dual-port RAM
--> -->
<mode name="mem_512x32_dp"> <mode name="mem_2048x8_dp">
<pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> <pb_type name="mem_2048x8_dp" blif_model=".subckt dpram_2048x8" num_pb="1">
<input name="waddr" num_pins="10" port_class="address"/> <input name="waddr" num_pins="12" port_class="address1"/>
<input name="raddr" num_pins="10" port_class="address"/> <input name="raddr" num_pins="12" port_class="address2"/>
<input name="d_in" num_pins="32" port_class="data_in"/> <input name="data_in" num_pins="8" port_class="data_in1"/>
<input name="wen" num_pins="1" port_class="write_en"/> <input name="wen" num_pins="1" port_class="write_en1"/>
<input name="ren" num_pins="1" port_class="write_en"/> <input name="ren" num_pins="1" port_class="write_en2"/>
<output name="d_out" num_pins="32" port_class="data_out"/> <output name="data_out" num_pins="8" port_class="data_out1"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/> <T_setup value="509e-12" port="mem_2048x8_dp.waddr" clock="clk"/>
<T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/> <T_setup value="509e-12" port="mem_2048x8_dp.raddr" clock="clk"/>
<T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/> <T_setup value="509e-12" port="mem_2048x8_dp.data_in" clock="clk"/>
<T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/> <T_setup value="509e-12" port="mem_2048x8_dp.wen" clock="clk"/>
<T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/> <T_setup value="509e-12" port="mem_2048x8_dp.ren" clock="clk"/>
<T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/> <T_clock_to_Q max="1.234e-9" port="mem_2048x8_dp.data_out" clock="clk"/>
<power method="pin-toggle"> <power method="pin-toggle">
<port name="clk" energy_per_toggle="17.9e-12"/> <port name="clk" energy_per_toggle="17.9e-12"/>
<static_power power_per_instance="0.0"/> <static_power power_per_instance="0.0"/>
</power> </power>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr"> <direct name="waddress" input="memory.waddr" output="mem_2048x8_dp.waddr">
<delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/> <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_2048x8_dp.waddr"/>
</direct> </direct>
<direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr"> <direct name="raddress" input="memory.raddr" output="mem_2048x8_dp.raddr">
<delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/> <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_2048x8_dp.raddr"/>
</direct> </direct>
<direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in"> <direct name="data_input" input="memory.data_in" output="mem_2048x8_dp.data_in">
<delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/> <delay_constant max="132e-12" in_port="memory.data_in" out_port="mem_2048x8_dp.data_in"/>
</direct> </direct>
<direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen"> <direct name="writeen" input="memory.wen" output="mem_2048x8_dp.wen">
<delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/> <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_2048x8_dp.wen"/>
</direct> </direct>
<direct name="readen" input="memory.ren" output="mem_512x32_dp.ren"> <direct name="readen" input="memory.ren" output="mem_2048x8_dp.ren">
<delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/> <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_2048x8_dp.ren"/>
</direct> </direct>
<direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out"> <direct name="dataout" input="mem_2048x8_dp.data_out" output="memory.data_out">
<delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/> <delay_constant max="40e-12" in_port="mem_2048x8_dp.data_out" out_port="memory.data_out"/>
</direct> </direct>
<direct name="clk" input="memory.clk" output="mem_512x32_dp.clk"> <direct name="clk" input="memory.clk" output="mem_2048x8_dp.clk">
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>

93
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
View File

@ -118,14 +118,14 @@
<port name="lut6_out"/> <port name="lut6_out"/>
</output_ports> </output_ports>
</model> </model>
<model name="dual_port_ram"> <model name="dpram_2048x8">
<input_ports> <input_ports>
<!-- write address lines --> <!-- write address lines -->
<port name="waddr" clock="clk"/> <port name="waddr" clock="clk"/>
<!-- read address lines --> <!-- read address lines -->
<port name="raddr" clock="clk"/> <port name="raddr" clock="clk"/>
<!-- data lines can be broken down into smaller bit widths minimum size 1 --> <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
<port name="d_in" clock="clk"/> <port name="data_in" clock="clk"/>
<!-- write enable --> <!-- write enable -->
<port name="wen" clock="clk"/> <port name="wen" clock="clk"/>
<!-- read enable --> <!-- read enable -->
@ -135,7 +135,7 @@
</input_ports> </input_ports>
<output_ports> <output_ports>
<!-- output can be broken down into smaller bit widths minimum size 1 --> <!-- output can be broken down into smaller bit widths minimum size 1 -->
<port name="d_out" clock="clk"/> <port name="data_out" clock="clk"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
@ -176,19 +176,28 @@
<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc> <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
</pinlocations> </pinlocations>
</tile> </tile>
<tile name="memory" width="2" height="2" area="548000"> <tile name="memory" height="2" width="2" area="548000">
<equivalent_sites> <equivalent_sites>
<site pb_type="memory"/> <site pb_type="memory"/>
</equivalent_sites> </equivalent_sites>
<input name="waddr" num_pins="10"/> <input name="waddr" num_pins="12"/>
<input name="raddr" num_pins="10"/> <input name="raddr" num_pins="12"/>
<input name="d_in" num_pins="32"/> <input name="data_in" num_pins="8"/>
<input name="wen" num_pins="1"/> <input name="wen" num_pins="1"/>
<input name="ren" num_pins="1"/> <input name="ren" num_pins="1"/>
<output name="d_out" num_pins="32"/> <output name="data_out" num_pins="8"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="perimeter"/> <pinlocations pattern="custom">
<loc side="left" yoffset="0">memory.clk memory.waddr[0:1] memory.raddr[0:1] memory.data_in[0:0] memory.data_out[0:0]</loc>
<loc side="left" yoffset="1">memory.waddr[2:3] memory.raddr[2:3] memory.data_in[1:1] memory.data_out[1:1]</loc>
<loc side="top" xoffset="0" yoffset="1">memory.waddr[4:5] memory.raddr[4:5] memory.data_in[2:2] memory.data_out[2:2]</loc>
<loc side="top" xoffset="0" yoffset="1">memory.waddr[6:7] memory.raddr[6:7] memory.data_in[3:3] memory.data_out[3:3]</loc>
<loc side="right" xoffset="1" yoffset="0">memory.waddr[8:8] memory.raddr[8:8] memory.data_in[4:4] memory.data_out[4:4]</loc>
<loc side="right" xoffset="1" yoffset="1">memory.waddr[9:9] memory.raddr[9:9] memory.data_in[5:5] memory.data_out[5:5]</loc>
<loc side="bottom" xoffset="0">memory.wen memory.waddr[10:10] memory.raddr[10:10] memory.data_in[6:6] memory.data_out[6:6]</loc>
<loc side="bottom" xoffset="1">memory.ren memory.waddr[11:11] memory.raddr[11:11] memory.data_in[7:7] memory.data_out[7:7]</loc>
</pinlocations>
</tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
@ -204,7 +213,7 @@
<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/> <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/> <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
</auto_layout> </auto_layout>
<fixed_layout name="4x4" width="6" height="6"> <fixed_layout name="4x2" width="6" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
@ -682,57 +691,57 @@
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
<!-- Define single-mode dual-port memory begin --> <!-- Define single-mode dual-port memory begin -->
<pb_type name="memory"> <pb_type name="memory">
<input name="waddr" num_pins="10"/> <input name="waddr" num_pins="12"/>
<input name="raddr" num_pins="10"/> <input name="raddr" num_pins="12"/>
<input name="d_in" num_pins="32"/> <input name="data_in" num_pins="8"/>
<input name="wen" num_pins="1"/> <input name="wen" num_pins="1"/>
<input name="ren" num_pins="1"/> <input name="ren" num_pins="1"/>
<output name="d_out" num_pins="32"/> <output name="data_out" num_pins="8"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Specify the 512x32=16Kbit memory block <!-- Specify the 2048x8=16Kbit memory block
Note: the delay numbers are extracted from VPR flagship XML without modification Note: the delay numbers are extracted from VPR flagship XML without modification
Should align to the process technology we using to create the 16K dual-port RAM Should align to the process technology we using to create the 16K dual-port RAM
--> -->
<mode name="mem_512x32_dp"> <mode name="mem_2048x8_dp">
<pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1"> <pb_type name="mem_2048x8_dp" blif_model=".subckt dpram_2048x8" num_pb="1">
<input name="waddr" num_pins="10" port_class="address"/> <input name="waddr" num_pins="12" port_class="address1"/>
<input name="raddr" num_pins="10" port_class="address"/> <input name="raddr" num_pins="12" port_class="address2"/>
<input name="d_in" num_pins="32" port_class="data_in"/> <input name="data_in" num_pins="8" port_class="data_in1"/>
<input name="wen" num_pins="1" port_class="write_en"/> <input name="wen" num_pins="1" port_class="write_en1"/>
<input name="ren" num_pins="1" port_class="write_en"/> <input name="ren" num_pins="1" port_class="write_en2"/>
<output name="d_out" num_pins="32" port_class="data_out"/> <output name="data_out" num_pins="8" port_class="data_out1"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/> <T_setup value="509e-12" port="mem_2048x8_dp.waddr" clock="clk"/>
<T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/> <T_setup value="509e-12" port="mem_2048x8_dp.raddr" clock="clk"/>
<T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/> <T_setup value="509e-12" port="mem_2048x8_dp.data_in" clock="clk"/>
<T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/> <T_setup value="509e-12" port="mem_2048x8_dp.wen" clock="clk"/>
<T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/> <T_setup value="509e-12" port="mem_2048x8_dp.ren" clock="clk"/>
<T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/> <T_clock_to_Q max="1.234e-9" port="mem_2048x8_dp.data_out" clock="clk"/>
<power method="pin-toggle"> <power method="pin-toggle">
<port name="clk" energy_per_toggle="17.9e-12"/> <port name="clk" energy_per_toggle="17.9e-12"/>
<static_power power_per_instance="0.0"/> <static_power power_per_instance="0.0"/>
</power> </power>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr"> <direct name="waddress" input="memory.waddr" output="mem_2048x8_dp.waddr">
<delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/> <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_2048x8_dp.waddr"/>
</direct> </direct>
<direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr"> <direct name="raddress" input="memory.raddr" output="mem_2048x8_dp.raddr">
<delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/> <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_2048x8_dp.raddr"/>
</direct> </direct>
<direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in"> <direct name="data_input" input="memory.data_in" output="mem_2048x8_dp.data_in">
<delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/> <delay_constant max="132e-12" in_port="memory.data_in" out_port="mem_2048x8_dp.data_in"/>
</direct> </direct>
<direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen"> <direct name="writeen" input="memory.wen" output="mem_2048x8_dp.wen">
<delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/> <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_2048x8_dp.wen"/>
</direct> </direct>
<direct name="readen" input="memory.ren" output="mem_512x32_dp.ren"> <direct name="readen" input="memory.ren" output="mem_2048x8_dp.ren">
<delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/> <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_2048x8_dp.ren"/>
</direct> </direct>
<direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out"> <direct name="dataout" input="mem_2048x8_dp.data_out" output="memory.data_out">
<delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/> <delay_constant max="40e-12" in_port="mem_2048x8_dp.data_out" out_port="memory.data_out"/>
</direct> </direct>
<direct name="clk" input="memory.clk" output="mem_512x32_dp.clk"> <direct name="clk" input="memory.clk" output="mem_2048x8_dp.clk">
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>