From 0f3f4b0d8145382fbc34c561695ca32a184bf876 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 22 Jul 2023 23:55:54 -0700 Subject: [PATCH] [core] now tile module use unique port name (for heterogeneous blocks) --- openfpga/src/fabric/build_tile_modules.cpp | 40 ++++++++++++++++------ 1 file changed, 29 insertions(+), 11 deletions(-) diff --git a/openfpga/src/fabric/build_tile_modules.cpp b/openfpga/src/fabric/build_tile_modules.cpp index 6aafad219..d4bf74fc1 100644 --- a/openfpga/src/fabric/build_tile_modules.cpp +++ b/openfpga/src/fabric/build_tile_modules.cpp @@ -64,13 +64,16 @@ static int build_tile_module_port_and_nets_between_sb_and_pb( const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph, const RRGSB& rr_gsb, const FabricTile& fabric_tile, const FabricTileId& fabric_tile_id, const std::vector& pb_instances, - const size_t& sb_instance, const bool& compact_routing_hierarchy, + const std::vector& sb_instances, + const size_t& isb, const bool& compact_routing_hierarchy, const bool& frame_view, const bool& verbose) { /* Skip those Switch blocks that do not exist */ if (false == rr_gsb.is_sb_exist()) { return CMD_EXEC_SUCCESS; } + size_t sb_instance = sb_instances[isb]; + /* We could have two different coordinators, one is the instance, the other is * the module */ vtr::Point instance_sb_coordinate(rr_gsb.get_sb_x(), @@ -195,7 +198,8 @@ static int build_tile_module_port_and_nets_between_sb_and_pb( } } else { /* Create a port on the tile module and create the net if required. - * FIXME: Create a proper name to avoid naming conflicts */ + * Create a proper name to avoid naming conflicts */ + src_grid_port.set_name(generate_tile_module_port_name(fabric_tile.sb_coordinates(fabric_tile_id, isb), src_grid_port.get_name())); ModulePortId src_tile_port_id = module_manager.add_port( tile_module, src_grid_port, ModuleManager::e_module_port_type::MODULE_INPUT_PORT); @@ -284,9 +288,12 @@ static int build_tile_module_port_and_nets_between_cb_and_pb( const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph, const RRGSB& rr_gsb, const FabricTile& fabric_tile, const FabricTileId& fabric_tile_id, const t_rr_type& cb_type, - const std::vector& pb_instances, const size_t& cb_instance, + const std::vector& pb_instances, + const std::vector& cb_instances, + const size_t& icb, const bool& compact_routing_hierarchy, const bool& frame_view, const bool& verbose) { + size_t cb_instance = cb_instances.at(cb_type)[icb]; /* We could have two different coordinators, one is the instance, the other is * the module */ vtr::Point instance_cb_coordinate(rr_gsb.get_cb_x(cb_type), @@ -413,6 +420,7 @@ static int build_tile_module_port_and_nets_between_cb_and_pb( } else { /* Create a port on the tile module and create the net if required. * FIXME: Create a proper name to avoid naming conflicts */ + src_cb_port.set_name(generate_tile_module_port_name(fabric_tile.cb_coordinates(fabric_tile_id, cb_type, icb), src_cb_port.get_name())); ModulePortId sink_tile_port_id = module_manager.add_port( tile_module, src_cb_port, ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT); @@ -485,8 +493,11 @@ static int build_tile_module_port_and_nets_between_sb_and_cb( const RRGSB& rr_gsb, const FabricTile& fabric_tile, const FabricTileId& fabric_tile_id, const std::map>& cb_instances, - const size_t& sb_instance, const bool& compact_routing_hierarchy, + const std::vector& sb_instances, + const size_t& isb, + const bool& compact_routing_hierarchy, const bool& frame_view, const bool& verbose) { + size_t sb_instance = sb_instances[isb]; /* We could have two different coordinators, one is the instance, the other is * the module */ vtr::Point instance_sb_coordinate(rr_gsb.get_sb_x(), @@ -663,6 +674,7 @@ static int build_tile_module_port_and_nets_between_sb_and_cb( module_manager.find_module_port(sb_module_id, chan_input_port_name); BasicPort chan_input_port = module_manager.module_port(sb_module_id, sb_chan_input_port_id); + chan_input_port.set_name(generate_tile_module_port_name(fabric_tile.sb_coordinates(fabric_tile_id, isb), chan_input_port.get_name())); ModulePortId tile_chan_input_port_id = module_manager.add_port( tile_module, chan_input_port, ModuleManager::e_module_port_type::MODULE_INPUT_PORT); @@ -692,6 +704,7 @@ static int build_tile_module_port_and_nets_between_sb_and_cb( module_manager.find_module_port(sb_module_id, chan_output_port_name); BasicPort chan_output_port = module_manager.module_port(sb_module_id, sb_chan_output_port_id); + chan_output_port.set_name(generate_tile_module_port_name(fabric_tile.sb_coordinates(fabric_tile_id, isb), chan_output_port.get_name())); ModulePortId tile_chan_output_port_id = module_manager.add_port( tile_module, chan_output_port, ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT); @@ -739,8 +752,12 @@ static int build_tile_module_port_and_nets_between_sb_and_cb( static int build_tile_port_and_nets_from_pb( ModuleManager& module_manager, const ModuleId& tile_module, const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation, - const vtr::Point& pb_coord, const size_t& pb_instance, + const vtr::Point& pb_coord, + const std::vector& pb_instances, + const size_t& ipb, const bool& frame_view, const bool& verbose) { + /* FIXME: Should consider tile direct connections here! */ + size_t pb_instance = pb_instances[ipb]; t_physical_tile_type_ptr phy_tile = grids.get_physical_type(pb_coord.x(), pb_coord.y()); /* Empty type does not require a module */ @@ -810,6 +827,8 @@ static int build_tile_port_and_nets_from_pb( pb_coord.x(), pb_coord.y()); return CMD_EXEC_FATAL_ERROR; } + /* Create a proper name to avoid naming conflicts */ + pb_port.set_name(generate_tile_module_port_name(fabric_tile.pb_coordinates(fabric_tile_id, ipb), pb_port.get_name())); /* Find the port from the pb module and see if it is already been * driven or driving a net. if not, create a new port at the tile @@ -829,8 +848,7 @@ static int build_tile_port_and_nets_from_pb( "programmable block '%s'...\n", pb_port.to_verilog_string().c_str(), pb_module_name.c_str()); - /* Create a new port and a new net. FIXME: Create a proper name to - * avoid naming conflicts */ + /* Create a new port and a new net. */ ModulePortId tile_module_port_id = module_manager.add_port( tile_module, pb_port, ModuleManager::e_module_port_type::MODULE_INPUT_PORT); @@ -921,7 +939,7 @@ static int build_tile_module_ports_and_nets( status_code = build_tile_module_port_and_nets_between_sb_and_pb( module_manager, tile_module, grids, vpr_device_annotation, device_rr_gsb, rr_graph_view, rr_gsb, fabric_tile, fabric_tile_id, pb_instances, - sb_instances[isb], true, frame_view, verbose); + sb_instances, isb, true, frame_view, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } @@ -938,7 +956,7 @@ static int build_tile_module_ports_and_nets( status_code = build_tile_module_port_and_nets_between_cb_and_pb( module_manager, tile_module, grids, vpr_device_annotation, device_rr_gsb, rr_graph_view, rr_gsb, fabric_tile, fabric_tile_id, - cb_type, pb_instances, cb_instances.at(cb_type)[icb], true, frame_view, + cb_type, pb_instances, cb_instances, icb, true, frame_view, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; @@ -954,7 +972,7 @@ static int build_tile_module_ports_and_nets( const RRGSB& rr_gsb = device_rr_gsb.get_gsb(sb_coord); status_code = build_tile_module_port_and_nets_between_sb_and_cb( module_manager, tile_module, device_rr_gsb, rr_graph_view, rr_gsb, - fabric_tile, fabric_tile_id, cb_instances, sb_instances[isb], true, + fabric_tile, fabric_tile_id, cb_instances, sb_instances, isb, true, frame_view, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; @@ -968,7 +986,7 @@ static int build_tile_module_ports_and_nets( fabric_tile.pb_coordinates(fabric_tile_id)[ipb]; status_code = build_tile_port_and_nets_from_pb( module_manager, tile_module, grids, vpr_device_annotation, pb_coord, - pb_instances[ipb], frame_view, verbose); + pb_instances, ipb, frame_view, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; }