diff --git a/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml
index d93495f6b..17eb8b550 100644
--- a/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml
@@ -96,7 +96,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -106,7 +105,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -116,7 +114,6 @@
       <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -127,7 +124,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -150,7 +146,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -161,7 +156,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="inout" prefix="pad" size="1"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
index b750f9736..c43614ae8 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
@@ -110,7 +110,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -120,7 +119,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -130,7 +128,6 @@
       <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -141,7 +138,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -167,7 +163,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -178,7 +173,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="inout" prefix="pad" size="1"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
index 98823698f..cf619cd27 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
@@ -110,7 +110,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -120,7 +119,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -130,7 +128,6 @@
       <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -141,7 +138,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -168,7 +164,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -179,7 +174,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="inout" prefix="pad" size="1"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
@@ -189,7 +183,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="a" size="1"/>
       <port type="input" prefix="b" size="1"/>
       <port type="input" prefix="cin" size="1"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
index 9f37c1293..4ddf1dd0b 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
@@ -110,7 +110,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -120,7 +119,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -130,7 +128,6 @@
       <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -141,7 +138,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -168,7 +164,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -179,7 +174,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="inout" prefix="pad" size="1"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
@@ -189,7 +183,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="a" size="1"/>
       <port type="input" prefix="b" size="1"/>
       <port type="input" prefix="cin" size="1"/>
@@ -200,7 +193,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="waddr" size="10"/>
       <port type="input" prefix="raddr" size="10"/>
       <port type="input" prefix="d_in" size="32"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
index ea56fe036..f0e84e167 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
@@ -110,7 +110,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -120,7 +119,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -130,7 +128,6 @@
       <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -141,7 +138,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -168,7 +164,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -179,7 +174,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="inout" prefix="pad" size="1"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
@@ -189,7 +183,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="a" size="1"/>
       <port type="input" prefix="b" size="1"/>
       <port type="input" prefix="cin" size="1"/>
@@ -200,7 +193,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="waddr" size="10"/>
       <port type="input" prefix="raddr" size="10"/>
       <port type="input" prefix="d_in" size="32"/>
@@ -213,7 +205,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="tx_data" size="80"/>
       <port type="output" prefix="rx_data" size="80"/>
       <port type="clock" prefix="tx_clk" size="1" default_val="0"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
index 34f44d153..d70ebcb2d 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
@@ -110,7 +110,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -120,7 +119,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -130,7 +128,6 @@
       <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -141,7 +138,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -168,7 +164,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -179,7 +174,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="inout" prefix="pad" size="1"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
@@ -189,7 +183,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="a" size="1"/>
       <port type="input" prefix="b" size="1"/>
       <port type="input" prefix="cin" size="1"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
index 2b432ce86..547c742c8 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
@@ -110,7 +110,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -120,7 +119,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -130,7 +128,6 @@
       <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -141,7 +138,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -167,7 +163,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -178,7 +173,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="inout" prefix="pad" size="1"/>
       <!-- A spypad for the direction port of the I/O pad, which can be visible in the fpga_top -->
       <port type="input" prefix="din" size="1" is_global="true" io="true" default_value="0"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
index dc0fa4c27..bcbcb7e00 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
@@ -110,7 +110,6 @@
       <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -120,7 +119,6 @@
       <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -131,7 +129,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -157,7 +154,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -168,7 +164,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="inout" prefix="pad" size="1"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>