From 0e620f35a4eff1237a9ba64acb51bbf93a94d4f0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 6 Nov 2019 11:45:28 -0700 Subject: [PATCH] bug fixed for MUX2 std cells, avoid duplicated module writing --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 06c2e1f4c..69eea6452 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -582,6 +582,13 @@ void generate_verilog_mux_branch_module(ModuleManager& module_manager, /* Multiplexers built with different technology is in different organization */ switch (circuit_lib.design_tech_type(mux_model)) { case SPICE_MODEL_DESIGN_CMOS: + /* Skip module writing if the branch subckt is a standard cell! */ + if (true == circuit_lib.valid_model_id(circuit_lib.model(module_name))) { + /* This model must be a MUX2 gate */ + VTR_ASSERT(SPICE_MODEL_GATE == circuit_lib.model_type(circuit_lib.model(module_name))); + VTR_ASSERT(SPICE_MODEL_GATE_MUX2 == circuit_lib.gate_type(circuit_lib.model(module_name))); + break; + } if (true == circuit_lib.dump_structural_verilog(mux_model)) { /* Structural verilog can be easily generated by module writer */ ModuleId mux_module = module_manager.find_module(module_name);