add configuration bus nets for memory bank decoders at top module
This commit is contained in:
tangxifan
parent
fa8dfc1fbd
commit
0e16ee1030
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@ -156,6 +156,34 @@ std::string generate_frame_memory_decoder_subckt_name(const size_t& addr_size,
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return subckt_name;
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}
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/************************************************
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* Generate the module name of a bit-line decoder
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* for memories
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***********************************************/
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std::string generate_bl_memory_decoder_subckt_name(const size_t& addr_size,
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const size_t& data_size) {
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std::string subckt_name = "bl_decoder";
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subckt_name += std::to_string(addr_size);
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subckt_name += "to";
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subckt_name += std::to_string(data_size);
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return subckt_name;
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}
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/************************************************
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* Generate the module name of a word-line decoder
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* for memories
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***********************************************/
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std::string generate_wl_memory_decoder_subckt_name(const size_t& addr_size,
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const size_t& data_size) {
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std::string subckt_name = "wl_decoder";
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subckt_name += std::to_string(addr_size);
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subckt_name += "to";
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subckt_name += std::to_string(data_size);
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return subckt_name;
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}
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/************************************************
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* Generate the module name of a routing track wire
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***********************************************/
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@ -53,6 +53,12 @@ std::string generate_mux_local_decoder_subckt_name(const size_t& addr_size,
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std::string generate_frame_memory_decoder_subckt_name(const size_t& addr_size,
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const size_t& data_size);
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std::string generate_bl_memory_decoder_subckt_name(const size_t& addr_size,
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const size_t& data_size);
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std::string generate_wl_memory_decoder_subckt_name(const size_t& addr_size,
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const size_t& data_size);
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std::string generate_segment_wire_subckt_name(const std::string& wire_model_name,
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const size_t& segment_id);
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@ -74,6 +74,119 @@ ModuleId build_frame_memory_decoder_module(ModuleManager& module_manager,
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return module_id;
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}
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/***************************************************************************************
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* Create a module for a BL decoder with a given output size
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*
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* BL Address
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* | | ... |
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* v v v
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* +-----------+
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* / \<-- data_in
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* enable-->/ Decoder \
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* +-----------------+
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* | | | ... | | |
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* v v v v v v
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* Data Outputs
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*
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* The outputs are assumes to be one-hot codes (at most only one '1' exist)
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* Considering this fact, there are only num_of_outputs conditions to be encoded.
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* Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2))
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***************************************************************************************/
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ModuleId build_bl_memory_decoder_module(ModuleManager& module_manager,
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const DecoderLibrary& decoder_lib,
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const DecoderId& decoder) {
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/* Get the number of inputs */
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size_t addr_size = decoder_lib.addr_size(decoder);
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size_t data_size = decoder_lib.data_size(decoder);
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/* Create a name for the local encoder */
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std::string module_name = generate_bl_memory_decoder_subckt_name(addr_size, data_size);
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/* Create a Verilog Module based on the circuit model, and add to module manager */
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ModuleId module_id = module_manager.add_module(module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(module_id));
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/* Add enable port */
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BasicPort en_port(std::string(DECODER_ENABLE_PORT_NAME), 1);
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module_manager.add_port(module_id, en_port, ModuleManager::MODULE_INPUT_PORT);
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/* Add each input port */
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BasicPort addr_port(std::string(DECODER_ADDRESS_PORT_NAME), addr_size);
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module_manager.add_port(module_id, addr_port, ModuleManager::MODULE_INPUT_PORT);
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/* Add each input port */
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BasicPort din_port(std::string(DECODER_DATA_IN_PORT_NAME), 1);
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module_manager.add_port(module_id, din_port, ModuleManager::MODULE_INPUT_PORT);
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/* Add each output port */
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BasicPort data_port(std::string(DECODER_DATA_OUT_PORT_NAME), data_size);
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module_manager.add_port(module_id, data_port, ModuleManager::MODULE_OUTPUT_PORT);
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/* Data port is registered. It should be outputted as
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* output reg [lsb:msb] data
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*/
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module_manager.set_port_is_register(module_id, data_port.get_name(), true);
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/* Add data_in port */
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if (true == decoder_lib.use_data_inv_port(decoder)) {
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BasicPort data_inv_port(std::string(DECODER_DATA_OUT_INV_PORT_NAME), data_size);
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module_manager.add_port(module_id, data_inv_port, ModuleManager::MODULE_OUTPUT_PORT);
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}
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return module_id;
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}
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/***************************************************************************************
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* Create a module for a Word-line decoder with a given output size
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*
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* WL Address
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* | | ... |
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* v v v
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* +-----------+
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* / \
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* enable-->/ Decoder \
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* +-----------------+
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* | | | ... | | |
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* v v v v v v
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* Data Outputs
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*
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* The outputs are assumes to be one-hot codes (at most only one '1' exist)
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* Considering this fact, there are only num_of_outputs conditions to be encoded.
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* Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2))
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***************************************************************************************/
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ModuleId build_wl_memory_decoder_module(ModuleManager& module_manager,
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const DecoderLibrary& decoder_lib,
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const DecoderId& decoder) {
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/* Get the number of inputs */
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size_t addr_size = decoder_lib.addr_size(decoder);
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size_t data_size = decoder_lib.data_size(decoder);
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/* Create a name for the local encoder */
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std::string module_name = generate_wl_memory_decoder_subckt_name(addr_size, data_size);
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/* Create a Verilog Module based on the circuit model, and add to module manager */
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ModuleId module_id = module_manager.add_module(module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(module_id));
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/* Add enable port */
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BasicPort en_port(std::string(DECODER_ENABLE_PORT_NAME), 1);
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module_manager.add_port(module_id, en_port, ModuleManager::MODULE_INPUT_PORT);
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/* Add each input port */
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BasicPort addr_port(std::string(DECODER_ADDRESS_PORT_NAME), addr_size);
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module_manager.add_port(module_id, addr_port, ModuleManager::MODULE_INPUT_PORT);
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/* Add each output port */
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BasicPort data_port(std::string(DECODER_DATA_OUT_PORT_NAME), data_size);
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module_manager.add_port(module_id, data_port, ModuleManager::MODULE_OUTPUT_PORT);
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/* Data port is registered. It should be outputted as
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* output reg [lsb:msb] data
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*/
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module_manager.set_port_is_register(module_id, data_port.get_name(), true);
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/* Add data_in port */
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if (true == decoder_lib.use_data_inv_port(decoder)) {
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BasicPort data_inv_port(std::string(DECODER_DATA_OUT_INV_PORT_NAME), data_size);
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module_manager.add_port(module_id, data_inv_port, ModuleManager::MODULE_OUTPUT_PORT);
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}
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return module_id;
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}
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/***************************************************************************************
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* Create a module for a decoder with a given output size
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*
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@ -20,6 +20,14 @@ ModuleId build_frame_memory_decoder_module(ModuleManager& module_manager,
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const DecoderLibrary& decoder_lib,
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const DecoderId& decoder);
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ModuleId build_bl_memory_decoder_module(ModuleManager& module_manager,
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const DecoderLibrary& decoder_lib,
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const DecoderId& decoder);
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ModuleId build_wl_memory_decoder_module(ModuleManager& module_manager,
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const DecoderLibrary& decoder_lib,
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const DecoderId& decoder);
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void build_mux_local_decoder_modules(ModuleManager& module_manager,
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const MuxLibrary& mux_lib,
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const CircuitLibrary& circuit_lib);
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@ -16,6 +16,7 @@
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#include "memory_utils.h"
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#include "decoder_library_utils.h"
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#include "module_manager_utils.h"
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#include "build_decoder_modules.h"
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#include "build_top_module_memory.h"
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/* begin namespace openfpga */
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@ -461,6 +462,249 @@ void add_top_module_sram_ports(ModuleManager& module_manager,
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}
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}
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/*********************************************************************
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* Top-level function to add nets for memory banks
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* - Find the number of BLs and WLs required
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* - Create BL and WL decoders, and add them to decoder library
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* - Create nets to connect from top-level module inputs to inputs of decoders
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* - Create nets to connect from outputs of decoders to BL/WL of configurable children
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*
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* WL_enable WL address
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* | |
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* v v
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* +-----------------------------------------------+
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* | Word Line Decoder |
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* +-----------------------------------------------+
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* +---------+ | | |
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* BL | | | | |
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* enable ---->| |-----------+--------------+---- ... |------+--> BL[0]
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* | | | | | | | |
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* | | | v | v | v
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* | Bit | | +------+ | +------+ | +------+
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* BL | Line | +-->| SRAM | +-->| SRAM | +->| SRAM |
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* address ---->| Decoder | | | [0] | | | [1] | ... | | [i] |
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* | | | +------+ | +------+ | +------+
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* | | | | |
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* | |-----------+--------------+---- --- | -----+--> BL[1]
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* | | | | | | | |
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* | | | v | v | v
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* | | | +------+ | +------+ | +------+
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* | | +-->| SRAM | | | SRAM | +->| SRAM |
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* | | | | [x] | | | [x+1]| ... | | [x+i]|
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* | | | +------+ | +------+ | +------+
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* | | | |
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* | | | ... ... ... | ...
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* | | | | |
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* | |-----------+--------------+---- --- | -----+--> BL[y]
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* | | | | | | | |
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* | | | v | v | v
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* | | | +------+ | +------+ | +------+
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* | | +-->| SRAM | +-->| SRAM | +->| SRAM |
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* | | | | [y] | | |[y+1] | ... | |[y+i] |
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* | | | +------+ | +------+ | +------+
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* BL | | v v v
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* data_in ---->| | WL[0] WL[1] WL[i]
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* +---------+
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*
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**********************************************************************/
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static
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void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manager,
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DecoderLibrary& decoder_lib,
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const ModuleId& top_module) {
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/* Find Enable port from the top-level module */
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ModulePortId en_port = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME));
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BasicPort en_port_info = module_manager.module_port(top_module, en_port);
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/* Find data-in port from the top-level module */
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ModulePortId din_port = module_manager.find_module_port(top_module, std::string(DECODER_DATA_IN_PORT_NAME));
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BasicPort din_port_info = module_manager.module_port(top_module, din_port);
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/* Find BL and WL address port from the top-level module */
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ModulePortId bl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_BL_ADDRESS_PORT_NAME));
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BasicPort bl_addr_port_info = module_manager.module_port(top_module, bl_addr_port);
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ModulePortId wl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_WL_ADDRESS_PORT_NAME));
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BasicPort wl_addr_port_info = module_manager.module_port(top_module, wl_addr_port);
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/* Find the number of BLs and WLs required to access each memory bit */
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size_t bl_addr_size = bl_addr_port_info.get_width();
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size_t wl_addr_size = wl_addr_port_info.get_width();
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size_t num_bls = find_memory_decoder_data_size(bl_addr_size);
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size_t num_wls = find_memory_decoder_data_size(wl_addr_size);
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/* Add the BL decoder module
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* Search the decoder library
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* If we find one, we use the module.
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* Otherwise, we create one and add it to the decoder library
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*/
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DecoderId bl_decoder_id = decoder_lib.find_decoder(bl_addr_size, num_bls,
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true, true, false);
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if (DecoderId::INVALID() == bl_decoder_id) {
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bl_decoder_id = decoder_lib.add_decoder(bl_addr_size, num_bls, true, true, false);
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}
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VTR_ASSERT(DecoderId::INVALID() != bl_decoder_id);
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/* Create a module if not existed yet */
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std::string bl_decoder_module_name = generate_bl_memory_decoder_subckt_name(bl_addr_size, num_bls);
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ModuleId bl_decoder_module = module_manager.find_module(bl_decoder_module_name);
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if (ModuleId::INVALID() == bl_decoder_module) {
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/* BL decoder has the same ports as the frame-based decoders
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* We reuse it here
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*/
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bl_decoder_module = build_bl_memory_decoder_module(module_manager,
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decoder_lib,
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bl_decoder_id);
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}
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VTR_ASSERT(ModuleId::INVALID() != bl_decoder_module);
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VTR_ASSERT(0 == module_manager.num_instance(top_module, bl_decoder_module));
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module_manager.add_child_module(top_module, bl_decoder_module);
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/* Add the WL decoder module
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* Search the decoder library
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* If we find one, we use the module.
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* Otherwise, we create one and add it to the decoder library
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*/
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DecoderId wl_decoder_id = decoder_lib.find_decoder(wl_addr_size, num_wls,
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true, false, false);
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if (DecoderId::INVALID() == wl_decoder_id) {
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wl_decoder_id = decoder_lib.add_decoder(wl_addr_size, num_wls, true, false, false);
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}
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VTR_ASSERT(DecoderId::INVALID() != wl_decoder_id);
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/* Create a module if not existed yet */
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std::string wl_decoder_module_name = generate_bl_memory_decoder_subckt_name(wl_addr_size, num_wls);
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ModuleId wl_decoder_module = module_manager.find_module(wl_decoder_module_name);
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if (ModuleId::INVALID() == wl_decoder_module) {
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/* BL decoder has the same ports as the frame-based decoders
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* We reuse it here
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*/
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wl_decoder_module = build_wl_memory_decoder_module(module_manager,
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decoder_lib,
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wl_decoder_id);
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}
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VTR_ASSERT(ModuleId::INVALID() != wl_decoder_module);
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VTR_ASSERT(0 == module_manager.num_instance(top_module, wl_decoder_module));
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module_manager.add_child_module(top_module, wl_decoder_module);
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/* Add module nets from the top module to BL decoder's inputs */
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ModulePortId bl_decoder_en_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_ENABLE_PORT_NAME));
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BasicPort bl_decoder_en_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_en_port);
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ModulePortId bl_decoder_addr_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_ADDRESS_PORT_NAME));
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BasicPort bl_decoder_addr_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_addr_port);
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ModulePortId bl_decoder_din_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_DATA_IN_PORT_NAME));
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BasicPort bl_decoder_din_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_din_port);
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/* Top module Enable port -> BL Decoder Enable port */
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add_module_bus_nets(module_manager,
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top_module,
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top_module, 0, en_port,
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bl_decoder_module, 0, bl_decoder_en_port);
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/* Top module Address port -> BL Decoder Address port */
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add_module_bus_nets(module_manager,
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top_module,
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top_module, 0, bl_addr_port,
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bl_decoder_module, 0, bl_decoder_addr_port);
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/* Top module data_in port -> BL Decoder data_in port */
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add_module_bus_nets(module_manager,
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top_module,
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top_module, 0, din_port,
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bl_decoder_module, 0, bl_decoder_din_port);
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/* Add module nets from the top module to WL decoder's inputs */
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ModulePortId wl_decoder_en_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_ENABLE_PORT_NAME));
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BasicPort wl_decoder_en_port_info = module_manager.module_port(wl_decoder_module, wl_decoder_en_port);
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ModulePortId wl_decoder_addr_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_ADDRESS_PORT_NAME));
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BasicPort wl_decoder_addr_port_info = module_manager.module_port(wl_decoder_module, bl_decoder_addr_port);
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/* Top module Enable port -> WL Decoder Enable port */
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add_module_bus_nets(module_manager,
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top_module,
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top_module, 0, en_port,
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wl_decoder_module, 0, wl_decoder_en_port);
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/* Top module Address port -> WL Decoder Address port */
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add_module_bus_nets(module_manager,
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top_module,
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top_module, 0, wl_addr_port,
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wl_decoder_module, 0, wl_decoder_addr_port);
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/* Add nets from BL data out to each configurable child */
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size_t cur_bl_index = 0;
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ModulePortId bl_decoder_dout_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME));
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BasicPort bl_decoder_dout_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_dout_port);
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for (size_t child_id = 0; child_id < module_manager.configurable_children(top_module).size(); ++child_id) {
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ModuleId child_module = module_manager.configurable_children(top_module)[child_id];
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size_t child_instance = module_manager.configurable_child_instances(top_module)[child_id];
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/* Find the BL port */
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ModulePortId child_bl_port = module_manager.find_module_port(child_module, std::string(MEMORY_BL_PORT_NAME));
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BasicPort child_bl_port_info = module_manager.module_port(child_module, child_bl_port);
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for (const size_t& sink_bl_pin : child_bl_port_info.pins()) {
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/* Find the BL decoder data index:
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* It should be the residual when divided by the number of BLs
|
||||
*/
|
||||
size_t bl_pin_id = cur_bl_index / num_bls;
|
||||
|
||||
/* Create net */
|
||||
ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
|
||||
bl_decoder_module, 0,
|
||||
bl_decoder_dout_port,
|
||||
bl_decoder_dout_port_info.pins()[bl_pin_id]);
|
||||
VTR_ASSERT(ModuleNetId::INVALID() != net);
|
||||
|
||||
/* Add net sink */
|
||||
module_manager.add_module_net_sink(top_module, net,
|
||||
child_module, child_instance, child_bl_port, sink_bl_pin);
|
||||
|
||||
/* Increment the BL index */
|
||||
cur_bl_index++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Add nets from WL data out to each configurable child */
|
||||
size_t cur_wl_index = 0;
|
||||
|
||||
ModulePortId wl_decoder_dout_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME));
|
||||
BasicPort wl_decoder_dout_port_info = module_manager.module_port(wl_decoder_module, wl_decoder_dout_port);
|
||||
|
||||
for (size_t child_id = 0; child_id < module_manager.configurable_children(top_module).size(); ++child_id) {
|
||||
ModuleId child_module = module_manager.configurable_children(top_module)[child_id];
|
||||
size_t child_instance = module_manager.configurable_child_instances(top_module)[child_id];
|
||||
|
||||
/* Find the WL port */
|
||||
ModulePortId child_wl_port = module_manager.find_module_port(child_module, std::string(MEMORY_WL_PORT_NAME));
|
||||
BasicPort child_wl_port_info = module_manager.module_port(child_module, child_wl_port);
|
||||
|
||||
for (const size_t& sink_wl_pin : child_wl_port_info.pins()) {
|
||||
/* Find the BL decoder data index:
|
||||
* It should be the residual when divided by the number of BLs
|
||||
*/
|
||||
size_t wl_pin_id = cur_wl_index % num_wls;
|
||||
|
||||
/* Create net */
|
||||
ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
|
||||
wl_decoder_module, 0,
|
||||
wl_decoder_dout_port,
|
||||
wl_decoder_dout_port_info.pins()[wl_pin_id]);
|
||||
VTR_ASSERT(ModuleNetId::INVALID() != net);
|
||||
|
||||
/* Add net sink */
|
||||
module_manager.add_module_net_sink(top_module, net,
|
||||
child_module, child_instance, child_wl_port, sink_wl_pin);
|
||||
|
||||
/* Increment the WL index */
|
||||
cur_wl_index++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* Add the port-to-port connection between all the memory modules
|
||||
|
|
@ -524,6 +768,7 @@ void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
|
|||
}
|
||||
case CONFIG_MEM_MEMORY_BANK:
|
||||
/* TODO */
|
||||
add_top_module_nets_cmos_memory_bank_config_bus(module_manager, decoder_lib, parent_module);
|
||||
break;
|
||||
case CONFIG_MEM_FRAME_BASED:
|
||||
add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib, parent_module);
|
||||
|
|
|
|||
|
|
@ -77,6 +77,10 @@ size_t find_memory_decoder_addr_size(const size_t& num_mems) {
|
|||
return find_mux_local_decoder_addr_size((size_t)std::ceil(std::sqrt((float)num_mems)));
|
||||
}
|
||||
|
||||
size_t find_memory_decoder_data_size(const size_t& num_addr) {
|
||||
return (size_t)std::pow(2., num_addr);
|
||||
}
|
||||
|
||||
/***************************************************************************************
|
||||
* Try to find if the decoder already exists in the library,
|
||||
* If there is no such decoder, add it to the library
|
||||
|
|
|
|||
|
|
@ -15,6 +15,8 @@ size_t find_mux_local_decoder_addr_size(const size_t& data_size);
|
|||
|
||||
size_t find_memory_decoder_addr_size(const size_t& num_mems);
|
||||
|
||||
size_t find_memory_decoder_data_size(const size_t& num_addr);
|
||||
|
||||
DecoderId add_mux_local_decoder_to_library(DecoderLibrary& decoder_lib,
|
||||
const size_t data_size);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue