diff --git a/openfpga/src/base/openfpga_verilog_template.h b/openfpga/src/base/openfpga_verilog_template.h
index 4545b3eeb..c9b4ff849 100644
--- a/openfpga/src/base/openfpga_verilog_template.h
+++ b/openfpga/src/base/openfpga_verilog_template.h
@@ -64,8 +64,8 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd,
     options.set_constant_undriven_inputs(cmd_context.option_value(cmd, opt_constant_undriven_inputs));
   }
   if (g_vpr_ctx.device().arch->perimeter_cb) {
-    if (FabricVerilogOptions::e_undriven_input_type::NONE == options.constant_undriven_inputs()) {
-      options.set_constant_undriven_inputs(FabricVerilogOptions::e_undriven_input_type::BUS0);
+    if (FabricVerilogOption::e_undriven_input_type::NONE == options.constant_undriven_inputs()) {
+      options.set_constant_undriven_inputs(FabricVerilogOption::e_undriven_input_type::BUS0);
       VTR_LOG(
         "Automatically enable the constant_undriven_input option as perimeter "
         "connection blocks are seen in FPGA fabric\n");
diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp
index a3b29f71e..571cca4df 100644
--- a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp
+++ b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp
@@ -72,9 +72,9 @@ size_t FabricVerilogOption::constant_undriven_inputs_value() const {
   return 0;
 }
 
-std::string FabricVerilogOption::full_constant_undriven_input_type_str() const;
+std::string FabricVerilogOption::full_constant_undriven_input_type_str() const {
   std::string full_type_str("[");
-  for (size_t itype = 0; itype < FabricVerilogOption::e_undriven_input_type::NUM_TYPES; ++itype) {
+  for (size_t itype = 0; itype < size_t(FabricVerilogOption::e_undriven_input_type::NUM_TYPES); ++itype) {
     full_type_str += std::string(CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_[itype]) + std::string("|");
   }
   full_type_str.pop_back();
@@ -137,7 +137,7 @@ void FabricVerilogOption::set_default_net_type(
 
 bool FabricVerilogOption::set_constant_undriven_inputs(const std::string& type_str) {
   bool valid_type = false;
-  for (size_t itype = 0; itype < FabricVerilogOption::e_undriven_input_type::NUM_TYPES; ++itype) {
+  for (size_t itype = 0; itype < size_t(FabricVerilogOption::e_undriven_input_type::NUM_TYPES); ++itype) {
     if (std::string(CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_[itype]) == type_str) {
       constant_undriven_inputs_ = static_cast<FabricVerilogOption::e_undriven_input_type>(itype);
       valid_type = true;
diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.h b/openfpga/src/fpga_verilog/fabric_verilog_options.h
index 1271277e0..9e29a9585 100644
--- a/openfpga/src/fpga_verilog/fabric_verilog_options.h
+++ b/openfpga/src/fpga_verilog/fabric_verilog_options.h
@@ -73,7 +73,7 @@ class FabricVerilogOption {
   bool time_stamp_;
   bool use_relative_path_;
   e_undriven_input_type constant_undriven_inputs_;
-  std::array<const char*, FabricVerilogOption::e_undriven_input_type::NUM_TYPES> CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_; //String versions of constant undriven input types
+  std::array<const char*, size_t(FabricVerilogOption::e_undriven_input_type::NUM_TYPES)> CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_; //String versions of constant undriven input types
   bool verbose_output_;
 };
 
diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
index 3ed9bce57..11f063f46 100644
--- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp
+++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
@@ -604,7 +604,7 @@ void write_verilog_module_to_file(
   }
 
   /* Use constant to drive undriven local wires */
-  if (options.constant_local_undriven_inputs() != FabricVerilogOption::e_undriven_input_type::NONE) {
+  if (options.constant_undriven_inputs() != FabricVerilogOption::e_undriven_input_type::NONE) {
     std::vector<ModuleManager::e_module_port_type> blacklist = {
       ModuleManager::e_module_port_type::MODULE_GLOBAL_PORT,
       ModuleManager::e_module_port_type::MODULE_GPIN_PORT,
@@ -619,14 +619,14 @@ void write_verilog_module_to_file(
     for (std::pair<std::string, std::vector<BasicPort>> port_group :
          local_undriven_wires) {
       for (const BasicPort& local_undriven_wire : port_group.second) {
-        if (options.constant_local_undriven_inputs_use_bus()) {
+        if (options.constant_undriven_inputs_use_bus()) {
           print_verilog_wire_constant_values(
             fp, local_undriven_wire,
-            std::vector<size_t>(local_undriven_wire.get_width(), options.constant_local_undriven_inputs_value()));
+            std::vector<size_t>(local_undriven_wire.get_width(), options.constant_undriven_inputs_value()));
         } else {
           print_verilog_wire_constant_values_bit_blast(
             fp, local_undriven_wire,
-            std::vector<size_t>(local_undriven_wire.get_width(), options.constant_local_undriven_inputs_value()));
+            std::vector<size_t>(local_undriven_wire.get_width(), options.constant_undriven_inputs_value()));
         }
       }
     }
@@ -658,7 +658,7 @@ void write_verilog_module_to_file(
       /* Print an instance */
       write_verilog_instance_to_file(fp, module_manager, module_id,
                                      child_module, instance,
-                                     options.use_explicit_port_map());
+                                     options.explicit_port_mapping());
       /* Print an empty line as splitter */
       fp << std::endl;
     }
diff --git a/openfpga/src/fpga_verilog/verilog_mux.cpp b/openfpga/src/fpga_verilog/verilog_mux.cpp
index d6b323e62..2fca08df4 100644
--- a/openfpga/src/fpga_verilog/verilog_mux.cpp
+++ b/openfpga/src/fpga_verilog/verilog_mux.cpp
@@ -676,7 +676,7 @@ static void generate_verilog_mux_branch_module(
         VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
         FabricVerilogOption curr_options = options;
         curr_options.set_explicit_port_mapping(
-          use_explicit_port_map ||
+          curr_options.explicit_port_mapping() ||
             circuit_lib.dump_explicit_port_map(mux_model));
         curr_options.set_constant_undriven_inputs(FabricVerilogOption::e_undriven_input_type::NONE);
         write_verilog_module_to_file(
@@ -688,13 +688,13 @@ static void generate_verilog_mux_branch_module(
         /* Behavioral verilog requires customized generation */
         print_verilog_cmos_mux_branch_module_behavioral(
           module_manager, circuit_lib, fp, mux_model, module_name, mux_graph,
-          default_net_type);
+          options.default_net_type());
       }
       break;
     case CIRCUIT_MODEL_DESIGN_RRAM:
       generate_verilog_rram_mux_branch_module(
         module_manager, circuit_lib, fp, mux_model, module_name, mux_graph,
-        default_net_type, circuit_lib.dump_structural_verilog(mux_model));
+        options.default_net_type(), circuit_lib.dump_structural_verilog(mux_model));
       break;
     default:
       VTR_LOGF_ERROR(__FILE__, __LINE__,
@@ -1403,8 +1403,8 @@ static void generate_verilog_rram_mux_module(
 static void generate_verilog_mux_module(
   ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
   std::fstream& fp, const CircuitModelId& mux_model, const MuxGraph& mux_graph,
-  const ModuleNameMap& module_name_map, const bool& use_explicit_port_map,
-  const e_verilog_default_net_type& default_net_type) {
+  const ModuleNameMap& module_name_map,
+  const FabricVerilogOption& options) {
   std::string module_name =
     generate_mux_subckt_name(circuit_lib, mux_model,
                              find_mux_num_datapath_inputs(
@@ -1420,13 +1420,13 @@ static void generate_verilog_mux_module(
       ModuleId mux_module = module_manager.find_module(module_name);
       VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
       FabricVerilogOption curr_options = options;
-      curr_option.set_explict_port_mapping(
-        (use_explicit_port_map ||
+      curr_options.set_explicit_port_mapping(
+        (curr_options.explicit_port_mapping() ||
          circuit_lib.dump_explicit_port_map(mux_model) ||
          circuit_lib.dump_explicit_port_map(
            circuit_lib.pass_gate_logic_model(mux_model)))
       );
-      curr_option.set_constant_undriven_inputs(FabricVerilogOption::e_undriven_input_type::NONE);
+      curr_options.set_constant_undriven_inputs(FabricVerilogOption::e_undriven_input_type::NONE);
       write_verilog_module_to_file(
         fp, module_manager, mux_module,
         curr_options);
@@ -1438,7 +1438,7 @@ static void generate_verilog_mux_module(
       /* TODO: RRAM-based Multiplexer Verilog module generation */
       generate_verilog_rram_mux_module(module_manager, circuit_lib, fp,
                                        mux_model, module_name, mux_graph,
-                                       default_net_type);
+                                       options.default_net_type());
       break;
     default:
       VTR_LOGF_ERROR(__FILE__, __LINE__,
@@ -1545,8 +1545,7 @@ static void print_verilog_submodule_mux_top_modules(
     /* Create MUX circuits */
     generate_verilog_mux_module(module_manager, circuit_lib, fp,
                                 mux_circuit_model, mux_graph, module_name_map,
-                                options.explicit_port_mapping(),
-                                options.default_net_type());
+                                options);
   }
 
   /* Close the file stream */
diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
index 8169b80ff..aef6cf5fa 100644
--- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
@@ -843,7 +843,7 @@ void print_verilog_wire_constant_values_bit_blast(
 
   for (size_t ipin : output_port.pins()) {
     BasicPort curr_pin(output_port.get_name(), ipin, ipin);
-    print_verilog_wire_constant_values_bit_blast(fp, curr_pin, const_values[ipin]);
+    print_verilog_wire_constant_values(fp, curr_pin, std::vector<size_t>(curr_pin.get_width(), const_values[ipin]));
   }
 }