diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py
index 0c36338a6..064defa19 100644
--- a/openfpga_flow/scripts/run_fpga_flow.py
+++ b/openfpga_flow/scripts/run_fpga_flow.py
@@ -411,8 +411,9 @@ def validate_command_line_arguments():
 
     # Expand run directory to absolute path
     args.run_dir = os.path.abspath(args.run_dir)
-    if args.activity_file:
-        args.activity_file = os.path.abspath(args.activity_file)
+    if args.power:
+      if args.activity_file:
+          args.activity_file = os.path.abspath(args.activity_file)
     if args.base_verilog:
         args.base_verilog = os.path.abspath(args.base_verilog)
 
@@ -717,10 +718,11 @@ def collect_files_for_vpr():
     shutil.copy(args.benchmark_files[0], args.top_module+".blif")
 
     # Sanitize provided Activity file option
-    if not os.path.isfile(args.activity_file or ""):
-        logger.error("Activity File - %s" % args.activity_file)
-        clean_up_and_exit("Provided activity file not found")
-    shutil.copy(args.activity_file, args.top_module+"_ace_out.act")
+    if args.power:
+      if not os.path.isfile(args.activity_file or ""):
+          logger.error("Activity File - %s" % args.activity_file)
+          clean_up_and_exit("Provided activity file not found")
+      shutil.copy(args.activity_file, args.top_module+"_ace_out.act")
 
     # Sanitize provided Benchmark option
     if not os.path.isfile(args.base_verilog or ""):
@@ -736,6 +738,7 @@ def run_openfpga_shell():
                          encoding='utf-8').read())
 
     path_variables = script_env_vars["PATH"]
+    path_variables["TOP_MODULE"] = args.top_module
     path_variables["VPR_ARCH_FILE"] = args.arch_file
     path_variables["OPENFPGA_ARCH_FILE"] = args.openfpga_arch_file
     path_variables["VPR_TESTBENCH_BLIF"] = args.top_module+".blif"
diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py
index 6b6e43294..2c73e98e8 100644
--- a/openfpga_flow/scripts/run_fpga_task.py
+++ b/openfpga_flow/scripts/run_fpga_task.py
@@ -317,11 +317,15 @@ def generate_each_task_actions(taskname):
                 CurrBenchPara["benchVariable"] += [f"--{param}", value]
 
         if GeneralSection.get("fpga_flow") == "vpr_blif":
-            # Check if activity file exist
-            if not SynthSection.get(bech_name+"_act"):
-                clean_up_and_exit("Missing argument %s" % (bech_name+"_act") +
-                                  "for vpr_blif flow")
-            CurrBenchPara["activity_file"] = SynthSection.get(bech_name+"_act")
+            # Check if activity file exist only when power analysis is required
+            if (GeneralSection.getboolean("power_analysis")):
+                if not SynthSection.get(bech_name+"_act"):
+                    clean_up_and_exit("Missing argument %s" % (bech_name+"_act") +
+                                      "for vpr_blif flow")
+                CurrBenchPara["activity_file"] = SynthSection.get(bech_name+"_act")
+            else:
+                # Send a dummy act
+                CurrBenchPara["activity_file"] = bech_name+"_act"
 
             # Check if base verilog file exists
             if not SynthSection.get(bech_name+"_verilog"):