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[test] fixed a bug where OPIN for direct connection is included in GSB

This commit is contained in:
tangxifan 2022-09-30 15:24:51 -07:00
parent 9c5be017bc
commit 0d8d8446ee
3 changed files with 21 additions and 41 deletions
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29
openfpga/src/annotation/annotate_rr_graph.cpp
View File

@ -256,15 +256,14 @@ RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
/* Fill opin_rr_nodes */
/* Copy from temp_opin_rr_node to opin_rr_node */
for (const RRNodeId& inode : temp_opin_rr_nodes[0]) {
for (size_t opin_array_id = 0; opin_array_id < temp_opin_rr_nodes.size(); ++opin_array_id) {
for (const RRNodeId& inode : temp_opin_rr_nodes[opin_array_id]) {
/* Skip those has no configurable outgoing, they should NOT appear in the GSB connection
* This is for those grid output pins used by direct connections
*/
if (0 == std::distance(vpr_device_ctx.rr_graph.node_configurable_out_edges(inode).begin(),
vpr_device_ctx.rr_graph.node_configurable_out_edges(inode).end())) {
if (0 == vpr_device_ctx.rr_graph.num_configurable_edges(inode)) {
continue;
}
/* Do not consider OPINs that directly drive an IPIN
* they are supposed to be handled by direct connection
*/
@ -275,25 +274,6 @@ RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
/* Grid[x+1][y+1] Bottom side outputs pins */
rr_gsb.add_opin_node(inode, side_manager.get_side());
}
for (const RRNodeId& inode : temp_opin_rr_nodes[1]) {
/* Skip those has no configurable outgoing, they should NOT appear in the GSB connection
* This is for those grid output pins used by direct connections
*/
if (0 == std::distance(vpr_device_ctx.rr_graph.node_configurable_out_edges(inode).begin(),
vpr_device_ctx.rr_graph.node_configurable_out_edges(inode).end())) {
continue;
}
/* Do not consider OPINs that directly drive an IPIN
* they are supposed to be handled by direct connection
*/
if (true == is_opin_direct_connected_ipin(vpr_device_ctx.rr_graph, inode)) {
continue;
}
/* Grid[x+1][y] TOP side outputs pins */
rr_gsb.add_opin_node(inode, side_manager.get_side());
}
/* Clean ipin_rr_nodes */
@ -375,8 +355,7 @@ RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
/* Skip those has no configurable outgoing, they should NOT appear in the GSB connection
* This is for those grid output pins used by direct connections
*/
if (0 == std::distance(vpr_device_ctx.rr_graph.node_configurable_in_edges(inode).begin(),
vpr_device_ctx.rr_graph.node_configurable_in_edges(inode).end())) {
if (0 == vpr_device_ctx.rr_graph.node_configurable_in_edges(inode).size()) {
continue;
}

3
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml
View File

@ -207,7 +207,8 @@
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
<direct_connection>
<direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
<!-- direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/-->
<direct name="adder_carry" circuit_model_name="direct_interc"/>
</direct_connection>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->

2
vtr-verilog-to-routing

@ -1 +1 @@
Subproject commit 2f1bfd32080e81c63b0ea3116fbafff2f085202e
Subproject commit c415acba3a44f0ca72c444f1bc17620d33de38d6