diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp
index d0097ced6..880edc74d 100644
--- a/openfpga/src/annotation/annotate_rr_graph.cpp
+++ b/openfpga/src/annotation/annotate_rr_graph.cpp
@@ -257,10 +257,25 @@ RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
     /* Fill opin_rr_nodes */
     /* Copy from temp_opin_rr_node to opin_rr_node */
     for (const RRNodeId& inode : temp_opin_rr_nodes[0]) {
+      /* Skip those has no configurable outgoing, they should NOT appear in the GSB connection
+       * This is for those grid output pins used by direct connections
+       */
+      if (0 == std::distance(vpr_device_ctx.rr_graph.node_configurable_out_edges(inode).begin(),
+                             vpr_device_ctx.rr_graph.node_configurable_out_edges(inode).end())) {
+        continue;
+      }
       /* Grid[x+1][y+1] Bottom side outputs pins */
       rr_gsb.add_opin_node(inode, side_manager.get_side());
     }
     for (const RRNodeId& inode : temp_opin_rr_nodes[1]) {
+      /* Skip those has no configurable outgoing, they should NOT appear in the GSB connection
+       * This is for those grid output pins used by direct connections
+       */
+      if (0 == std::distance(vpr_device_ctx.rr_graph.node_configurable_out_edges(inode).begin(),
+                             vpr_device_ctx.rr_graph.node_configurable_out_edges(inode).end())) {
+        continue;
+      }
+
       /* Grid[x+1][y] TOP side outputs pins */
       rr_gsb.add_opin_node(inode, side_manager.get_side());
     }
diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp
index 2ee5527e7..1562b2f3c 100644
--- a/openfpga/src/fabric/build_grid_modules.cpp
+++ b/openfpga/src/fabric/build_grid_modules.cpp
@@ -263,7 +263,7 @@ void build_primitive_block_module(ModuleManager& module_manager,
   /* Add all the nets to connect configuration ports from memory module to primitive modules
    * This is a one-shot addition that covers all the memory modules in this primitive module!
    */
-  if (false == memory_modules.empty()) {
+  if (0 < module_manager.configurable_children(primitive_module).size()) {
     add_module_nets_memory_config_bus(module_manager, primitive_module, 
                                       sram_orgz_type, circuit_lib.design_tech_type(sram_model));
   }
@@ -878,7 +878,7 @@ void rec_build_logical_tile_modules(ModuleManager& module_manager,
   /* Add module nets to connect memory cells inside
    * This is a one-shot addition that covers all the memory modules in this pb module!
    */
-  if (false == memory_modules.empty()) {
+  if (0 < module_manager.configurable_children(pb_module).size()) {
     add_module_nets_memory_config_bus(module_manager, pb_module, 
                                       sram_orgz_type, circuit_lib.design_tech_type(sram_model));
   }
diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
index 59f863701..34c2c4be7 100644
--- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp
+++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
@@ -32,11 +32,25 @@ namespace openfpga {
  *******************************************************************/
 static 
 std::string generate_verilog_undriven_local_wire_name(const ModuleManager& module_manager, 
-                                                      const ModuleId& module, 
-                                                      const ModulePortId& module_port_id) {
-  return module_manager.module_port(module, module_port_id).get_name();
+                                                      const ModuleId& parent, 
+                                                      const ModuleId& child, 
+                                                      const size_t& instance_id, 
+                                                      const ModulePortId& child_port_id) {
+  std::string wire_name;
+  if (!module_manager.instance_name(parent, child, instance_id).empty()) {
+    wire_name = module_manager.instance_name(parent, child, instance_id);
+  } else {
+    wire_name = module_manager.module_name(parent) + std::string("_") + std::to_string(instance_id); 
+    wire_name += std::string("_");
+  }
+  
+  wire_name += std::string("_undriven_");
+  wire_name += module_manager.module_port(child, child_port_id).get_name();
+  
+  return wire_name;
 }
 
+
 /********************************************************************
  * Name a net for a local wire for a verilog module 
  * 1. If this is a local wire, name it after the <src_module_name>_<instance_id>_<src_port_name>
@@ -176,7 +190,7 @@ std::map<std::string, std::vector<BasicPort>> find_verilog_module_local_wires(co
         }
         /* Reach here, we need a local wire, we will create a port only for the undriven pins of the port! */
         BasicPort instance_port;
-        instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, child, child_port_id));
+        instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, module_id, child, instance, child_port_id));
         /* We give the same port name as child module, this case happens to global ports */
         instance_port.set_width(*std::min_element(undriven_pins.begin(), undriven_pins.end()),
                                 *std::max_element(undriven_pins.begin(), undriven_pins.end())); 
@@ -413,7 +427,7 @@ void write_verilog_instance_to_file(std::fstream& fp,
         BasicPort instance_port;
         if (ModuleNetId::INVALID() == net) {
           /* We give the same port name as child module, this case happens to global ports */
-          instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, child_module, child_port_id));
+          instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, parent_module, child_module, instance_id, child_port_id));
           instance_port.set_width(child_pin, child_pin); 
         } else {
           /* Find the name for this child port */