From 0c6d27cf7ea056db2c82fa0b1578dd7faf9df469 Mon Sep 17 00:00:00 2001 From: Nachiket Kapre Date: Mon, 8 Feb 2021 21:26:48 -0500 Subject: [PATCH] merge for consideration; --- ...tdcell_mux_40nm_openfpga_synthesizable.xml | 223 ++++++++++++++++++ .../openfpga_cell_library/verilog/buf4.v | 29 +++ .../openfpga_cell_library/verilog/dffr.v | 35 +++ .../openfpga_cell_library/verilog/dffsrq.v | 36 +++ .../openfpga_cell_library/verilog/inv.v | 29 +++ 5 files changed, 352 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml create mode 100644 openfpga_flow/openfpga_cell_library/verilog/buf4.v create mode 100644 openfpga_flow/openfpga_cell_library/verilog/dffr.v create mode 100644 openfpga_flow/openfpga_cell_library/verilog/dffsrq.v create mode 100644 openfpga_flow/openfpga_cell_library/verilog/inv.v diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml new file mode 100644 index 000000000..6d7b080f1 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml @@ -0,0 +1,223 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_cell_library/verilog/buf4.v b/openfpga_flow/openfpga_cell_library/verilog/buf4.v new file mode 100644 index 000000000..a9f0585bc --- /dev/null +++ b/openfpga_flow/openfpga_cell_library/verilog/buf4.v @@ -0,0 +1,29 @@ +// ----- Verilog module for buf4 ----- +module buf4(in, + out); +//----- INPUT PORTS ----- +input [0:0] in; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Verilog codes of a regular inverter ----- + //assign out = (in === 1'bz)? $random : in; + assign out = in; + +`ifdef ENABLE_TIMING +// ------ BEGIN Pin-to-pin Timing constraints ----- + specify + (in[0] => out[0]) = (0.01, 0.01); + endspecify +// ------ END Pin-to-pin Timing constraints ----- +`endif +endmodule +// ----- END Verilog module for buf4 ----- + diff --git a/openfpga_flow/openfpga_cell_library/verilog/dffr.v b/openfpga_flow/openfpga_cell_library/verilog/dffr.v new file mode 100644 index 000000000..051fa71fb --- /dev/null +++ b/openfpga_flow/openfpga_cell_library/verilog/dffr.v @@ -0,0 +1,35 @@ +module DFFR(RST, + CK, + D, + Q, + QN); +//----- GLOBAL PORTS ----- +input [0:0] RST; +//----- GLOBAL PORTS ----- +input [0:0] CK; +//----- INPUT PORTS ----- +input [0:0] D; +//----- OUTPUT PORTS ----- +output reg [0:0] Q; +output reg [0:0] QN; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Internal logic should start here ----- +always @(posedge CK) begin + if(RST) begin + Q <= 1'b0; + QN <= 1'b1; + end else begin + Q <= D; + QN <= ~D; + end +end + +// ----- Internal logic should end here ----- +endmodule diff --git a/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v b/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v new file mode 100644 index 000000000..c466740c6 --- /dev/null +++ b/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v @@ -0,0 +1,36 @@ +module DFFSRQ(SET, + RST, + CK, + D, + Q); +//----- GLOBAL PORTS ----- +input [0:0] SET; +//----- GLOBAL PORTS ----- +input [0:0] RST; +//----- GLOBAL PORTS ----- +input [0:0] CK; +//----- INPUT PORTS ----- +input [0:0] D; +//----- OUTPUT PORTS ----- +output reg [0:0] Q; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Internal logic should start here ----- +always @(posedge CK) begin + if(RST) begin + Q <= 1'b0; + else if(SET) begin + Q <= 1'b1; + end else begin + Q <= D; + end +end + +// ----- Internal logic should end here ----- +endmodule diff --git a/openfpga_flow/openfpga_cell_library/verilog/inv.v b/openfpga_flow/openfpga_cell_library/verilog/inv.v new file mode 100644 index 000000000..cb208248f --- /dev/null +++ b/openfpga_flow/openfpga_cell_library/verilog/inv.v @@ -0,0 +1,29 @@ +// ----- Verilog module for INVTX1 ----- +module INVTX1(in, + out); +//----- INPUT PORTS ----- +input [0:0] in; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Verilog codes of a regular inverter ----- + //assign out = (in === 1'bz)? $random : ~in; + assign out = ~in; + +`ifdef ENABLE_TIMING +// ------ BEGIN Pin-to-pin Timing constraints ----- + specify + (in[0] => out[0]) = (0.01, 0.01); + endspecify +// ------ END Pin-to-pin Timing constraints ----- +`endif +endmodule +// ----- END Verilog module for INVTX1 ----- +