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[engine] Use RRGraphView in openfpga source codes

This commit is contained in:
tangxifan 2022-08-16 16:48:32 -07:00
parent 9b3e358440
commit 0c329866da
23 changed files with 82 additions and 82 deletions
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2
openfpga/src/annotation/annotate_routing.cpp
View File

@ -60,7 +60,7 @@ void annotate_rr_node_nets(const DeviceContext& device_ctx,
* If not validated, try to find a right one in the routing traces
*******************************************************************/
static
RRNodeId find_previous_node_from_routing_traces(const RRGraph& rr_graph,
RRNodeId find_previous_node_from_routing_traces(const RRGraphView& rr_graph,
t_trace* routing_trace_head,
const RRNodeId& prev_node_candidate,
const RRNodeId& cur_rr_node) {

2
openfpga/src/annotation/annotate_rr_graph.cpp
View File

@ -445,7 +445,7 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx,
* Sort all the incoming edges for each channel node which are
* output ports of the GSB
*******************************************************************/
void sort_device_rr_gsb_chan_node_in_edges(const RRGraph& rr_graph,
void sort_device_rr_gsb_chan_node_in_edges(const RRGraphView& rr_graph,
DeviceRRGSB& device_rr_gsb,
const bool& verbose_output) {
vtr::ScopedStartFinishTimer timer("Sort incoming edges for each routing track output node of General Switch Block(GSB)");

2
openfpga/src/annotation/annotate_rr_graph.h
View File

@ -19,7 +19,7 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx,
DeviceRRGSB& device_rr_gsb,
const bool& verbose_output);
void sort_device_rr_gsb_chan_node_in_edges(const RRGraph& rr_graph,
void sort_device_rr_gsb_chan_node_in_edges(const RRGraphView& rr_graph,
DeviceRRGSB& device_rr_gsb,
const bool& verbose_output);

6
openfpga/src/annotation/device_rr_gsb.cpp
View File

@ -213,7 +213,7 @@ RRGSB& DeviceRRGSB::get_mutable_gsb(const size_t& x, const size_t& y) {
}
/* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void DeviceRRGSB::build_cb_unique_module(const RRGraph& rr_graph, const t_rr_type& cb_type) {
void DeviceRRGSB::build_cb_unique_module(const RRGraphView& rr_graph, const t_rr_type& cb_type) {
/* Make sure a clean start */
clear_cb_unique_module(cb_type);
@ -249,7 +249,7 @@ void DeviceRRGSB::build_cb_unique_module(const RRGraph& rr_graph, const t_rr_typ
}
/* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void DeviceRRGSB::build_sb_unique_module(const RRGraph& rr_graph) {
void DeviceRRGSB::build_sb_unique_module(const RRGraphView& rr_graph) {
/* Make sure a clean start */
clear_sb_unique_module();
@ -323,7 +323,7 @@ void DeviceRRGSB::build_gsb_unique_module() {
}
}
void DeviceRRGSB::build_unique_module(const RRGraph& rr_graph) {
void DeviceRRGSB::build_unique_module(const RRGraphView& rr_graph) {
build_sb_unique_module(rr_graph);
build_cb_unique_module(rr_graph, CHANX);

8
openfpga/src/annotation/device_rr_gsb.h
View File

@ -8,7 +8,7 @@
#include "vtr_geometry.h"
/* Header files from vpr library */
#include "rr_graph_obj.h"
#include "rr_graph_view.h"
#include "rr_gsb.h"
@ -46,7 +46,7 @@ class DeviceRRGSB {
void add_rr_gsb(const vtr::Point<size_t>& coordinate, const RRGSB& rr_gsb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
RRGSB& get_mutable_gsb(const vtr::Point<size_t>& coordinate); /* Get a rr switch block in the array with a coordinate */
RRGSB& get_mutable_gsb(const size_t& x, const size_t& y); /* Get a rr switch block in the array with a coordinate */
void build_unique_module(const RRGraph& rr_graph); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void build_unique_module(const RRGraphView& rr_graph); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void clear(); /* clean the content */
private: /* Internal cleaners */
void clear_gsb(); /* clean the content */
@ -67,8 +67,8 @@ class DeviceRRGSB {
void add_gsb_unique_module(const vtr::Point<size_t>& coordinate);
void add_cb_unique_module(const t_rr_type& cb_type, const vtr::Point<size_t>& coordinate);
void set_cb_unique_module_id(const t_rr_type& cb_type, const vtr::Point<size_t>& coordinate, size_t id);
void build_sb_unique_module(const RRGraph& rr_graph); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void build_cb_unique_module(const RRGraph& rr_graph, const t_rr_type& cb_type); /* Add a switch block to the array, which will automatically identify and update the lists of unique side module */
void build_sb_unique_module(const RRGraphView& rr_graph); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
void build_cb_unique_module(const RRGraphView& rr_graph, const t_rr_type& cb_type); /* Add a switch block to the array, which will automatically identify and update the lists of unique side module */
void build_gsb_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
private: /* Internal Data */
std::vector<std::vector<RRGSB>> rr_gsb_;

8
openfpga/src/annotation/write_xml_device_rr_gsb.cpp
View File

@ -24,7 +24,7 @@ namespace openfpga {
***************************************************************************************/
static
void write_rr_gsb_ipin_connection_to_xml(std::fstream& fp,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const enum e_side& gsb_side) {
/* Validate the file stream */
@ -83,7 +83,7 @@ static
void write_rr_gsb_chan_connection_to_xml(std::fstream& fp,
const DeviceGrid& vpr_device_grid,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const enum e_side& gsb_side) {
/* Validate the file stream */
@ -180,7 +180,7 @@ static
void write_rr_switch_block_to_xml(const std::string fname_prefix,
const DeviceGrid& vpr_device_grid,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const bool& verbose) {
/* Prepare file name */
@ -231,7 +231,7 @@ void write_rr_switch_block_to_xml(const std::string fname_prefix,
void write_device_rr_gsb_to_xml(const char* sb_xml_dir,
const DeviceGrid& vpr_device_grid,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& unique,
const bool& verbose) {

2
openfpga/src/annotation/write_xml_device_rr_gsb.h
View File

@ -20,7 +20,7 @@ namespace openfpga {
void write_device_rr_gsb_to_xml(const char* sb_xml_dir,
const DeviceGrid& vpr_device_grid,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& unique,
const bool& verbose);

2
openfpga/src/base/openfpga_link_arch.cpp
View File

@ -41,7 +41,7 @@ namespace openfpga {
* It means every routing tracks must have a direction
*******************************************************************/
static
bool is_vpr_rr_graph_supported(const RRGraph& rr_graph) {
bool is_vpr_rr_graph_supported(const RRGraphView& rr_graph) {
/* Check if the rr_graph is uni-directional*/
for (const RRNodeId& node : rr_graph.nodes()) {
if (CHANX != rr_graph.node_type(node) && CHANY != rr_graph.node_type(node)) {

16
openfpga/src/fabric/build_routing_module_utils.cpp
View File

@ -64,7 +64,7 @@ std::string generate_sb_module_grid_port_name(const e_side& sb_side,
const e_side& grid_side,
const DeviceGrid& vpr_device_grid,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRNodeId& rr_node) {
SideManager sb_side_manager(sb_side);
SideManager grid_side_manager(grid_side);
@ -95,7 +95,7 @@ std::string generate_sb_module_grid_port_name(const e_side& sb_side,
std::string generate_cb_module_grid_port_name(const e_side& cb_side,
const DeviceGrid& vpr_device_grid,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRNodeId& rr_node) {
SideManager side_manager(cb_side);
@ -122,7 +122,7 @@ std::string generate_cb_module_grid_port_name(const e_side& cb_side,
********************************************************************/
ModulePinInfo find_switch_block_module_chan_port(const ModuleManager& module_manager,
const ModuleId& sb_module,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const e_side& chan_side,
const RRNodeId& cur_rr_node,
@ -165,7 +165,7 @@ ModulePinInfo find_switch_block_module_input_port(const ModuleManager& module_ma
const ModuleId& sb_module,
const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const e_side& input_side,
const RRNodeId& input_rr_node) {
@ -215,7 +215,7 @@ std::vector<ModulePinInfo> find_switch_block_module_input_ports(const ModuleMana
const ModuleId& sb_module,
const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const std::vector<RRNodeId>& input_rr_nodes) {
std::vector<ModulePinInfo> input_ports;
@ -241,7 +241,7 @@ std::vector<ModulePinInfo> find_switch_block_module_input_ports(const ModuleMana
********************************************************************/
ModulePinInfo find_connection_block_module_chan_port(const ModuleManager& module_manager,
const ModuleId& cb_module,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const RRNodeId& chan_rr_node) {
@ -277,7 +277,7 @@ ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_
const ModuleId& cb_module,
const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const RRNodeId& src_rr_node) {
@ -309,7 +309,7 @@ ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_
********************************************************************/
std::vector<ModulePinInfo> find_connection_block_module_input_ports(const ModuleManager& module_manager,
const ModuleId& cb_module,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const std::vector<RRNodeId>& input_rr_nodes) {

16
openfpga/src/fabric/build_routing_module_utils.h
View File

@ -26,18 +26,18 @@ std::string generate_sb_module_grid_port_name(const e_side& sb_side,
const e_side& grid_side,
const DeviceGrid& vpr_device_grid,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRNodeId& rr_node);
std::string generate_cb_module_grid_port_name(const e_side& cb_side,
const DeviceGrid& vpr_device_grid,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRNodeId& rr_node);
ModulePinInfo find_switch_block_module_chan_port(const ModuleManager& module_manager,
const ModuleId& sb_module,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const e_side& chan_side,
const RRNodeId& cur_rr_node,
@ -47,7 +47,7 @@ ModulePinInfo find_switch_block_module_input_port(const ModuleManager& module_ma
const ModuleId& sb_module,
const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const e_side& input_side,
const RRNodeId& input_rr_node);
@ -56,13 +56,13 @@ std::vector<ModulePinInfo> find_switch_block_module_input_ports(const ModuleMana
const ModuleId& sb_module,
const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const std::vector<RRNodeId>& input_rr_nodes);
ModulePinInfo find_connection_block_module_chan_port(const ModuleManager& module_manager,
const ModuleId& cb_module,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const RRNodeId& chan_rr_node);
@ -71,13 +71,13 @@ ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_
const ModuleId& cb_module,
const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const RRNodeId& src_rr_node);
std::vector<ModulePinInfo> find_connection_block_module_input_ports(const ModuleManager& module_manager,
const ModuleId& cb_module,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const std::vector<RRNodeId>& input_rr_nodes);

16
openfpga/src/fabric/build_routing_modules.cpp
View File

@ -44,7 +44,7 @@ void build_switch_block_module_short_interc(ModuleManager& module_manager,
const ModuleId& sb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const e_side& chan_side,
const RRNodeId& cur_rr_node,
@ -105,7 +105,7 @@ void build_switch_block_mux_module(ModuleManager& module_manager,
const ModuleId& sb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const CircuitLibrary& circuit_lib,
const e_side& chan_side,
@ -215,7 +215,7 @@ void build_switch_block_interc_modules(ModuleManager& module_manager,
const ModuleId& sb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const CircuitLibrary& circuit_lib,
const e_side& chan_side,
@ -337,7 +337,7 @@ void build_switch_block_module(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
const CircuitModelId& sram_model,
@ -485,7 +485,7 @@ void build_connection_block_module_short_interc(ModuleManager& module_manager,
const ModuleId& cb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const RRNodeId& src_rr_node,
@ -546,7 +546,7 @@ void build_connection_block_mux_module(ModuleManager& module_manager,
const ModuleId& cb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const CircuitLibrary& circuit_lib,
@ -660,7 +660,7 @@ void build_connection_block_interc_modules(ModuleManager& module_manager,
const ModuleId& cb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const CircuitLibrary& circuit_lib,
@ -745,7 +745,7 @@ void build_connection_block_module(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
const CircuitModelId& sram_model,

2
openfpga/src/fabric/build_top_module.cpp
View File

@ -289,7 +289,7 @@ int build_top_module(ModuleManager& module_manager,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,
const TileAnnotation& tile_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const TileDirect& tile_direct,
const ArchDirect& arch_direct,

4
openfpga/src/fabric/build_top_module.h
View File

@ -10,7 +10,7 @@
#include "device_grid.h"
#include "vpr_device_annotation.h"
#include "tile_annotation.h"
#include "rr_graph_obj.h"
#include "rr_graph_view.h"
#include "device_rr_gsb.h"
#include "circuit_library.h"
#include "decoder_library.h"
@ -35,7 +35,7 @@ int build_top_module(ModuleManager& module_manager,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,
const TileAnnotation& tile_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const TileDirect& tile_direct,
const ArchDirect& arch_direct,

10
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -68,7 +68,7 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,
const vtr::Matrix<size_t>& grid_instance_ids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const RRGSB& rr_gsb,
const vtr::Matrix<size_t>& sb_instance_ids,
@ -197,7 +197,7 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,
const vtr::Matrix<size_t>& grid_instance_ids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const RRGSB& rr_gsb,
const vtr::Matrix<size_t>& sb_instance_ids,
@ -369,7 +369,7 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,
const vtr::Matrix<size_t>& grid_instance_ids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
@ -508,7 +508,7 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager,
static
void add_top_module_nets_connect_sb_and_cb(ModuleManager& module_manager,
const ModuleId& top_module,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const RRGSB& rr_gsb,
const vtr::Matrix<size_t>& sb_instance_ids,
@ -673,7 +673,7 @@ void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,
const vtr::Matrix<size_t>& grid_instance_ids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const vtr::Matrix<size_t>& sb_instance_ids,
const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,

4
openfpga/src/fabric/build_top_module_connection.h
View File

@ -8,7 +8,7 @@
#include "vtr_geometry.h"
#include "vtr_ndmatrix.h"
#include "device_grid.h"
#include "rr_graph_obj.h"
#include "rr_graph_view.h"
#include "device_rr_gsb.h"
#include "tile_annotation.h"
#include "vpr_device_annotation.h"
@ -26,7 +26,7 @@ void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,
const vtr::Matrix<size_t>& grid_instance_ids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const vtr::Matrix<size_t>& sb_instance_ids,
const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,

16
openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
View File

@ -39,7 +39,7 @@ void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager,
const ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRNodeId& cur_rr_node,
const std::vector<RRNodeId>& drive_rr_nodes,
const AtomContext& atom_ctx,
@ -145,7 +145,7 @@ void build_switch_block_interc_bitstream(BitstreamManager& bitstream_manager,
const ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const AtomContext& atom_ctx,
const VprDeviceAnnotation& device_annotation,
const VprRoutingAnnotation& routing_annotation,
@ -204,7 +204,7 @@ void build_switch_block_bitstream(BitstreamManager& bitstream_manager,
const AtomContext& atom_ctx,
const VprDeviceAnnotation& device_annotation,
const VprRoutingAnnotation& routing_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb) {
/* Iterate over all the multiplexers */
@ -242,7 +242,7 @@ void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager,
const AtomContext& atom_ctx,
const VprDeviceAnnotation& device_annotation,
const VprRoutingAnnotation& routing_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRNodeId& src_rr_node) {
/* Find drive_rr_nodes*/
@ -350,7 +350,7 @@ void build_connection_block_interc_bitstream(BitstreamManager& bitstream_manager
const AtomContext& atom_ctx,
const VprDeviceAnnotation& device_annotation,
const VprRoutingAnnotation& routing_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const e_side& cb_ipin_side,
const size_t& ipin_index) {
@ -395,7 +395,7 @@ void build_connection_block_bitstream(BitstreamManager& bitstream_manager,
const AtomContext& atom_ctx,
const VprDeviceAnnotation& device_annotation,
const VprRoutingAnnotation& routing_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type) {
@ -427,7 +427,7 @@ void build_connection_block_bitstreams(BitstreamManager& bitstream_manager,
const AtomContext& atom_ctx,
const VprDeviceAnnotation& device_annotation,
const VprRoutingAnnotation& routing_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& compact_routing_hierarchy,
const t_rr_type& cb_type) {
@ -500,7 +500,7 @@ void build_routing_bitstream(BitstreamManager& bitstream_manager,
const AtomContext& atom_ctx,
const VprDeviceAnnotation& device_annotation,
const VprRoutingAnnotation& routing_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& compact_routing_hierarchy) {

2
openfpga/src/fpga_bitstream/build_routing_bitstream.h
View File

@ -32,7 +32,7 @@ void build_routing_bitstream(BitstreamManager& bitstream_manager,
const AtomContext& atom_ctx,
const VprDeviceAnnotation& device_annotation,
const VprRoutingAnnotation& routing_annotation,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& compact_routing_hierarchy);

10
openfpga/src/fpga_sdc/analysis_sdc_routing_writer.cpp
View File

@ -36,7 +36,7 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,
const RRGSB& rr_gsb,
@ -222,7 +222,7 @@ void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,
const t_rr_type& cb_type,
@ -265,7 +265,7 @@ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,
const bool& compact_routing_hierarchy) {
@ -301,7 +301,7 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,
const RRGSB& rr_gsb,
@ -547,7 +547,7 @@ void print_analysis_sdc_disable_unused_sbs(std::fstream& fp,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,
const bool& compact_routing_hierarchy) {

4
openfpga/src/fpga_sdc/analysis_sdc_routing_writer.h
View File

@ -24,7 +24,7 @@ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,
const bool& compact_routing_hierarchy);
@ -34,7 +34,7 @@ void print_analysis_sdc_disable_unused_sbs(std::fstream& fp,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,
const bool& compact_routing_hierarchy);

18
openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
View File

@ -57,7 +57,7 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
const ModuleId& sb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const e_side& output_node_side,
const RRNodeId& output_rr_node,
@ -147,7 +147,7 @@ void print_pnr_sdc_constrain_sb_timing(const PnrSdcOption& options,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb) {
std::string sdc_dir = options.sdc_dir();
float time_unit = options.time_unit();
@ -219,7 +219,7 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const PnrSdcOption& optio
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb) {
/* Start time count */
@ -265,7 +265,7 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const PnrSdcOption& optio
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb) {
/* Start time count */
@ -313,7 +313,7 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
const ModuleId& cb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const RRNodeId& output_rr_node,
@ -417,7 +417,7 @@ void print_pnr_sdc_constrain_cb_timing(const PnrSdcOption& options,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type) {
std::string sdc_dir = options.sdc_dir();
@ -540,7 +540,7 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const PnrSdcOption& optio
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const t_rr_type& cb_type) {
/* Build unique X-direction connection block modules */
@ -591,7 +591,7 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const PnrSdcOption& optio
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb) {
/* Start time count */
@ -623,7 +623,7 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const PnrSdcOption& optio
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb) {
/* Start time count */

10
openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h
View File

@ -8,7 +8,7 @@
#include <vector>
#include "module_manager.h"
#include "device_rr_gsb.h"
#include "rr_graph_obj.h"
#include "rr_graph_view.h"
#include "device_grid.h"
#include "vpr_device_annotation.h"
#include "pnr_sdc_option.h"
@ -25,7 +25,7 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const PnrSdcOption& optio
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb);
void print_pnr_sdc_compact_routing_constrain_sb_timing(const PnrSdcOption& options,
@ -33,7 +33,7 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const PnrSdcOption& optio
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb);
void print_pnr_sdc_flatten_routing_constrain_cb_timing(const PnrSdcOption& options,
@ -41,7 +41,7 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const PnrSdcOption& optio
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb);
void print_pnr_sdc_compact_routing_constrain_cb_timing(const PnrSdcOption& options,
@ -49,7 +49,7 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const PnrSdcOption& optio
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb);
} /* end namespace openfpga */

2
openfpga/src/utils/rr_gsb_utils.cpp
View File

@ -39,7 +39,7 @@ bool connection_block_contain_only_routing_tracks(const RRGSB& rr_gsb,
/************************************************************************
* Find the configurable driver nodes for a node in the rr_graph
***********************************************************************/
std::vector<RRNodeId> get_rr_gsb_chan_node_configurable_driver_nodes(const RRGraph& rr_graph,
std::vector<RRNodeId> get_rr_gsb_chan_node_configurable_driver_nodes(const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const e_side& chan_side,
const size_t& track_id) {

2
openfpga/src/utils/rr_gsb_utils.h
View File

@ -18,7 +18,7 @@ namespace openfpga {
bool connection_block_contain_only_routing_tracks(const RRGSB& rr_gsb,
const t_rr_type& cb_type);
std::vector<RRNodeId> get_rr_gsb_chan_node_configurable_driver_nodes(const RRGraph& rr_graph,
std::vector<RRNodeId> get_rr_gsb_chan_node_configurable_driver_nodes(const RRGraphViewView& rr_graph,
const RRGSB& rr_gsb,
const e_side& chan_side,
const size_t& track_id);