From 0c2ad5ab5e1c5317ae166d2e1f07edc46c0700dc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 13 Nov 2019 20:45:41 -0700 Subject: [PATCH] critical bug fixed for some corner cases --- .../backend_assistant/analysis_sdc_grid_writer.cpp | 5 +++++ .../backend_assistant/pnr_sdc_routing_writer.cpp | 10 ++++++++++ .../fpga_x2p/module_builder/build_routing_modules.cpp | 2 +- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c | 6 +++++- 4 files changed, 21 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp index 235e99bee..9eac8c52a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp @@ -278,6 +278,11 @@ void disable_pb_graph_node_unused_mux_inputs(std::fstream& fp, int rr_node_index = child_pb_graph_node->output_pins[iport][ipin].rr_node_index_physical_pb; t_rr_node* output_rr_node = &(block_physical_pb->rr_graph->rr_node[rr_node_index]); + /* Corner case: if the rr node has no fan-out we will skip this pin */ + if (0 == output_rr_node->num_edges) { + continue; + } + disable_analysis_module_output_pin_net_sinks(fp, module_manager, parent_module, hierarchy_name, child_module, inst, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp index 13bc17d1c..1efc9279c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp @@ -237,6 +237,15 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp, check_file_handler(fp); VTR_ASSERT(IPIN == output_rr_node->type); + + /* We have OPINs since we may have direct connections: + * These connections should be handled by other functions in the compact_netlist.c + * So we just return here for OPINs + */ + if ( (1 == output_rr_node->num_drive_rr_nodes) + && (OPIN == output_rr_node->drive_rr_nodes[0]->type) ) { + return; + } /* Find the module port corresponding to the output rr_node */ ModulePortId module_output_port = find_connection_block_module_ipin_port(module_manager, @@ -247,6 +256,7 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp, /* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */ std::vector input_rr_nodes; for (int iedge = 0; iedge < output_rr_node->num_drive_rr_nodes; iedge++) { + /* Skip OPINs which should be handled in direct connection */ input_rr_nodes.push_back(output_rr_node->drive_rr_nodes[iedge]); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp index b43baa0f4..fcd0f93d2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp @@ -446,7 +446,7 @@ void build_connection_block_module_short_interc(ModuleManager& module_manager, /* Ensure we have only one 1 driver node */ VTR_ASSERT_SAFE(1 == src_rr_node->fan_in); - /* Find the driver node */ + /* Find the driver node */ t_rr_node* drive_rr_node = src_rr_node->drive_rr_nodes[0]; /* We have OPINs since we may have direct connections: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 57e742fe7..9047cb473 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -515,9 +515,13 @@ void vpr_fpga_verilog(ModuleManager& module_manager, } /* Print a Verilog file including all the netlists that have been generated */ + std::string ref_verilog_benchmark_file_name; + if (NULL != vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.reference_verilog_benchmark_file) { + ref_verilog_benchmark_file_name = std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.reference_verilog_benchmark_file); + } print_include_netlists(std::string(src_dir_path), std::string(chomped_circuit_name), - std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.reference_verilog_benchmark_file), + ref_verilog_benchmark_file_name, Arch.spice->circuit_lib); vpr_printf(TIO_MESSAGE_INFO, "Outputted %lu Verilog modules in total.\n", module_manager.num_modules());