Merge pull request #167 from lnis-uofu/dev
Support on Using Scan-chain Flip-flop in Configuration Chain
This commit is contained in:
tangxifan
GitHub
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0bb1f92ed8
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@ -14,6 +14,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/config
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set_reset --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set_reset --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_config_enable_scff --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_configuration_chain --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_configuration_chain --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs
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@ -979,18 +979,18 @@ This example shows:
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.. _circuit_model_ccff_example:
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.. _circuit_model_ccff_example:
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Configuration-chain Flip-flop
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Regular Configuration-chain Flip-flop
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`````````````````````````````
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`````````````````````````````````````
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:numref:`fig_ccff` illustrates an example of scan-chain flop-flop used to build a configuration chain.
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:numref:`fig_ccff_config_chain` illustrates an example of standard flip-flops used to build a configuration chain.
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.. _fig_ccff:
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.. _fig_ccff_config_chain:
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.. figure:: ./figures/scff.png
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.. figure:: ./figures/config_chain.svg
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:scale: 50%
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:scale: 50%
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:alt: SCFF symbol
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:alt: SCFF symbol
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An example of a Scan-Chain Flip-Flop.
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An example of a Flip-Flop organized in a chain.
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The code describing this FF is:
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The code describing this FF is:
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@ -999,14 +999,94 @@ The code describing this FF is:
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<circuit_model type="ccff" name="ccff" prefix="ccff" verilog_netlist="ccff.v" spice_netlist="ccff.sp">
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<circuit_model type="ccff" name="ccff" prefix="ccff" verilog_netlist="ccff.v" spice_netlist="ccff.sp">
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="output" prefix="Qb" size="1"/>
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<port type="output" prefix="QN" size="1"/>
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<port type="clock" prefix="CK" size="1" is_global="true"/>
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<port type="clock" prefix="CK" size="1" is_global="true" is_prog="true" is_clock="true"/>
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</circuit_model>
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</circuit_model>
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This example shows:
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This example shows:
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- A configuration-chain flip-flop which is defined in a Verilog netlist ``ccff.v`` and a SPICE netlist ``ccff.sp``
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- A configuration-chain flip-flop which is defined in a Verilog netlist ``ccff.v`` and a SPICE netlist ``ccff.sp``
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- The flip-flop has a global clock port, ``CK``, which will be wired a global programming clock
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- The flip-flop has a global clock port, ``CK``, which will be wired a global programming clock
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.. note::
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The output ports of the configuration flip-flop must follow a fixed sequence in definition:
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- The first output port **MUST** be the data output port, e.g., ``Q``.
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- The second output port **MUST** be the **inverted** data output port, e.g., ``QN``.
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Configuration-chain Flip-flop with Configure Enable Signals
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```````````````````````````````````````````````````````````
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Configuration chain could be built with flip-flops with outputs that are enabled by specific signals.
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Consider the example in :numref:`fig_ccff_config_chain_config_enable`, the flip-flop has
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- a configure enable signal ``CFG_EN`` to release the data output ``Q`` and ``QN``
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- a pair of data outputs ``Q`` and ``QN`` which are controlled by the configure enable signal ``CFG_EN``
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- a regular data output ``SCAN_Q`` which outputs registered data
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.. _fig_ccff_config_chain_config_enable:
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.. figure:: ./figures/config_chain_config_enable.svg
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:scale: 50%
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:alt: SCFF symbol
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An example of a Flip-Flop with config enable feature organized in a chain.
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The code describing this FF is:
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.. code-block:: xml
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<circuit_model type="ccff" name="ccff" prefix="ccff" verilog_netlist="ccff.v" spice_netlist="ccff.sp">
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<port type="input" prefix="CFG_EN" size="1" is_global="true" is_config_enable="true"/>
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<port type="input" prefix="D" size="1"/>
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<port type="output" prefix="SCAN_Q" size="1"/>
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<port type="output" prefix="QN" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="CK" size="1" is_global="true" is_prog="true" is_clock="true"/>
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</circuit_model>
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.. note::
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The output ports of the configuration flip-flop must follow a fixed sequence in definition:
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- The first output port **MUST** be the regular data output port, e.g., ``SCAN_Q``.
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- The second output port **MUST** be the **inverted** data output port which is activated by the configure enable signal, e.g., ``QN``.
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- The second output port **MUST** be the data output port which is activated by the configure enable signal, e.g., ``Q``.
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Configuration-chain Flip-flop with Scan Input
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`````````````````````````````````````````````
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Configuration chain could be built with flip-flops with a scan chain input .
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Consider the example in :numref:`fig_ccff_config_chain_scan_capable`, the flip-flop has
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- an additional input ``SI`` to enable scan-chain capabaility
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- a configure enable signal ``CFG_EN`` to release the data output ``Q`` and ``QN``
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- a pair of data outputs ``Q`` and ``QN`` which are controlled by the configure enable signal ``CFG_EN``
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- a regular data output ``SCAN_Q`` which outputs registered data
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.. _fig_ccff_config_chain_scan_capable:
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.. figure:: ./figures/config_chain_scan_capable.svg
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:scale: 50%
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:alt: SCFF symbol
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An example of a Flip-Flop with scan input organized in a chain.
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The code describing this FF is:
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.. code-block:: xml
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<circuit_model type="ccff" name="ccff" prefix="ccff" verilog_netlist="ccff.v" spice_netlist="ccff.sp">
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<port type="input" prefix="CFG_EN" size="1" is_global="true" is_config_enable="true"/>
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="SI" size="1"/>
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<port type="output" prefix="SCAN_Q" size="1"/>
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<port type="output" prefix="QN" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="CK" size="1" is_global="true" is_prog="true" is_clock="true"/>
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</circuit_model>
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.. note::
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The input ports of the configuration flip-flop must follow a fixed sequence in definition:
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- The first input port **MUST** be the regular data input port, e.g., ``D``.
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- The second input port **MUST** be the scan input port, e.g., ``SI``.
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Hard Logics
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Hard Logics
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~~~~~~~~~~~
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~~~~~~~~~~~
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@ -0,0 +1,375 @@
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<tspan font-family="Times New Roman" font-size="9" font-style="italic" font-weight="400" fill="black" x="0" y="8">Q</tspan>
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<g id="Graphic_35828">
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_out[0]</tspan>
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</text>
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<g id="Graphic_35852">
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_outb[0]</tspan>
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</text>
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<g id="Graphic_35853">
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_out[1]</tspan>
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|
</text>
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<g id="Graphic_35854">
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_outb[1]</tspan>
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</text>
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</g>
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|
<g id="Graphic_35856">
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_out[2]</tspan>
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</text>
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<g id="Graphic_35855">
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_outb[2]</tspan>
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|
</text>
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|
</g>
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|
<g id="Graphic_35858">
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_out[n]</tspan>
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</text>
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<g id="Graphic_35857">
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_outb[n]</tspan>
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|
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|
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">CLK</tspan>
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<tspan font-family="Times New Roman" font-size="14" font-style="italic" font-weight="400" fill="black" x="0" y="12">…</tspan>
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<ellipse cx="417.7701" cy="419.80915" rx="2.47010548958708" ry="2.52000397038635" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_outb[0]</tspan>
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</g>
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<g id="Graphic_35853">
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_out[1]</tspan>
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|
</text>
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<g id="Graphic_35854">
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_outb[1]</tspan>
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|
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</g>
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<g id="Graphic_35856">
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_out[2]</tspan>
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|
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</g>
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<g id="Graphic_35855">
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_outb[2]</tspan>
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<g id="Graphic_35858">
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_out[n]</tspan>
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|
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<g id="Graphic_35857">
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_outb[n]</tspan>
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<tspan font-family="Times New Roman" font-size="14" font-weight="400" fill="black" x="11.595982" y="12">CCFF</tspan>
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<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">D</tspan>
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|
<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">SCAN_Q</tspan>
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|
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|
</g>
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|
<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">QN</tspan>
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|
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|
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|
<g id="Graphic_35860">
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<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">Q</tspan>
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|
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|
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|
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<tspan font-family="Times New Roman" font-size="14" font-weight="400" fill="black" x="11.595982" y="12">CCFF</tspan>
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<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">D</tspan>
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|
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</g>
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|
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|
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|
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<tspan font-family="Times New Roman" font-size="14" font-style="italic" font-weight="400" fill="black" x="0" y="12">…</tspan>
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|
<ellipse cx="417.7701" cy="419.80915" rx="2.47010548958708" ry="2.52000397038635" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">CCFF_TAIL</tspan>
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_out[0]</tspan>
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_outb[0]</tspan>
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</text>
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|
<g id="Graphic_35853">
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_out[1]</tspan>
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<g id="Graphic_35854">
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_outb[1]</tspan>
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</g>
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<g id="Graphic_35856">
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_out[2]</tspan>
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|
<g id="Graphic_35855">
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<text transform="translate(486.68 430.88)" fill="black">
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_outb[2]</tspan>
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|
</text>
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|
</g>
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|
<g id="Graphic_35858">
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|
<text transform="translate(606.2 446.72)" fill="black">
|
||||||
|
<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_out[n]</tspan>
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|
</text>
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|
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|
<g id="Graphic_35857">
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<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">mem_outb[n]</tspan>
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|
</text>
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|
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|
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<g id="Graphic_35772">
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<text transform="translate(181.97979 368.86263)" fill="black">
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|
<tspan font-family="Times New Roman" font-size="14" font-weight="400" fill="black" x="11.595982" y="12">CCFF</tspan>
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</g>
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<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">D</tspan>
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|
</text>
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</g>
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|
<g id="Graphic_35776">
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<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">CLK</tspan>
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</g>
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<path d="M 176.97979 388.91704 L 184.53979 392.99704 L 176.97979 397.07704 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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</g>
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<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">SCAN_Q</tspan>
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|
</text>
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</g>
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<g id="Graphic_35859">
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|
<text transform="translate(226.63794 395.36767)" fill="black">
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|
<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">QN</tspan>
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|
</text>
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|
</g>
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|
<g id="Graphic_35860">
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<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">Q</tspan>
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|
</text>
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|
</g>
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|
</g>
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</g>
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<tspan font-family="Times New Roman" font-size="14" font-weight="400" fill="black" x="11.595982" y="12">CCFF</tspan>
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</g>
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<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">D</tspan>
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</text>
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</g>
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<g id="Graphic_35872">
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<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">CLK</tspan>
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|
</text>
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</g>
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</g>
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</g>
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<g id="Graphic_35868">
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<path d="M 306.9398 388.91704 L 314.4998 392.99704 L 306.9398 397.07704 Z" fill="#ccc"/>
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<path d="M 306.9398 388.91704 L 314.4998 392.99704 L 306.9398 397.07704 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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</g>
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<text transform="translate(337.92647 358.26883)" fill="black">
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|
<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">SCAN_Q</tspan>
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|
</text>
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|
</g>
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|
<g id="Graphic_35866">
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<text transform="translate(356.59794 395.36767)" fill="black">
|
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|
<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">QN</tspan>
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|
</text>
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|
</g>
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|
<g id="Graphic_35865">
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|
<text transform="translate(344.88 395.61767)" fill="black">
|
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|
<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">Q</tspan>
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|
</text>
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|
</g>
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|
</g>
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</g>
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<tspan font-family="Times New Roman" font-size="14" font-weight="400" fill="black" x="11.595982" y="12">CCFF</tspan>
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</text>
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</g>
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<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">D</tspan>
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|
</text>
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</g>
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<g id="Graphic_35885">
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<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">CLK</tspan>
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|
</text>
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</g>
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</g>
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</g>
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</g>
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|
<g id="Graphic_35881">
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<path d="M 430.7424 388.66704 L 438.3024 392.74704 L 430.7424 396.82704 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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</g>
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<g id="Graphic_35880">
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<text transform="translate(461.7291 358.01883)" fill="black">
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|
<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">SCAN_Q</tspan>
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|
</text>
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|
</g>
|
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|
<g id="Graphic_35879">
|
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|
<text transform="translate(480.40056 395.11767)" fill="black">
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|
<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">QN</tspan>
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|
</text>
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|
</g>
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|
<g id="Graphic_35878">
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|
<text transform="translate(468.6826 395.36767)" fill="black">
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|
<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">Q</tspan>
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|
</text>
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|
</g>
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|
</g>
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|
</g>
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<g id="Group_35889">
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<g id="Graphic_35899">
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<rect x="593.3428" y="347.07" width="67.44001" height="58.68" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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<tspan font-family="Times New Roman" font-size="14" font-weight="400" fill="black" x="11.595982" y="12">CCFF</tspan>
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</g>
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<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">D</tspan>
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</text>
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</g>
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<g id="Graphic_35897">
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<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">CLK</tspan>
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</g>
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</g>
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<path d="M 593.3428 388.66704 L 600.9028 392.74704 L 593.3428 396.82704 Z" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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</g>
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<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">SCAN_Q</tspan>
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</text>
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</g>
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<g id="Graphic_35891">
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||||||
|
<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">QN</tspan>
|
||||||
|
</text>
|
||||||
|
</g>
|
||||||
|
<g id="Graphic_35890">
|
||||||
|
<text transform="translate(631.283 395.36767)" fill="black">
|
||||||
|
<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">Q</tspan>
|
||||||
|
</text>
|
||||||
|
</g>
|
||||||
|
</g>
|
||||||
|
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|
</g>
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||||||
|
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|
<line x1="365.24055" y1="406" x2="365.24055" y2="432.84513" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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</g>
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||||||
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|
<line x1="471.725" y1="405.73076" x2="471.7103" y2="447.48" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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</g>
|
||||||
|
<g id="Line_35902">
|
||||||
|
<line x1="488.645" y1="405.55665" x2="488.645" y2="432.4018" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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</g>
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||||||
|
<g id="Line_35905">
|
||||||
|
<line x1="635.885" y1="406.47363" x2="635.8709" y2="441.72" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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|
</g>
|
||||||
|
<g id="Line_35904">
|
||||||
|
<line x1="652.805" y1="406.29953" x2="652.805" y2="433.14467" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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||||||
|
</g>
|
||||||
|
<g id="Line_35906">
|
||||||
|
<line x1="417.9226" y1="393.48" x2="417.9226" y2="419.46915" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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|
</g>
|
||||||
|
<g id="Line_35907">
|
||||||
|
<line x1="294.12" y1="392.51084" x2="294.0757" y2="416.40256" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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|
</g>
|
||||||
|
<g id="Graphic_35909">
|
||||||
|
<text transform="translate(189 347.32)" fill="black">
|
||||||
|
<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">CONFIG_EN</tspan>
|
||||||
|
</text>
|
||||||
|
</g>
|
||||||
|
<g id="Graphic_35910">
|
||||||
|
<text transform="translate(188.0328 309.2)" fill="black">
|
||||||
|
<tspan font-family="Times New Roman" font-size="12" font-style="italic" font-weight="400" fill="black" x="0" y="11">CFG_EN</tspan>
|
||||||
|
</text>
|
||||||
|
</g>
|
||||||
|
<g id="Graphic_35911">
|
||||||
|
<text transform="translate(318.24 347.07)" fill="black">
|
||||||
|
<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">CONFIG_EN</tspan>
|
||||||
|
</text>
|
||||||
|
</g>
|
||||||
|
<g id="Line_35914">
|
||||||
|
<line x1="210.6998" y1="328.70976" x2="210.6998" y2="346.32" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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||||||
|
</g>
|
||||||
|
<g id="Line_35915">
|
||||||
|
<line x1="341.7405" y1="338.41742" x2="341.7405" y2="346.75" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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|
</g>
|
||||||
|
<g id="Graphic_35917">
|
||||||
|
<text transform="translate(439.644 347.07)" fill="black">
|
||||||
|
<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">CONFIG_EN</tspan>
|
||||||
|
</text>
|
||||||
|
</g>
|
||||||
|
<g id="Line_35916">
|
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<line x1="463.1445" y1="338.12" x2="463.1445" y2="346.75" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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</g>
|
||||||
|
<g id="Graphic_35919">
|
||||||
|
<text transform="translate(603.804 347.07)" fill="black">
|
||||||
|
<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">CONFIG_EN</tspan>
|
||||||
|
</text>
|
||||||
|
</g>
|
||||||
|
<g id="Line_35918">
|
||||||
|
<line x1="627.3045" y1="334.08" x2="627.3045" y2="346.75" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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|
</g>
|
||||||
|
<g id="Line_35920">
|
||||||
|
<line x1="213.16987" y1="336.11768" x2="627.3045" y2="334.08" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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|
</g>
|
||||||
|
<g id="Graphic_35921">
|
||||||
|
<ellipse cx="463.1445" cy="335.1" rx="2.47010548958708" ry="2.52000397038632" fill="black"/>
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|
<ellipse cx="463.1445" cy="335.1" rx="2.47010548958708" ry="2.52000397038632" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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||||||
|
</g>
|
||||||
|
<g id="Graphic_35922">
|
||||||
|
<ellipse cx="341.7405" cy="335.39742" rx="2.47010548958708" ry="2.52000397038629" fill="black"/>
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|
<ellipse cx="341.7405" cy="335.39742" rx="2.47010548958708" ry="2.52000397038629" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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||||||
|
</g>
|
||||||
|
<g id="Graphic_35923">
|
||||||
|
<ellipse cx="210.6998" cy="336.12983" rx="2.47010548958711" ry="2.5200039703863" fill="black"/>
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|
<ellipse cx="210.6998" cy="336.12983" rx="2.47010548958711" ry="2.5200039703863" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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||||||
|
</g>
|
||||||
|
<g id="Line_35926">
|
||||||
|
<line x1="99.34016" y1="472.63047" x2="772.9913" y2="468.9238" stroke="#ff2600" stroke-linecap="round" stroke-linejoin="round" stroke-dasharray="4.0,4.0" stroke-width="1"/>
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|
</g>
|
||||||
|
<g id="Graphic_35925">
|
||||||
|
<text transform="translate(96.8972 479.89917)" fill="#ff2600">
|
||||||
|
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="#ff2600" x="0" y="11">Configurable Circuits</tspan>
|
||||||
|
</text>
|
||||||
|
</g>
|
||||||
|
<g id="Graphic_35924">
|
||||||
|
<text transform="translate(71.011316 309.2)" fill="#ff2600">
|
||||||
|
<tspan font-family="Times New Roman" font-size="12" font-weight="700" fill="#ff2600" x="0" y="11">Configuration Chain</tspan>
|
||||||
|
</text>
|
||||||
|
</g>
|
||||||
|
<g id="Graphic_35927">
|
||||||
|
<text transform="translate(177.84 372.6)" fill="black">
|
||||||
|
<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">SI</tspan>
|
||||||
|
</text>
|
||||||
|
</g>
|
||||||
|
<g id="Line_35928">
|
||||||
|
<path d="M 175.8488 377.29115 L 164.16 377.375 L 164.16 362.9738" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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|
</g>
|
||||||
|
<g id="Graphic_35929">
|
||||||
|
<ellipse cx="164.16" cy="363.2949" rx="2.4701054895871" ry="2.52000397038626" fill="black"/>
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|
<ellipse cx="164.16" cy="363.2949" rx="2.4701054895871" ry="2.52000397038626" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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|
</g>
|
||||||
|
<g id="Line_35931">
|
||||||
|
<line x1="139.14015" y1="362.6472" x2="164.07007" y2="362.49023" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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|
</g>
|
||||||
|
<g id="Graphic_35934">
|
||||||
|
<text transform="translate(307.8 372.6)" fill="black">
|
||||||
|
<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">SI</tspan>
|
||||||
|
</text>
|
||||||
|
</g>
|
||||||
|
<g id="Line_35933">
|
||||||
|
<path d="M 305.8088 377.29115 L 294.12 377.375 L 294.12 362.9738" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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</g>
|
||||||
|
<g id="Graphic_35932">
|
||||||
|
<ellipse cx="294.12" cy="363.2949" rx="2.47010548958708" ry="2.52000397038629" fill="black"/>
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|
<ellipse cx="294.12" cy="363.2949" rx="2.47010548958708" ry="2.52000397038629" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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|
</g>
|
||||||
|
<g id="Graphic_35937">
|
||||||
|
<text transform="translate(431.6026 372.1462)" fill="black">
|
||||||
|
<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">SI</tspan>
|
||||||
|
</text>
|
||||||
|
</g>
|
||||||
|
<g id="Line_35936">
|
||||||
|
<path d="M 429.6114 376.83735 L 417.9226 376.9212 L 417.9226 362.52" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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</g>
|
||||||
|
<g id="Graphic_35935">
|
||||||
|
<ellipse cx="417.9226" cy="362.8411" rx="2.47010548958708" ry="2.52000397038635" fill="black"/>
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<ellipse cx="417.9226" cy="362.8411" rx="2.47010548958708" ry="2.52000397038635" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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|
</g>
|
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|
<g id="Graphic_35940">
|
||||||
|
<text transform="translate(594.203 372.1462)" fill="black">
|
||||||
|
<tspan font-family="Times New Roman" font-size="9" font-weight="400" fill="black" x="0" y="8">SI</tspan>
|
||||||
|
</text>
|
||||||
|
</g>
|
||||||
|
<g id="Line_35939">
|
||||||
|
<path d="M 592.2118 376.83735 L 580.523 376.9212 L 580.523 362.52" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="2"/>
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</g>
|
||||||
|
<g id="Graphic_35938">
|
||||||
|
<ellipse cx="580.523" cy="362.8411" rx="2.47010548958711" ry="2.52000397038635" fill="black"/>
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<ellipse cx="580.523" cy="362.8411" rx="2.47010548958711" ry="2.52000397038635" stroke="black" stroke-linecap="round" stroke-linejoin="round" stroke-width="1"/>
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||||||
|
</g>
|
||||||
|
</g>
|
||||||
|
</g>
|
||||||
|
</svg>
|
||||||
|
After Width: | Height: | Size: 27 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 25 KiB |
|
|
@ -290,17 +290,35 @@ size_t check_ccff_circuit_model_ports(const CircuitLibrary& circuit_lib,
|
||||||
VTR_ASSERT(CIRCUIT_MODEL_CCFF == circuit_lib.model_type(circuit_model));
|
VTR_ASSERT(CIRCUIT_MODEL_CCFF == circuit_lib.model_type(circuit_model));
|
||||||
|
|
||||||
/* Check if we have D, Set and Reset */
|
/* Check if we have D, Set and Reset */
|
||||||
|
/* We can have either 1 input which is D or 2 inputs which are D and scan input */
|
||||||
|
size_t num_input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true).size();
|
||||||
|
if ((1 != num_input_ports) && (2 != num_input_ports)) {
|
||||||
|
VTR_LOG_ERROR("Configuration flip-flop '%s' must have either 1 or 2 %s ports!\n\tAmong which:\n\t\tthe first input is a regular input (e.g., D)\n\t\tand the other could be scan-chain input (e.g., SI)\n",
|
||||||
|
circuit_lib.model_name(circuit_model).c_str(),
|
||||||
|
CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(CIRCUIT_MODEL_PORT_INPUT)]);
|
||||||
|
num_err++;
|
||||||
|
}
|
||||||
|
|
||||||
num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model,
|
num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model,
|
||||||
CIRCUIT_MODEL_PORT_INPUT,
|
CIRCUIT_MODEL_PORT_INPUT,
|
||||||
1, 1, false);
|
num_input_ports, 1, false);
|
||||||
/* Check if we have a clock */
|
/* Check if we have a clock */
|
||||||
num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model,
|
num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model,
|
||||||
CIRCUIT_MODEL_PORT_CLOCK,
|
CIRCUIT_MODEL_PORT_CLOCK,
|
||||||
1, 1, true);
|
1, 1, true);
|
||||||
|
|
||||||
|
|
||||||
/* Check if we have 1 or 2 outputs */
|
/* Check if we have 1 or 2 or 3 outputs */
|
||||||
size_t num_output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true).size();
|
size_t num_output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true).size();
|
||||||
|
if ((1 != num_output_ports)
|
||||||
|
&& (2 != num_output_ports)
|
||||||
|
&& (3 != num_output_ports)) {
|
||||||
|
VTR_LOG_ERROR("Configuration flip-flop '%s' must have either 1 or 2 or 3 %s ports!\n\tAmong which:\n\t\tthe first port is the manadatory regular data output (e.g., Q) and \n\t\tthe second port could be the inverted data output which can optionally be enabled by configure-enable signal (e.g., QN or cgf_en_QN) and \n\t\tthe third port could be the data output which can optionally be enabled by configure-enable signal (e.g., cgf_en_Q)\n",
|
||||||
|
circuit_lib.model_name(circuit_model).c_str(),
|
||||||
|
CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(CIRCUIT_MODEL_PORT_OUTPUT)]);
|
||||||
|
num_err++;
|
||||||
|
}
|
||||||
|
|
||||||
num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model,
|
num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model,
|
||||||
CIRCUIT_MODEL_PORT_OUTPUT,
|
CIRCUIT_MODEL_PORT_OUTPUT,
|
||||||
num_output_ports, 1, false);
|
num_output_ports, 1, false);
|
||||||
|
|
|
||||||
|
|
@ -13,7 +13,10 @@ namespace openfpga {
|
||||||
/* Top-level module name */
|
/* Top-level module name */
|
||||||
constexpr char* FPGA_TOP_MODULE_NAME = "fpga_top";
|
constexpr char* FPGA_TOP_MODULE_NAME = "fpga_top";
|
||||||
|
|
||||||
|
constexpr char* CONFIGURABLE_MEMORY_CHAIN_IN_NAME = "ccff_head";
|
||||||
|
constexpr char* CONFIGURABLE_MEMORY_CHAIN_OUT_NAME = "ccff_tail";
|
||||||
constexpr char* CONFIGURABLE_MEMORY_DATA_OUT_NAME = "mem_out";
|
constexpr char* CONFIGURABLE_MEMORY_DATA_OUT_NAME = "mem_out";
|
||||||
|
constexpr char* CONFIGURABLE_MEMORY_INVERTED_DATA_OUT_NAME = "mem_outb";
|
||||||
|
|
||||||
/* IO PORT */
|
/* IO PORT */
|
||||||
/* Prefix of global input, output and inout ports of FPGA fabric */
|
/* Prefix of global input, output and inout ports of FPGA fabric */
|
||||||
|
|
|
||||||
|
|
@ -708,7 +708,7 @@ std::string generate_formal_verification_sram_port_name(const CircuitLibrary& ci
|
||||||
* TODO: This could be replaced as a constexpr string
|
* TODO: This could be replaced as a constexpr string
|
||||||
*********************************************************************/
|
*********************************************************************/
|
||||||
std::string generate_configuration_chain_head_name() {
|
std::string generate_configuration_chain_head_name() {
|
||||||
return std::string("ccff_head");
|
return std::string(CONFIGURABLE_MEMORY_CHAIN_IN_NAME);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*********************************************************************
|
/*********************************************************************
|
||||||
|
|
@ -716,7 +716,7 @@ std::string generate_configuration_chain_head_name() {
|
||||||
* TODO: This could be replaced as a constexpr string
|
* TODO: This could be replaced as a constexpr string
|
||||||
*********************************************************************/
|
*********************************************************************/
|
||||||
std::string generate_configuration_chain_tail_name() {
|
std::string generate_configuration_chain_tail_name() {
|
||||||
return std::string("ccff_tail");
|
return std::string(CONFIGURABLE_MEMORY_CHAIN_OUT_NAME);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*********************************************************************
|
/*********************************************************************
|
||||||
|
|
@ -732,7 +732,7 @@ std::string generate_configurable_memory_data_out_name() {
|
||||||
* TODO: This could be replaced as a constexpr string
|
* TODO: This could be replaced as a constexpr string
|
||||||
*********************************************************************/
|
*********************************************************************/
|
||||||
std::string generate_configurable_memory_inverted_data_out_name() {
|
std::string generate_configurable_memory_inverted_data_out_name() {
|
||||||
return std::string("mem_outb");
|
return std::string(CONFIGURABLE_MEMORY_INVERTED_DATA_OUT_NAME);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*********************************************************************
|
/*********************************************************************
|
||||||
|
|
|
||||||
|
|
@ -77,8 +77,6 @@ void add_module_input_nets_to_mem_modules(ModuleManager& module_manager,
|
||||||
* j-th pin of output port of the i-th child module is wired to the j + i*W -th
|
* j-th pin of output port of the i-th child module is wired to the j + i*W -th
|
||||||
* pin of output port of the memory module, where W is the size of port
|
* pin of output port of the memory module, where W is the size of port
|
||||||
* 3. It assumes fixed port name for output ports
|
* 3. It assumes fixed port name for output ports
|
||||||
*
|
|
||||||
* We cache the module nets that have been created because they will be used later
|
|
||||||
********************************************************************/
|
********************************************************************/
|
||||||
static
|
static
|
||||||
std::vector<ModuleNetId> add_module_output_nets_to_chain_mem_modules(ModuleManager& module_manager,
|
std::vector<ModuleNetId> add_module_output_nets_to_chain_mem_modules(ModuleManager& module_manager,
|
||||||
|
|
@ -165,15 +163,11 @@ void add_module_output_nets_to_mem_modules(ModuleManager& module_manager,
|
||||||
* add_module_nets_cmos_memory_chain_config_bus() !!!
|
* add_module_nets_cmos_memory_chain_config_bus() !!!
|
||||||
*********************************************************************/
|
*********************************************************************/
|
||||||
static
|
static
|
||||||
void add_module_nets_to_cmos_memory_chain_module(ModuleManager& module_manager,
|
void add_module_nets_to_cmos_memory_config_chain_module(ModuleManager& module_manager,
|
||||||
const ModuleId& parent_module,
|
const ModuleId& parent_module,
|
||||||
const std::vector<ModuleNetId>& output_nets,
|
|
||||||
const CircuitLibrary& circuit_lib,
|
const CircuitLibrary& circuit_lib,
|
||||||
const CircuitPortId& model_input_port,
|
const CircuitPortId& model_input_port,
|
||||||
const CircuitPortId& model_output_port) {
|
const CircuitPortId& model_output_port) {
|
||||||
/* Counter for the nets */
|
|
||||||
size_t net_counter = 0;
|
|
||||||
|
|
||||||
for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) {
|
for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) {
|
||||||
ModuleId net_src_module_id;
|
ModuleId net_src_module_id;
|
||||||
size_t net_src_instance_id;
|
size_t net_src_instance_id;
|
||||||
|
|
@ -219,21 +213,9 @@ void add_module_nets_to_cmos_memory_chain_module(ModuleManager& module_manager,
|
||||||
/* Create a net for each pin */
|
/* Create a net for each pin */
|
||||||
for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) {
|
for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) {
|
||||||
/* Create a net and add source and sink to it */
|
/* Create a net and add source and sink to it */
|
||||||
ModuleNetId net;
|
ModuleNetId net = create_module_source_pin_net(module_manager, parent_module, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]);
|
||||||
if (0 == mem_index) {
|
|
||||||
net = module_manager.create_module_net(parent_module);
|
|
||||||
} else {
|
|
||||||
net = output_nets[net_counter];
|
|
||||||
}
|
|
||||||
/* Add net source */
|
|
||||||
module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]);
|
|
||||||
/* Add net sink */
|
/* Add net sink */
|
||||||
module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]);
|
module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]);
|
||||||
|
|
||||||
/* Update net counter */
|
|
||||||
if (0 < mem_index) {
|
|
||||||
net_counter++;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -263,17 +245,90 @@ void add_module_nets_to_cmos_memory_chain_module(ModuleManager& module_manager,
|
||||||
/* Create a net for each pin */
|
/* Create a net for each pin */
|
||||||
for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) {
|
for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) {
|
||||||
/* Create a net and add source and sink to it */
|
/* Create a net and add source and sink to it */
|
||||||
ModuleNetId net = output_nets[net_counter];
|
ModuleNetId net = create_module_source_pin_net(module_manager, parent_module, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]);
|
||||||
/* Add net source */
|
|
||||||
module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]);
|
|
||||||
/* Add net sink */
|
/* Add net sink */
|
||||||
module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]);
|
module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]);
|
||||||
|
}
|
||||||
/* Update net counter */
|
|
||||||
net_counter++;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
VTR_ASSERT(net_counter == output_nets.size());
|
/********************************************************************
|
||||||
|
* Connect the scan input of all the memory modules
|
||||||
|
* under the parent module in a chain
|
||||||
|
*
|
||||||
|
* +--------+ +--------+ +--------+
|
||||||
|
* ccff_head --->| Memory |--->| Memory |--->... --->| Memory |
|
||||||
|
* | Module | | Module | | Module |
|
||||||
|
* | [0] | | [1] | | [N-1] |
|
||||||
|
* +--------+ +--------+ +--------+
|
||||||
|
* For the 1st memory module:
|
||||||
|
* net source is the configuration chain head of the primitive module
|
||||||
|
* net sink is the scan input of the next memory module
|
||||||
|
*
|
||||||
|
* For the rest of memory modules:
|
||||||
|
* net source is the configuration chain tail of the previous memory module
|
||||||
|
* net sink is the scan input of the next memory module
|
||||||
|
*
|
||||||
|
* Note that:
|
||||||
|
* This function is designed for memory modules ONLY!
|
||||||
|
* Do not use it to replace the
|
||||||
|
* add_module_nets_cmos_memory_chain_config_bus() !!!
|
||||||
|
*********************************************************************/
|
||||||
|
static
|
||||||
|
void add_module_nets_to_cmos_memory_scan_chain_module(ModuleManager& module_manager,
|
||||||
|
const ModuleId& parent_module,
|
||||||
|
const CircuitLibrary& circuit_lib,
|
||||||
|
const CircuitPortId& model_input_port,
|
||||||
|
const CircuitPortId& model_output_port) {
|
||||||
|
for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) {
|
||||||
|
ModuleId net_src_module_id;
|
||||||
|
size_t net_src_instance_id;
|
||||||
|
ModulePortId net_src_port_id;
|
||||||
|
|
||||||
|
ModuleId net_sink_module_id;
|
||||||
|
size_t net_sink_instance_id;
|
||||||
|
ModulePortId net_sink_port_id;
|
||||||
|
|
||||||
|
if (0 == mem_index) {
|
||||||
|
/* Find the port name of configuration chain head */
|
||||||
|
std::string src_port_name = generate_configuration_chain_head_name();
|
||||||
|
net_src_module_id = parent_module;
|
||||||
|
net_src_instance_id = 0;
|
||||||
|
net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name);
|
||||||
|
|
||||||
|
/* Find the port name of next memory module */
|
||||||
|
std::string sink_port_name = circuit_lib.port_prefix(model_input_port);
|
||||||
|
net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index];
|
||||||
|
net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index];
|
||||||
|
net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name);
|
||||||
|
} else {
|
||||||
|
/* Find the port name of previous memory module */
|
||||||
|
std::string src_port_name = circuit_lib.port_prefix(model_output_port);
|
||||||
|
net_src_module_id = module_manager.configurable_children(parent_module)[mem_index - 1];
|
||||||
|
net_src_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index - 1];
|
||||||
|
net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name);
|
||||||
|
|
||||||
|
/* Find the port name of next memory module */
|
||||||
|
std::string sink_port_name = circuit_lib.port_prefix(model_input_port);
|
||||||
|
net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index];
|
||||||
|
net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index];
|
||||||
|
net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get the pin id for source port */
|
||||||
|
BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id);
|
||||||
|
/* Get the pin id for sink port */
|
||||||
|
BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id);
|
||||||
|
/* Port sizes of source and sink should match */
|
||||||
|
VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width());
|
||||||
|
|
||||||
|
/* Create a net for each pin */
|
||||||
|
for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) {
|
||||||
|
/* Create a net and add source and sink to it */
|
||||||
|
ModuleNetId net = create_module_source_pin_net(module_manager, parent_module, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]);
|
||||||
|
/* Add net sink */
|
||||||
|
module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]);
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/*********************************************************************
|
/*********************************************************************
|
||||||
|
|
@ -382,7 +437,7 @@ void build_memory_flatten_module(ModuleManager& module_manager,
|
||||||
* scan-chain--->| CCFF |--->| CCFF |--->... --->| CCFF |---->scan-chain
|
* scan-chain--->| CCFF |--->| CCFF |--->... --->| CCFF |---->scan-chain
|
||||||
* input&clock | [0] | | [1] | | [N-1] | output
|
* input&clock | [0] | | [1] | | [N-1] | output
|
||||||
* +-------+ +-------+ +-------+
|
* +-------+ +-------+ +-------+
|
||||||
* | | ... |
|
* | | ... | config-memory output
|
||||||
* v v v
|
* v v v
|
||||||
* +-----------------------------------------+
|
* +-----------------------------------------+
|
||||||
* | Multiplexer Configuration port |
|
* | Multiplexer Configuration port |
|
||||||
|
|
@ -397,12 +452,15 @@ void build_memory_chain_module(ModuleManager& module_manager,
|
||||||
|
|
||||||
/* Get the input ports from the SRAM */
|
/* Get the input ports from the SRAM */
|
||||||
std::vector<CircuitPortId> sram_input_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_INPUT, true);
|
std::vector<CircuitPortId> sram_input_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_INPUT, true);
|
||||||
/* Should have only 1 input port */
|
/* Should have only 1 or 2 input port */
|
||||||
VTR_ASSERT( 1 == sram_input_ports.size() );
|
VTR_ASSERT( (1 == sram_input_ports.size())
|
||||||
|
|| (2 == sram_input_ports.size()) );
|
||||||
/* Get the output ports from the SRAM */
|
/* Get the output ports from the SRAM */
|
||||||
std::vector<CircuitPortId> sram_output_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
|
std::vector<CircuitPortId> sram_output_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
|
||||||
/* Should have only 1 or 2 output port */
|
/* Should have only 1 or 2 or 3 output port */
|
||||||
VTR_ASSERT( (1 == sram_output_ports.size()) || ( 2 == sram_output_ports.size()) );
|
VTR_ASSERT( (1 == sram_output_ports.size())
|
||||||
|
|| (2 == sram_output_ports.size())
|
||||||
|
|| (3 == sram_output_ports.size()) );
|
||||||
|
|
||||||
/* Create a module and add to the module manager */
|
/* Create a module and add to the module manager */
|
||||||
ModuleId mem_module = module_manager.add_module(module_name);
|
ModuleId mem_module = module_manager.add_module(module_name);
|
||||||
|
|
@ -428,13 +486,27 @@ void build_memory_chain_module(ModuleManager& module_manager,
|
||||||
circuit_lib.port_size(sram_output_ports[0]));
|
circuit_lib.port_size(sram_output_ports[0]));
|
||||||
module_manager.add_port(mem_module, chain_tail_port, ModuleManager::MODULE_OUTPUT_PORT);
|
module_manager.add_port(mem_module, chain_tail_port, ModuleManager::MODULE_OUTPUT_PORT);
|
||||||
|
|
||||||
/* Add each output port: port width should match the number of memories */
|
/* There could be 3 conditions w.r.t. the number of output ports:
|
||||||
for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) {
|
* - Only one output port is defined. In this case, the 1st port is the Q
|
||||||
|
* In such case, only Q will be considered as data output ports
|
||||||
|
* - Two output port is defined. In this case, the 1st port is the Q while the 2nd port is the QN
|
||||||
|
* In such case, both Q and QN will be considered as data output ports
|
||||||
|
* - Three output port is defined.
|
||||||
|
* In this case:
|
||||||
|
* - the 1st port is the Q (the chain output)
|
||||||
|
* - the 2nd port is the QN (the inverted data output)
|
||||||
|
* - the 3nd port is the configure-enabled Q
|
||||||
|
* In such case, configure-enabled Q and QN will be considered as data output ports
|
||||||
|
*/
|
||||||
|
size_t num_data_output_ports = sram_output_ports.size();
|
||||||
|
if (3 == sram_output_ports.size()) {
|
||||||
|
num_data_output_ports = 2;
|
||||||
|
}
|
||||||
|
for (size_t iport = 0; iport < num_data_output_ports; ++iport) {
|
||||||
std::string port_name;
|
std::string port_name;
|
||||||
if (0 == iport) {
|
if (0 == iport) {
|
||||||
port_name = generate_configurable_memory_data_out_name();
|
port_name = generate_configurable_memory_data_out_name();
|
||||||
} else {
|
} else if (1 == iport) {
|
||||||
VTR_ASSERT( 1 == iport);
|
|
||||||
port_name = generate_configurable_memory_inverted_data_out_name();
|
port_name = generate_configurable_memory_inverted_data_out_name();
|
||||||
}
|
}
|
||||||
BasicPort output_port(port_name, num_mems);
|
BasicPort output_port(port_name, num_mems);
|
||||||
|
|
@ -444,9 +516,6 @@ void build_memory_chain_module(ModuleManager& module_manager,
|
||||||
/* Find the sram module in the module manager */
|
/* Find the sram module in the module manager */
|
||||||
ModuleId sram_mem_module = module_manager.find_module(circuit_lib.model_name(sram_model));
|
ModuleId sram_mem_module = module_manager.find_module(circuit_lib.model_name(sram_model));
|
||||||
|
|
||||||
/* Cache the output nets for non-inverted data output */
|
|
||||||
std::vector<ModuleNetId> mem_output_nets;
|
|
||||||
|
|
||||||
/* Instanciate each submodule */
|
/* Instanciate each submodule */
|
||||||
for (size_t i = 0; i < num_mems; ++i) {
|
for (size_t i = 0; i < num_mems; ++i) {
|
||||||
size_t sram_mem_instance = module_manager.num_instance(mem_module, sram_mem_module);
|
size_t sram_mem_instance = module_manager.num_instance(mem_module, sram_mem_module);
|
||||||
|
|
@ -454,7 +523,7 @@ void build_memory_chain_module(ModuleManager& module_manager,
|
||||||
module_manager.add_configurable_child(mem_module, sram_mem_module, sram_mem_instance);
|
module_manager.add_configurable_child(mem_module, sram_mem_module, sram_mem_instance);
|
||||||
|
|
||||||
/* Build module nets to wire outputs of sram modules to outputs of memory module */
|
/* Build module nets to wire outputs of sram modules to outputs of memory module */
|
||||||
for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) {
|
for (size_t iport = 0; iport < num_data_output_ports; ++iport) {
|
||||||
std::string port_name;
|
std::string port_name;
|
||||||
if (0 == iport) {
|
if (0 == iport) {
|
||||||
port_name = generate_configurable_memory_data_out_name();
|
port_name = generate_configurable_memory_data_out_name();
|
||||||
|
|
@ -462,20 +531,32 @@ void build_memory_chain_module(ModuleManager& module_manager,
|
||||||
VTR_ASSERT( 1 == iport);
|
VTR_ASSERT( 1 == iport);
|
||||||
port_name = generate_configurable_memory_inverted_data_out_name();
|
port_name = generate_configurable_memory_inverted_data_out_name();
|
||||||
}
|
}
|
||||||
std::vector<ModuleNetId> output_nets = add_module_output_nets_to_chain_mem_modules(module_manager, mem_module,
|
/* Find the proper data output port
|
||||||
port_name, circuit_lib, sram_output_ports[iport],
|
* The exception is when there are 3 output ports defined
|
||||||
sram_mem_module, i, sram_mem_instance);
|
* The 3rd port is the regular data output port to be used
|
||||||
/* Cache only for regular data outputs */
|
*/
|
||||||
if (0 == iport) {
|
CircuitPortId data_output_port_to_connect = sram_output_ports[iport];
|
||||||
mem_output_nets.insert(mem_output_nets.end(), output_nets.begin(), output_nets.end());
|
if ((3 == sram_output_ports.size()) && (0 == iport)) {
|
||||||
|
data_output_port_to_connect = sram_output_ports.back();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
std::vector<ModuleNetId> output_nets = add_module_output_nets_to_chain_mem_modules(module_manager, mem_module,
|
||||||
|
port_name, circuit_lib, data_output_port_to_connect,
|
||||||
|
sram_mem_module, i, sram_mem_instance);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Build module nets to wire the configuration chain */
|
/* Build module nets to wire the configuration chain */
|
||||||
add_module_nets_to_cmos_memory_chain_module(module_manager, mem_module, mem_output_nets,
|
add_module_nets_to_cmos_memory_config_chain_module(module_manager, mem_module,
|
||||||
circuit_lib, sram_input_ports[0], sram_output_ports[0]);
|
circuit_lib, sram_input_ports[0], sram_output_ports[0]);
|
||||||
|
|
||||||
|
/* If there is a second input defined,
|
||||||
|
* add nets to short wire the 2nd inputs to the first inputs
|
||||||
|
*/
|
||||||
|
if (2 == sram_input_ports.size()) {
|
||||||
|
add_module_nets_to_cmos_memory_scan_chain_module(module_manager, mem_module,
|
||||||
|
circuit_lib, sram_input_ports[1], sram_output_ports[0]);
|
||||||
|
}
|
||||||
|
|
||||||
/* Add global ports to the pb_module:
|
/* Add global ports to the pb_module:
|
||||||
* This is a much easier job after adding sub modules (instances),
|
* This is a much easier job after adding sub modules (instances),
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,194 @@
|
||||||
|
<!-- Architecture annotation for OpenFPGA framework
|
||||||
|
This annotation supports the k6_N10_40nm.xml
|
||||||
|
- General purpose logic block
|
||||||
|
- K = 6, N = 10, I = 40
|
||||||
|
- Single mode
|
||||||
|
- Routing architecture
|
||||||
|
- L = 4, fc_in = 0.15, fc_out = 0.1
|
||||||
|
-->
|
||||||
|
<openfpga_architecture>
|
||||||
|
<technology_library>
|
||||||
|
<device_library>
|
||||||
|
<device_model name="logic" type="transistor">
|
||||||
|
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||||
|
<design vdd="0.9" pn_ratio="2"/>
|
||||||
|
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||||
|
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||||
|
</device_model>
|
||||||
|
<device_model name="io" type="transistor">
|
||||||
|
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||||
|
<design vdd="2.5" pn_ratio="3"/>
|
||||||
|
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||||
|
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||||
|
</device_model>
|
||||||
|
</device_library>
|
||||||
|
<variation_library>
|
||||||
|
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||||
|
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||||
|
</variation_library>
|
||||||
|
</technology_library>
|
||||||
|
<circuit_library>
|
||||||
|
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
|
||||||
|
<design_technology type="cmos" topology="inverter" size="1"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
|
||||||
|
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
|
||||||
|
<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||||
|
10e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
|
||||||
|
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
|
||||||
|
<device_technology device_model_name="logic"/>
|
||||||
|
<input_buffer exist="false"/>
|
||||||
|
<output_buffer exist="false"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="input" prefix="sel" size="1"/>
|
||||||
|
<port type="input" prefix="selb" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<delay_matrix type="rise" in_port="in sel selb" out_port="out">
|
||||||
|
10e-12 5e-12 5e-12
|
||||||
|
</delay_matrix>
|
||||||
|
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
|
||||||
|
10e-12 5e-12 5e-12
|
||||||
|
</delay_matrix>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="false"/>
|
||||||
|
<output_buffer exist="false"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="false"/>
|
||||||
|
<output_buffer exist="false"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
|
||||||
|
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<port type="sram" prefix="sram" size="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" is_default="true" dump_structural_verilog="true">
|
||||||
|
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
|
||||||
|
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||||
|
<port type="input" prefix="in" size="1"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<port type="sram" prefix="sram" size="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
|
||||||
|
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<port type="input" prefix="D" size="1"/>
|
||||||
|
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
|
||||||
|
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
|
||||||
|
<port type="output" prefix="Q" size="1"/>
|
||||||
|
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<lut_input_buffer exist="true" circuit_model_name="buf4"/>
|
||||||
|
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||||
|
<port type="input" prefix="in" size="4"/>
|
||||||
|
<port type="output" prefix="out" size="1"/>
|
||||||
|
<port type="sram" prefix="sram" size="16"/>
|
||||||
|
</circuit_model>
|
||||||
|
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
|
||||||
|
<circuit_model type="ccff" name="CFGSDFFR" prefix="CFGSDFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
|
||||||
|
<port type="input" prefix="SE" size="1" is_global="true" default_val="0"/>
|
||||||
|
<port type="input" prefix="config_enable" lib_name="CFGE" size="1" is_global="true" default_val="0" is_config_enable="true"/>
|
||||||
|
<port type="input" prefix="D" size="1"/>
|
||||||
|
<port type="input" prefix="SI" size="1"/>
|
||||||
|
<port type="output" prefix="Q" size="1"/>
|
||||||
|
<port type="output" prefix="CFGQN" size="1"/>
|
||||||
|
<port type="output" prefix="CFGQ" size="1"/>
|
||||||
|
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
|
||||||
|
</circuit_model>
|
||||||
|
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
|
||||||
|
<design_technology type="cmos"/>
|
||||||
|
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||||
|
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
|
||||||
|
<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="CFGSDFFR" default_val="1"/>
|
||||||
|
<port type="input" prefix="outpad" lib_name="A" size="1"/>
|
||||||
|
<port type="output" prefix="inpad" lib_name="Y" size="1"/>
|
||||||
|
</circuit_model>
|
||||||
|
</circuit_library>
|
||||||
|
<configuration_protocol>
|
||||||
|
<organization type="scan_chain" circuit_model_name="CFGSDFFR"/>
|
||||||
|
</configuration_protocol>
|
||||||
|
<connection_block>
|
||||||
|
<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
|
||||||
|
</connection_block>
|
||||||
|
<switch_block>
|
||||||
|
<switch name="0" circuit_model_name="mux_tree_tapbuf"/>
|
||||||
|
</switch_block>
|
||||||
|
<routing_segment>
|
||||||
|
<segment name="L4" circuit_model_name="chan_segment"/>
|
||||||
|
</routing_segment>
|
||||||
|
<pb_type_annotations>
|
||||||
|
<!-- physical pb_type binding in complex block IO -->
|
||||||
|
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
||||||
|
<pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
|
||||||
|
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
|
||||||
|
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
|
||||||
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
|
|
||||||
|
<!-- physical pb_type binding in complex block CLB -->
|
||||||
|
<!-- physical mode will be the default mode if not specified -->
|
||||||
|
<pb_type name="clb">
|
||||||
|
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
|
||||||
|
<interconnect name="crossbar" circuit_model_name="mux_tree"/>
|
||||||
|
</pb_type>
|
||||||
|
<pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
|
||||||
|
<pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
|
||||||
|
<!-- End physical pb_type binding in complex block IO -->
|
||||||
|
</pb_type_annotations>
|
||||||
|
</openfpga_architecture>
|
||||||
|
|
@ -397,3 +397,50 @@ end
|
||||||
assign Q = q_reg;
|
assign Q = q_reg;
|
||||||
|
|
||||||
endmodule //End Of Module
|
endmodule //End Of Module
|
||||||
|
|
||||||
|
//-----------------------------------------------------
|
||||||
|
// Function : D-type flip-flop with
|
||||||
|
// - asynchronous active high reset
|
||||||
|
// - scan-chain input
|
||||||
|
// - a scan-chain enable
|
||||||
|
// - a configure enable, when enabled the registered output will
|
||||||
|
// be released to the Q
|
||||||
|
//-----------------------------------------------------
|
||||||
|
module CFGSDFFR (
|
||||||
|
input RST, // Reset input
|
||||||
|
input CK, // Clock Input
|
||||||
|
input SE, // Scan-chain Enable
|
||||||
|
input D, // Data Input
|
||||||
|
input SI, // Scan-chain input
|
||||||
|
input CFGE, // Configure enable
|
||||||
|
output Q, // Regular Q output
|
||||||
|
output CFGQ, // Data Q output which is released when configure enable is activated
|
||||||
|
output CFGQN // Data Qb output which is released when configure enable is activated
|
||||||
|
);
|
||||||
|
//------------Internal Variables--------
|
||||||
|
reg q_reg;
|
||||||
|
wire QN;
|
||||||
|
|
||||||
|
//-------------Code Starts Here---------
|
||||||
|
always @ ( posedge CK or posedge RST)
|
||||||
|
if (RST) begin
|
||||||
|
q_reg <= 1'b0;
|
||||||
|
end else if (SE) begin
|
||||||
|
q_reg <= SI;
|
||||||
|
end else begin
|
||||||
|
q_reg <= D;
|
||||||
|
end
|
||||||
|
|
||||||
|
assign CFGQ = CFGE ? Q : 1'b0;
|
||||||
|
assign CFGQN = CFGE ? QN : 1'b1;
|
||||||
|
|
||||||
|
`ifndef ENABLE_FORMAL_VERIFICATION
|
||||||
|
// Wire q_reg to Q
|
||||||
|
assign Q = q_reg;
|
||||||
|
assign QN = !Q;
|
||||||
|
`else
|
||||||
|
assign Q = 1'bZ;
|
||||||
|
assign QN = !Q;
|
||||||
|
`endif
|
||||||
|
|
||||||
|
endmodule //End Of Module
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,42 @@
|
||||||
|
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||||
|
# Configuration file for running experiments
|
||||||
|
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||||
|
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||||
|
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||||
|
# timeout_each_job is timeout for each job
|
||||||
|
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||||
|
|
||||||
|
[GENERAL]
|
||||||
|
run_engine=openfpga_shell
|
||||||
|
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||||
|
power_analysis = true
|
||||||
|
spice_output=false
|
||||||
|
verilog_output=true
|
||||||
|
timeout_each_job = 1*60
|
||||||
|
fpga_flow=yosys_vpr
|
||||||
|
|
||||||
|
[OpenFPGA_SHELL]
|
||||||
|
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga
|
||||||
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgscff_openfpga.xml
|
||||||
|
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||||
|
|
||||||
|
[ARCHITECTURES]
|
||||||
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
||||||
|
|
||||||
|
[BENCHMARKS]
|
||||||
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||||
|
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
|
||||||
|
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
|
||||||
|
|
||||||
|
[SYNTHESIS_PARAM]
|
||||||
|
bench0_top = and2
|
||||||
|
bench0_chan_width = 300
|
||||||
|
|
||||||
|
bench1_top = or2
|
||||||
|
bench1_chan_width = 300
|
||||||
|
|
||||||
|
bench2_top = and2_latch
|
||||||
|
bench2_chan_width = 300
|
||||||
|
|
||||||
|
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||||
|
end_flow_with_test=
|
||||||
Loading…
Reference in New Issue