diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 4c0ec145f..c38ba3b3a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -789,14 +789,15 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { Side side_manager(side); DeviceCoordinator chan_coordinator = rr_sb.get_side_block_coordinator(side_manager.get_side()); + DeviceCoordinator unique_chan_coordinator = unique_mirror.get_side_block_coordinator(side_manager.get_side()); fprintf(fp, "//----- %s side channel ports-----\n", side_manager.c_str()); for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { if (true == is_explicit_mapping) { fprintf(fp, ".%s(", - gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), - chan_coordinator.get_x(), chan_coordinator.get_y(), itrack, - rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + gen_verilog_routing_channel_one_pin_name(unique_mirror.get_chan_node(side_manager.get_side(), itrack), + unique_chan_coordinator.get_x(), unique_chan_coordinator.get_y(), itrack, + unique_mirror.get_chan_node_direction(side_manager.get_side(), itrack))); } fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), @@ -815,6 +816,8 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, + unique_mirror.get_opin_node(side_manager.get_side(), inode)->xlow, + unique_mirror.get_opin_node(side_manager.get_side(), inode)->ylow, FALSE, is_explicit_mapping); /* Do not specify the direction of port */ fprintf(fp, ",\n"); } @@ -964,6 +967,8 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), cur_ipin_node->xlow, cur_ipin_node->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* Do not specify direction of port */ if (true == is_explicit_mapping) { fprintf(fp, ")"); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 14d200038..30ac68c03 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -313,6 +313,7 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, int pin_index, int side, int x, int y, + int unique_x, int unique_y, /* If explicit, needs the coordinates of the mirror*/ boolean dump_port_type, bool is_explicit_mapping) { int height; @@ -360,7 +361,7 @@ void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, is_explicit_mapping = false; /* Both cannot be true at the same time */ } if (true == is_explicit_mapping) { - fprintf(fp, ".%s(", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE)); + fprintf(fp, ".%s(", gen_verilog_grid_one_pin_name(unique_x, unique_y, height, side, pin_index, TRUE)); } fprintf(fp, "%s", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE)); if (true == is_explicit_mapping) { @@ -565,6 +566,7 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp, drive_rr_node->ptc_num, rr_sb.get_opin_node_grid_side(drive_rr_node), grid_x, grid_y, + 0, 0, /* No explicit mapping*/ FALSE, false); /* Do not dump the direction of the port! */ break; case CHANX: @@ -667,6 +669,8 @@ void dump_verilog_switch_box_short_interc(FILE* fp, drive_rr_node->ptc_num, cur_sb_info->opin_rr_node_grid_side[side][index], grid_x, grid_y, + 0, /*Used in more recent version*/ + 0, /*Used in more recent version*/ FALSE, is_explicit_mapping); /* Do not dump the direction of the port! */ break; case CHANX: @@ -767,12 +771,16 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, /* Find grid_x and grid_y */ grid_x = drive_rr_nodes[inode]->xlow; grid_y = drive_rr_nodes[inode]->ylow; /*Plus the offset in function fprint_grid_side_pin_with_given_index */ + //const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, coordinator); /* Print a grid pin */ fprintf(fp, "assign %s_size%d_%d_inbus[%d] = ", verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num, cur_sb_info->opin_rr_node_grid_side[side][index], - grid_x, grid_y, FALSE, is_explicit_mapping); + grid_x, grid_y, + 0,/*Used in more recent version*/ + 0,/*Used in more recent version*/ + FALSE, is_explicit_mapping); fprintf(fp, ";\n"); input_cnt++; break; @@ -1029,7 +1037,9 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num, rr_sb.get_opin_node_grid_side(drive_rr_nodes[inode]), - grid_x, grid_y, FALSE, false); + grid_x, grid_y, + 0,0,/*No explicit mapping */ + FALSE, false); fprintf(fp, ";\n"); input_cnt++; break; @@ -1803,6 +1813,7 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, } /* Dump OPINs of adjacent CLBs */ + //const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(port_coordinator); for (size_t inode = 0; inode < rr_sb.get_num_opin_nodes(side_manager.get_side()); ++inode) { fprintf(fp, " "); dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */ @@ -1810,6 +1821,8 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, + rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, + rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, dump_port_type, is_explicit_mapping); /* Dump the direction of the port ! */ if (FALSE == dump_port_type) { fprintf(fp, ",\n"); @@ -2078,7 +2091,8 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, - TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ + 0,0, /*No explicit mapping */ + TRUE, false); /* Dump the direction of the port ! */ } } @@ -2315,6 +2329,8 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or } } /* Dump OPINs of adjacent CLBs */ + puts("CHECK4"); + const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(port_coordinator); for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) { fprintf(fp, " "); dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */ @@ -2322,6 +2338,8 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, + unique_mirror.get_opin_node(side_manager.get_side(), inode)->xlow, + unique_mirror.get_opin_node(side_manager.get_side(), inode)->ylow, TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ } } @@ -2524,6 +2542,8 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info cur_sb_info->opin_rr_node_grid_side[side][inode], cur_sb_info->opin_rr_node[side][inode]->xlow, cur_sb_info->opin_rr_node[side][inode]->ylow, + 0,/*used in more recent version*/ + 0,/*used in more recent version*/ TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ } } @@ -2772,6 +2792,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp, rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ + 0,0, /*No explicit mapping */ FALSE, false); /* Do not specify the direction of this pin */ /* End */ @@ -2849,6 +2870,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp, cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ + 0,0, /*No explicit mapping */ FALSE, false); /* Do not specify the direction of this pin */ /* End */ @@ -3006,6 +3028,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ + 0,0, /*No explicit mapping*/ FALSE, false); /* Do not specify the direction of port */ if (true == is_explicit_mapping) { fprintf(fp, ")"); @@ -3253,6 +3276,8 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ + 0,/*No explicit mapping*/ + 0,/*No explicit mapping*/ FALSE, false); /* Do not specify the direction of port */ if (true == is_explicit_mapping) { fprintf(fp, ")"); @@ -3582,6 +3607,8 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), rr_gsb.get_ipin_node(cb_ipin_side, inode)->xlow, rr_gsb.get_ipin_node(cb_ipin_side, inode)->ylow, + 0,/*No explicit mapping */ + 0,/*No explicit mapping */ TRUE, false); } @@ -3785,6 +3812,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ assert((1 == side_cnt)||(2 == side_cnt)); side_cnt = 0; + //const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, coordinator); /* Print the ports of grids*/ /* only check ipin_rr_nodes of cur_cb_info */ for (side = 0; side < cur_cb_info->num_sides; side++) { @@ -3802,6 +3830,8 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ cur_cb_info->ipin_rr_node_grid_side[side][inode], cur_cb_info->ipin_rr_node[side][inode]->xlow, cur_cb_info->ipin_rr_node[side][inode]->ylow, + 0,/*Used in more recent version*/ + 0,/*Used in more recent version*/ TRUE, is_explicit_mapping); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h index b126300e7..24b805a6b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h @@ -14,6 +14,7 @@ void dump_verilog_routing_chan_subckt(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, int pin_index, int side, int x, int y, + int unique_x, int unique_y, /* If explicit, needs the coordinates of the mirror*/ boolean dump_port_type, bool is_explicit_mapping); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c index b70163422..4311c341f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c @@ -638,6 +638,8 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp, des_rr_node_grid_side, des_rr_node->xlow, des_rr_node->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* If src_node == des_node, this is a metal wire */ @@ -723,6 +725,8 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp, des_rr_node_grid_side, mirror_ipin_node->xlow, mirror_ipin_node->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* If src_node == des_node, this is a metal wire */ @@ -1769,6 +1773,8 @@ void verilog_generate_sdc_disable_one_unused_cb(FILE* fp, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), ipin_node->xlow, ipin_node->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* Do not specify direction of port */ fprintf(fp, "\n"); } @@ -1827,6 +1833,8 @@ void verilog_generate_sdc_disable_one_unused_cb(FILE* fp, cur_cb_info->ipin_rr_node_grid_side[side][inode], cur_cb_info->ipin_rr_node[side][inode]->xlow, cur_cb_info->ipin_rr_node[side][inode]->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* Do not specify direction of port */ fprintf(fp, "\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c index 256f281a9..c3df4ed95 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c @@ -187,6 +187,8 @@ void dump_verilog_one_sb_routing_pin(FILE* fp, side, mirror_node->xlow, mirror_node->ylow, + 0, /*Used in newer version*/ + 0, /*Used in newer version*/ FALSE,is_explicit_mapping); /* Do not specify direction of port */ break; } @@ -231,6 +233,8 @@ void dump_verilog_one_sb_routing_pin(FILE* fp, side, cur_rr_node->xlow, cur_rr_node->ylow, + 0, /*Used in newer version*/ + 0, /*Used in newer version*/ FALSE, is_explicit_mapping); /* Do not specify direction of port */ break; case CHANX: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index f3cc2c5b9..8e52d6f5a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -686,6 +686,8 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf cur_cb_info.ipin_rr_node_grid_side[side][inode], cur_cb_info.ipin_rr_node[side][inode]->xlow, cur_cb_info.ipin_rr_node[side][inode]->ylow, + 0, /*Used in newer version*/ + 0, /*Used in newer version*/ FALSE, is_explicit_mapping); /* Do not specify direction of port */ fprintf(fp, ", \n"); } @@ -833,6 +835,8 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, cur_sb_info.opin_rr_node_grid_side[side][inode], cur_sb_info.opin_rr_node[side][inode]->xlow, cur_sb_info.opin_rr_node[side][inode]->ylow, + 0, /*Used in a more recent version*/ + 0, /*Used in a more recent version*/ FALSE, is_explicit_mapping); /* Do not specify the direction of port */ fprintf(fp, ",\n"); }