diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index 562a41f44..6dcc64a70 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -259,8 +259,10 @@ static std::vector<t_pb_graph_pin*> find_routed_pb_graph_pins_atom_net(
  * This function will find the actual routing traces of the demanded net
  * There is a specific search space applied when searching the routing traces:
  * - ONLY applicable to the pb_pin of top-level pb_graph_node
- * - First-tier candidates are in the same port of the source pin 
- * - If nothing is found in first-tier, we find expand the range by considering all the pins in the same type that are available at the top-level pb_graph_node
+ * - First-tier candidates are in the same port of the source pin
+ * - If nothing is found in first-tier, we find expand the range by considering
+ *all the pins in the same type that are available at the top-level
+ *pb_graph_node
  ***************************************************************************************/
 static std::vector<int> find_pb_route_by_atom_net(
   const t_pb* pb, const t_pb_graph_pin* source_pb_pin,
@@ -291,7 +293,9 @@ static std::vector<int> find_pb_route_by_atom_net(
 
   if (pb_route_indices.empty()) {
     for (int pin : candidate_pool) {
-      if (pb->pb_route.at(pin).pb_graph_pin->parent_node->is_root() && is_pb_graph_pins_share_interc(source_pb_pin, pb->pb_route.at(pin).pb_graph_pin)) {
+      if (pb->pb_route.at(pin).pb_graph_pin->parent_node->is_root() &&
+          is_pb_graph_pins_share_interc(source_pb_pin,
+                                        pb->pb_route.at(pin).pb_graph_pin)) {
         pb_route_indices.push_back(pin);
       }
     }
@@ -679,8 +683,12 @@ static void add_lb_router_nets(
     } else if (1 == pb_route_indices.size()) {
       pb_route_index = pb_route_indices[0];
     } else {
-      VTR_LOG_ERROR("Found %d routing traces for net \'%s\' in clustered block \'%s\'. Expect only 1.\n",
-                    pb_route_indices.size(), atom_ctx.nlist.net_name(atom_net_id_to_route).c_str(), clustering_ctx.clb_nlist.block_name(block_id).c_str());
+      VTR_LOG_ERROR(
+        "Found %d routing traces for net \'%s\' in clustered block \'%s\'. "
+        "Expect only 1.\n",
+        pb_route_indices.size(),
+        atom_ctx.nlist.net_name(atom_net_id_to_route).c_str(),
+        clustering_ctx.clb_nlist.block_name(block_id).c_str());
       VTR_ASSERT(1 == pb_route_indices.size());
     }
     t_pb_graph_pin* packing_source_pb_pin =
diff --git a/openfpga/src/utils/pb_graph_utils.cpp b/openfpga/src/utils/pb_graph_utils.cpp
index 4746535fd..5187bbaac 100644
--- a/openfpga/src/utils/pb_graph_utils.cpp
+++ b/openfpga/src/utils/pb_graph_utils.cpp
@@ -71,23 +71,29 @@ t_interconnect* pb_graph_pin_interc(t_pb_graph_pin* pb_graph_pin,
 }
 
 /********************************************************************
- * This function identifies if two pb graph pins share at least one interconnect model
- * The two pins should be in the same type of port, for example, both are inputs.
- * Each pin may drive a number of outgoing edges while each edge represents different interconnect model
- * By iterating over outgoing edges for each pin, common interconnect model may be found 
+ * This function identifies if two pb graph pins share at least one interconnect
+ *model The two pins should be in the same type of port, for example, both are
+ *inputs. Each pin may drive a number of outgoing edges while each edge
+ *represents different interconnect model By iterating over outgoing edges for
+ *each pin, common interconnect model may be found
  *******************************************************************/
-bool is_pb_graph_pins_share_interc(const t_pb_graph_pin* pinA, const t_pb_graph_pin* pinB) {
+bool is_pb_graph_pins_share_interc(const t_pb_graph_pin* pinA,
+                                   const t_pb_graph_pin* pinB) {
   if (pinA->port->type != pinB->port->type) {
     return false;
   }
   std::vector<t_interconnect*> pinA_interc_list;
   for (auto out_edge : pinA->output_edges) {
-    if (pinA_interc_list.end() == std::find(pinA_interc_list.begin(), pinA_interc_list.end(), out_edge->interconnect)) {
+    if (pinA_interc_list.end() == std::find(pinA_interc_list.begin(),
+                                            pinA_interc_list.end(),
+                                            out_edge->interconnect)) {
       pinA_interc_list.push_back(out_edge->interconnect);
     }
-  } 
+  }
   for (auto out_edge : pinB->output_edges) {
-    if (pinA_interc_list.end() != std::find(pinA_interc_list.begin(), pinA_interc_list.end(), out_edge->interconnect)) {
+    if (pinA_interc_list.end() != std::find(pinA_interc_list.begin(),
+                                            pinA_interc_list.end(),
+                                            out_edge->interconnect)) {
       return true;
     }
   }
diff --git a/openfpga/src/utils/pb_graph_utils.h b/openfpga/src/utils/pb_graph_utils.h
index cbe2a096d..e340ba860 100644
--- a/openfpga/src/utils/pb_graph_utils.h
+++ b/openfpga/src/utils/pb_graph_utils.h
@@ -22,7 +22,8 @@ std::vector<t_pb_graph_pin*> pb_graph_pin_inputs(
 t_interconnect* pb_graph_pin_interc(t_pb_graph_pin* pb_graph_pin,
                                     t_mode* selected_mode);
 
-bool is_pb_graph_pins_share_interc(const t_pb_graph_pin* pinA, const t_pb_graph_pin* pinB);
+bool is_pb_graph_pins_share_interc(const t_pb_graph_pin* pinA,
+                                   const t_pb_graph_pin* pinB);
 
 } /* end namespace openfpga */