Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into xt_plocf
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commit
0af0ededd9
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@ -26,6 +26,7 @@ error_codes = {"SUCCESS": 0, "ERROR": 1, "OPTION_ERROR": 2, "FILE_ERROR": 3}
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#####################################################################
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logging.basicConfig(format="%(levelname)s: %(message)s", level=logging.INFO)
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#####################################################################
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# Upgrade an architecture XML file from version 1.1 syntax to version 1.2
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# Change rules:
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@ -13,6 +13,7 @@ This example demonstrates the ``OpenFPGA_Arch`` class which parses the
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Author: Ganesh Gore
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"""
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import math
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import svgwrite
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from svgwrite.container import Group
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@ -674,9 +674,11 @@ def create_yosys_params():
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ys_params["READ_HDL_FILE"] += " ".join(
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[
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"verific",
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(
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"-L " + ys_params["VERIFIC_SEARCH_LIB"]
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if "VERIFIC_SEARCH_LIB" in ys_params
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else "",
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else ""
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),
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standard,
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" ".join([shlex.quote(src) for src in sources]),
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"\n",
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@ -5,5 +5,5 @@ pyverilog
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# Python linter and formatter
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click==8.0.2 # Our version of black needs an older version of click (https://stackoverflow.com/questions/71673404/importerror-cannot-import-name-unicodefun-from-click)
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black==20.8b1
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black==24.3.0
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pylint==2.7.4
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